Abstract: A virtual input queue 80 count frames of data arriving an input port zo in an Ethernet switch 10 using shared memory 50. The shared memory 50 is allocated among 1-N input ports based on either a static or dynamic memory scheme. The static scheme allocates the shared memory 50 evenly among the input ports 20 or based on the input port transmission rate. In the dynamic memory scheme, the range of a virtual input queue's occupancy is divided into an underload zone, a normal load zone and an overload zone. When the virtual input queue is in the underload zone, the input port is kept on and reserved a memory capacity equal to a low threshold. When a virtual input queue is in the normal load zone, the virtual on queue 80 is reserved an additional amount of memory and the link is kept on or is turned on whenever possible. The memory capacity not used or reserved by any input port operating in at least the underload zone and normal load zone is shared by the input ports operating in the overload zone.

Abstract: A time slot assignment circuit capable of performing channel setting with a high efficiency and with a high degree of freedom of channel setting with respect to a large volume of transmission data and in addition having a small circuit scale and low power consumption, provided a time switch provided with a transmission data memory into which transmission data is sequentially written and performing switching in a time domain with respect to the transmission data, a space switch for performing switching in a space domain with respect to an output thereof, an address control memory which outputs a channel setting address for controlling the two switches, and a channel setting information converting unit for converting a channel setting information from the outside to a channel setting address and an accessing address for the memory.

Abstract: A group switching apparatus for multi-channel data is disclosed. It includes a speech memory to temporarily store a time slot to be switched, and a connection memory (CM) to store group connection information. Also, it includes a processor matching unit to interface group connection information provided from an upper processor to the CM and a counter to count a system clock signal and output a read address for the CM. Additionally, an offset generating unit receives group connection information outputted from the CM and generates a first offset value according to a signal representing an ‘ON’ state of group connection, and an adder adds the output of the counter and the output of the offset generating unit and outputting the added value as a read address for the SM.

Abstract: In an STM-network having multiplexer units (1) and a switch (3), for changes in the traffic configuration memories (41,49;43,51) must also be changed, these configuration memories being located in the multiplexer units for controlling reading and writing in intermediate FIFO-type memories (21,23). Unsynchronized writing in the configuration memories (41,49;43,51) is avoided by transmitting suitable signals between the configuration memories, in the suitable case on particular lines (53) provided therefor or otherwise by transmitting particular control messages (rec.) which are located in a time slot having a predetermined position in each transmitted frame.

Abstract: A system for communicating digital data comprises a splitting device (38) for separating an input digital data word, which may be provided by a speech coding arrangement (34,36), into most significant bits and less significant bits. The most significant bit(s) of the digital data word are encoded (40) using a robust signalling alphabet and less significant bit(s) are encoded (42,44) using progressively less robust signalling alphabets. All of the symbols resulting from the encoding are combined (46) and transmitted (48). On reception (50) the received signal is split (52) and demodulated (54,56,58) to provide respective portions of a received data word to a combining means (60). Where the data word was originally provided by speech coding arrangement the received data word may be provided to a resynthesising arrangement (62,64). The signalling alphabets may comprise 2-level modulation, 3,4 and 8-level modulation and/or phase modulation of various degrees.

Abstract: A matrix time switch apparatus for use in a small capacity switching system comprises a matrix having N.times.N voice memories, N being a positive integer greater than 1, wherein each voice memory in each row of the matrix is attached to a corresponding time switch unit in a first group to simultaneously store subscriber data from the corresponding time switch unit in the first group and each voice memory in each column of the matrix is attached to a corresponding time switch unit in a second group to transmit the subscriber data retrieved from each voice memory in each column to the corresponding time switch unit in the second group, and a set of N control memories, wherein each control memory controls the transmission of the subscriber data retrieved in a voice memory selected in the column.

Abstract: A controller for a nonblocking broadcast switching network comprising an input stage, an output stage, and a middle stage. The input stage has N.sub.1 or n.sub.1 r.sub.1 input ports and r.sub.1 switches, where n.sub.1 .gtoreq.2 and r.sub.1 .gtoreq.1 and are integers. The network also includes an output stage. The output stage has N.sub.2 or n.sub.2 r.sub.2 output ports and r.sub.2 switches, where n.sub.2 .gtoreq.2 and r.sub.1 .gtoreq.1 and are integers. There is also a middle stage. The middle stage has m switches, where ##EQU1## The m switches are in communication with the r.sub.1 switches and r.sub.2 switches. The middle stage of m switches has L inputs, where L.gtoreq.r.sub.1 and is an integer, and J outputs, where J.gtoreq.r.sub.2 and is an integer, corresponding to the n.sub.1 input ports and n.sub.2 output ports, x or fewer of the m switches, where 1.ltoreq.x.ltoreq.

Abstract: There is provided a switching system that includes a plurality of input lines for transmitting time division multiplexed data signals, and a conversion means for receiving and converting the respective data signals into a non-time division multiplexed, parallel format, group of N data signals. The system also includes a crosspoint switch having a group of N/K outputs, a first group of N inputs connected to the respective outputs of the conversion means, and a second group of N/K select or control inputs. In addition, a control means includes connection memory that constitutes a means for addressing the crosspoint switch at the select inputs, and the outputs of a group of N/K multiplexers are connected to the select inputs and the inputs of the group of N/K multiplexers are connected to the control means.

Abstract: A time-slot interchanger includes first and second time switches and a space switch installed between the first and second time switches. The first time switch includes a first part for supplying data, which is produced by adding a blank region to input data supplied to the first time switch, in n systems (n is an integer), in parallel to the space switch. And the second time switch includes a second part for supplying output data, which is produced by removing the blank region from data received in the n systems and in parallel from the space switch.