Abstract: In one example, an optical network access switch includes independent first and second banks of individually selectable optical inputs, as well as independent first and second groups of individually controllable optical outputs. A first multiplexer is connected to the optical inputs of the first bank and the optical outputs of the first group, and a second multiplexer is connected to the optical inputs of the second bank and the optical outputs of the second group. Finally, a configuration interface communicates with the first and second multiplexers and receives a switching command which specifies the connection/disconnection of an optical output to/from an optical input.

Abstract: Methods and apparatus for scheduling transfer of data bursts in a network comprising electronic edge nodes interconnected by bufferless core nodes are disclosed. Each edge node comprises a source node and a sink node, and each core node comprises several bufferless space switches operating in parallel. Each space switch has a master controller and one of the master controllers in a core node functions as a core-node controller. Each master controller has a burst scheduler for computing a schedule for transfer of data bursts, received from source nodes, to respective destination sink nodes. A core-node controller receives requests for bitrate allocations from source nodes and assigns each request to one of the master controllers of the core node. In one embodiment, a scheduler determines schedules for concatenated reconfiguration periods. In another embodiment, parallel schedulers determine schedules for overlapping reconfiguration periods.

Abstract: A reconfigurable compute engine interconnect fabric includes a reconfigurable interconnect layer (24, FIG. 2) between an application layer (22) and a physical layer (26) which identifies the input and output pins for the engine and their functions.

Abstract: A large high capacity switch is provided for a communication network which is constructed from a network of smaller switches. Data is fragmented into fixed sized cells and the cells of a traffic flow are aggregated by grouping cells to form larger yet uniform units of information transfer. The groups are transmitted synchronously and in parallel to increase the effective bandwidth of information transfer.

Abstract: A high capacity distributed switching system comprises electronic edge nodes connected to a balanced bufferless switch which may be electronic or optical. The balanced bufferless switch comprises a balanced connector and a switch fabric. The balanced connector comprises an array of temporally cyclic rotator units having graduated rotation shifts and each having a prime number of output ports. The switch fabric may be a mesh interconnection of switch modules. Due to the use of the balanced connector, establishing a path through the switch fabric requires at most a second-order time-slot matching process for a high proportion of connection requests with a much reduced need for a third-order time-slot matching process required in a conventional mesh structure.

Abstract: A system and method for electronically identifying connections established through a cross-connect system provides for identification of all hard-wired and temporary patch connections, and any modifications made to same. Connection identification and status information is acquired in near real-time and stored in a database which is accessible by a user through a graphical user interface (GUI). The TRACE or lamp wires which connect respective pairs of cross-connect circuits are utilized in an unconventional manner so as to form a scanning bus. The information signal paths established through the cross-connect circuits remain undisturbed. A scanning signal is communicated between each pair of cross-connected circuits over the TRACE conductor. In the event a patch cord is used to temporarily redirect a signal connection, the scanning signal is transmitted over the shield or sleeve conductor of the patch cord. The scanning signal provides identification and other information concerning the transmitting circuit.

Abstract: A multi-grained high-performance rotorswitch scaling to high capacities is disclosed. In one embodiment, the rotorswitch comprises common-memory switch modules each of which cyclically accessing each other switch module for an access interval of a predefined value and transmitting, during the access interval, a number of data segments collectively having a duration not exceeding the access interval. The data segments transmitted to a given switch module during an access interval may be destined to several other switch modules. The switch modules may cyclically connect to each other using a plurality of rotators of the same rotational speed. In another embodiment, the rotorswitch uses rotators of different speeds connecting common-memory switch modules so that each of the switch modules has parallel cyclic access, possibly at different cyclic rates, to each other switch module.

Abstract: There is provided a method for routing packets on a linear of N processors connected in a nearest neighbor configuration. The method includes the step of, for each end processor of the array, connecting unused outputs to corresponding unused inputs. For each axis required to directly route a packet from a source to a destination processor, the following steps are performed. It is determined whether a result of directly sending a packet from an initial processor to a target processor is less than or greater than N/2 moves, respectively. The initial processor is the source processor in the first axis, and the target processor is the destination processor in the last axis. The packet is directly sent from the initial processor to the target processor, when the result is less than N/2 moves. The packet is indirectly sent so as to wrap around each end processor, when the result is greater than N/2 moves.

Abstract: The selection of the spatial mode together with modulation and encoding schemes based on channel condition measurements requested from MS forms a basis for selecting a best transmission data rate in a wireless link in every channel conditions. A method and network element comprising multiple-input multiple-output (MIMO) capable antenna technology allows the use of a best transmission data rate in the channel if selection of transmission mode has been made correctly. The thresholds for transmission mode selections are pre-determined and compared to instantaneous channel quality information. The practical MIMO solution based on correct selection procedure provides also continuous sufficient channel condition for terminal users when the user moves from LOS situation to NLOS situation.

Abstract: A packet switch that scales gracefully from a capacity of a fraction of a terabit per second to thousands of terabits per second is disclosed. The packet switch comprises edge nodes interconnected by independent switch units. The switch units are arranged in a matrix having multiple rows and multiple columns and may comprise instantaneous or latent space switches. Each edge node has a channel to a switch unit in each column and a channel from each switch unit in a selected column. A simple path traversing only one of the switch units may be established from each edge node to each other edge node. Where needed, a compound path comprising at most two simple paths may be established for any edge-node pair. In a preferred configuration, the switch units connect at input to orthogonal sets of edge nodes. A distributed control system expedites connection-request processing.

Abstract: A switching node comprises edge nodes interconnected by independent switch units. The switch units are arranged in at least one switch plane and the switch units of each switch plane are arranged in a matrix having several rows and several columns. Each edge node has a channel to a switch unit in each column in each switch plane and a channel from each switch unit in a selected column in each switch plane. Simple paths, each traversing only one switch unit in a switch plane, may be established for any directed edge-node pair. Additionally, several non-intersecting compound paths, each comprising at most two simple paths, may be established for any edge-node pair. A significant proportion of traffic may be routed through simple paths. The switching node employs distributed control scheme and scales gracefully from a capacity of a fraction of a terabit per second to thousands of terabits per second.

Abstract: The creation of a variety of upgradeable scalable switching networks are set forth including multistage switching networks as well as novel multidirectional architectures. Systems and methods exploiting the properties such as fault tolerance, upgradeability with out service disruption and path redundancy are incorporated into a variety of systems. A wide range of methods for upgrading and reconfiguration the scalable switching networks are presented including manifestations of implementations of said networks and said methods. Methods for designing new upgradeable scalable switching and the novel architectures derived thereof including architectures built from the redundant blocking compenstated cyclic group networks are set forth.

Abstract: A wide-coverage, high-capacity, switching network is modeled after a classical space-time-space switch. In the switching network, each of the space stages comprises geographically distributed optical space switches and the time stage comprises a plurality of geographically distributed high-capacity electronic switching nodes. User-access concentrators, each supporting numerous users, access the network through ports of the distributed optical space switches. A user-access concentrator is a simple device which need only have a single access channel to access the network, although two or more access channels may be used. Such a user-access concentrator can communicate with a large number of other user-access concentrators by time-multiplexing the access channel.

Abstract: A system and method for transmitting data in multiple-branch transmitter-diversity OFDM systems is presented. In one embodiment, an approach is taken where an inverse Fourier transform (IFT) is performed on data prior to encoding the data for transmission in the multiple-branch transmitter-diversity system. In another embodiment an IFT is performed on data prior to encoding the data using a space-time block code (STBC) algorithm.

Abstract: Network data switching comprises receiving a cell, associating the cell with a destination port, selecting an egress link that has been soft configured to be associated with the destination port, and switching the cell to the selected egress link. A network switch comprises an ingress link configured to receive a cell and a switch circuit coupled to the ingress link, configured to associate the cell with a destination port, to select an egress link that has been soft configured to be associated with the destination port, and to switch the cell to the egress link.

Abstract: Techniques for multi-stage switching in network elements are provided. The switching fabric can include three stages and as connections are being made through the stages, the connections are selected to minimize the difference in the number of signals between different stages. Additionally, the switching fabric can include six identical chips where pairs of chips are utilized for each of the three stages.

Abstract: A crossbar switching circuit and operating method thereof for coupling a plurality of source providers to a plurality of source consumers based on the request of the source consumer are provided. The crossbar switching circuit includes a plurality of source consumer terminals coupled to the source consumers respectively, a plurality of source provider terminals coupled to the source providers respectively, a plurality of first counters and a plurality of second counters. Wherein, each source consumer terminal has one first counter and one second counter. The first counter indicates a current latency state of the resource requested by the corresponding source consumer. The second counter indicates a current bandwidth state of resource requested by the corresponding source consumer. In addition, the connecting states between the source consumer terminals and the source provider terminals are determined based on the states of the first counters and the second counters.

Abstract: A multiple-domain processing system includes a multi-dimensional switching fabric to provide intra-domain and inter-domain communication within the system.

Abstract: A method for determining a combination of data for transfer comprises counting the number of candidates in data for candidates of a data transfer request for each row as the number of candidates at lattice points of a lattice composed of N rows×N columns, searching for a minimum value out of count values equal to or greater than 1, selecting and storing one row showing the minimum value. Regarding the candidates in the selected row, the method also comprises counting the number of candidates in each column where candidates exist, searching for a minimum value, selecting and storing one column, deleting all candidates on the row and the column determined, and repeating these processes until no more candidates exist to determine combinations of rows and columns stored at a point of time when no more candidates exist.

Abstract: A network for interconnecting processing element nodes which supports rich interconnection while having a number of switching elements which is linear in the number of processing elements interconnected. Processing elements connect to the lowest level of the tree and the higher levels of the tree make connections between the processing elements. The processing elements may be laid out in a two dimensional grid and one or more horizontal and vertical trees may be used to connect between the processing elements with corner switches used to connect between the horizontal and vertical trees. The levels of the tree can be accommodated in multiple layers of metalization such that the entire layout requires a two-dimensional area which is linear in the number of processing elements supported.

Abstract: A system and method for aggregating multiple radio interfaces into a single logical bridge interface with reference to an IEEE 802.11 Wi-Fi network and an Ethernet local area network. The system includes a master switch with multiple associated wireless modules. Each master switch wireless module selectively broadcasts an associated connection signal. The master switch has an associated aggregation port, which is in data communication with each of the master switch wireless modules and selectively routes data among the master switch wireless modules. The system also includes a slave switch with multiple associated wireless modules. Each of the slave switch wireless modules receives one associated connection signal and establishes a wireless data communication link with the broadcasting master switch. The slave switch also includes an associated aggregation port, which is in data communication with each of the slave switch wireless modules, selectively routes data among the slave switch wireless modules.

Abstract: Described are techniques used in a computer system for handling data operations to storage devices. A switching fabric includes one or more fast paths for handling lightweight, common data operations and at least one control path for handling other data operations. A control path manages one or more fast paths. The fast path and the control path are utilized in mapping virtual to physical addresses using mapping tables. The mapping tables include an extent table of one or more entries corresponding to varying address ranges. The size of an extent may be changed dynamically in accordance with a corresponding state change of physical storage. The fast path may cache only portions of the extent table as needed in accordance with a caching technique. The fast path may cache a subset of the extent table stored within the control path. A set of primitives may be used in performing data operations. A locking mechanism is described for controlling access to data shared by the control paths.

Abstract: A router has N1 local signal input terminals for connection to respective local signal sources for supplying respective local input signals, a local output interface including M1 local signal output terminals, and an input expansion terminal. A signal received at any one of the N1 local signal input terminals can be routed selectively to any one or more of the M1 local signal output terminals and a signal received at the input expansion terminal can be routed selectively to any one or more of the M1 local signal output terminals. An input signal received at a local signal input terminal is delayed relative to an input signal received at the input expansion terminal by a selectively adjustable amount to achieve a predetermined time relationship between the input signals at the local output interface.

Abstract: A method for selectively storing information received from a broadcast signal is disclosed. The method comprises the steps of; receiving and identifying a broadcast message, the message comprising a plurality of characters; comparing each character of the received message with a start of tag (SOT) identifier stored in a memory; if a character received in the received message is determined to match the SOT identifier stored in the memory then comparing each of the subsequent characters in the received message with an end of tag (EOT) identifier stored in the memory determining if the received message contains both SOT and EOT identifiers; and storing the message in a storage unit in dependence on the result of the determination.

Abstract: A bit-rate-transparent electrical space-division switching matrix is employed in an optical cross-connect and the input/output stage is constructed from simple, broadband optical receivers and transmitters. Since the switching matrix operates in unclocked manner, i.e. its switching function is not based on internal bit timing and frame timing, arbitrary signals can be switched though transparently at almost any bit rate, independently of the protocol-type being used. The inputs and outputs likewise operate fully independently of bit rate and protocol, since they only implement an O/E conversion or O/E conversion. By virtue of this structure, a simply constructed but extremely powerful optical cross-connect is created that can be employed equally for all types of optical signals within the stipulated wavelength-range.

Abstract: Rather than restricting a stream of data to a single channel within a multi-channel link between a source node and a core node, each channel is divided into time slots and the stream of data is distributed among these time slots in several channels. However, to ease the management of switching the stream of data at the core node, simultaneous time slots in each channel may be arranged into “stripes,” such that a particular stripe may only include data segments having a common destination. Switching these stripes of data at the core node requires that the source of such a stripe arrange the frame according to a frame structure provided by the core node. Advantageously, where the frame is striped across an entire link, the present invention provides for a variation on link switching that approaches the topological reach of TDM switching while maintaining relatively straightforward operation at the core node.

Abstract: A method and apparatus for scheduling the transfer of data bursts in a network comprising electronic edge nodes interconnected by bufferless core nodes are disclosed. Each edge node comprises a source node and a sink node, and each core node comprises several bufferless space switches operated in parallel. Each source node is connected to at least one core node by an upstream link that includes multiple upstream channels. Each core node is connected to at least one sink node by a downstream link that includes multiple downstream channels. Any of the space switches can have either an electronic fabric or a photonic fabric. Each space switch has a master controller, and one of the master controllers in a core node is designed to function as a core-node controller in addition to its function as a master controller. Each master controller has a burst scheduler operable to compute a schedule for the transfer of data bursts, received from source nodes, to destination sink nodes.

Abstract: A technique synchronizes a crossbar switch fabric of a network switch having a plurality of modules configured to transmit and receive data at high speeds. The crossbar switch fabric resides on a switch module and operates on fixed-size cells received at its input ports from line card modules over high-speed serial communication paths of the switch. To eliminate resynchronization between the modules after each serial communications path traversal, each module is allowed to operate within its own clock domain, thereby forcing the entire resynchronization task upon a receive data path of the switch module. Although this results in resynchronization of a “large magnitude”, the task only needs to be performed once and entirely on the switch module.

Abstract: Described are techniques used in a computer system for handling data operations to storage devices. A switching fabric includes one or more fast paths for handling lightweight, common data operations and at least one control path for handling other data operations. A control path manages one or more fast paths. The fast path and the control path are utilized in mapping virtual to physical addresses using mapping tables. The mapping tables include an extent table of one or more entries corresponding to varying address ranges. The size of an extent may be changed dynamically in accordance with a corresponding state change of physical storage. The fast path may cache only portions of the extent table as needed in accordance with a caching technique. The fast path may cache a subset of the extent table stored within the control path. A set of primitives may be used in performing data operations. A locking mechanism is described for controlling access to data shared by the control paths.

Abstract: A packet switch for switching cells comprising fixed-size data packets.

Abstract: A grooming switch comprises plural input ports for receiving multi-time-slot input signals and plural output ports for forwarding multi-time-slot output signals. At least five switching stages alternate between time switching and space switching. The first stage is connected to the input ports, and the last stage is connected to the output ports. Each intermediate stage is connected to two other stages. Collectively, these stages perform compact superconcentration of the input signals, copying and distribution of the compact superconcentrated signals, and unicast switching of the distributed signals to form the output signals, resulting in a grooming switch that is rearrangeably non-blocking for arbitrary multicast traffic.

Abstract: A centralized arbitration mechanism provides that a router switch fabric is configured in a consistent fashion. Remotely distributed packet forwarding modules determine which data chunks are ready to go through the optical switch and communicates this to the central arbiter. Each packet forwarding module has an ingress ASIC containing packet headers in roughly four thousand virtual output queues. Algorithms choose at most two chunk requests per chunk period to be sent to the arbiter, which queues up to roughly 24 requests per output port. Requests are sent through a Banyan network, which models the switch fabric and scales on the order of NlogN, where N is the number of router output ports. Therefore a crossbar switch function can be modeled up to the 320 output ports physically in the system, and yet have the central arbiter scale with the number of ports in a much less demanding way. An algorithm grants at most two requests per port in each chunk period and returns the grants to the ingress ASIC.

Abstract: Low speed switches operated under the common control of a global scheduler can be used to switch high speed data while preserving packet ordering if the incoming packets are queued in a temporal order. By operating several low speed switches in parallel, a high-speed switching capacity can be realized.

Abstract: A switch of a network. The switch includes a port card for sending and receiving packets to and from the network. The switch includes a plurality of fabrics connected to the port card. Each fabric switches portions of the packet. Each fabric has a queue in which portions of the packet are stored. The switch includes a first dequeuer for dequeueing the portions of the packet. The switch includes a second dequeuer for dequeueing the portions of the packets. The switch includes a state machine for controlling when the first and second dequeuers dequeue the portions of the packet. A method for sending packets with a switch of a network. The method includes the steps of dequeueing with a first dequeuer of a fabric portions of a packet from a queue of the fabric. Then there is the step of dequeueing with a second dequeuer of the fabric the portions of the packet from the queue after in the first dequeuer has dequeued the portions of the packet.

Abstract: A switch element is configured to extend communications between data lines. The switch element includes a set of ingress devices, a set of center stage devices, and a set of egress devices. Each center stage device is connectable to each ingress device and to each egress device. Each ingress device connects to a corresponding egress device across one of the center stage devices. The center stage switch can be selectively actuated to accommodate a new ingress or egress device across the center stage switch.

Abstract: A self-routing switching network composed of sorting cells interconnected as a bit-permuting network and, in particular, as a banyan-type network, and the concomitant general self-routing control mechanism for routing packets over such networks. The self-routing mechanism includes a theoretical approach of determining the routing tag of a packet from the guide of the network and the destination address of the packet, and accomplishes the self-routing of packets by the sorting of packets.

Abstract: A bit-rate-transparent electrical space-division switching matrix is employed in an optical cross-connect and the input/output stage is constructed from simple, broadband optical receivers and transmitters. Since the switching matrix operates in unclocked manner, i.e. its switching function is not based on internal bit timing and frame timing, arbitrary signals can be switched though transparently at almost any bit rate, independently of the protocol-type being used. The inputs and outputs likewise operate fully independently of bit rate and protocol, since they only implement an O/E conversion or O/E conversion. By virtue of this structure, a simply constructed but extremely powerful optical cross-connect is created that can be employed equally for all types of optical signals within the stipulated wavelength-range.

Abstract: A system and method for interleaving symbols to facilitate compatibility between serializer/deserializer (SerDes) units operating at different data rates multiplexes duplicates of a parallel data stream into a fast data rate serial data stream to form a serial data steam at a psuedo-slow data rate which can be received by a SerDes unit operating at the slow data rate. The psuedo-slow data rate serial data stream can also be received by a SerDes operating at the fast data rate by sampling each bit multiple times and demultiplexing the samples into duplicates of the parallel data stream.

Abstract: A self-routing multicast switching network composed of bicast cells interconnected as a bit-permuting network and, in particular, as a banyan-type network, and the concomitant general self-routing control mechanism for multicasting the packets over such networks. The self-routing mechanism includes the approach of determining the routing tag of a packet from the guide of the network and the destination addresses of the packet, and accomplishes the self-routing of the packets by the sorting of the packets.

Abstract: A switch element is configured to extend communications between data lines. The switch element has an ingress stage, a center stage, and an egress stage. The switch element connects to two sets of data lines. Time slots are identified on each set of data lines. Time slots from one set of data lines are assigned to ingress and egress edges on a center stage device. The time slots from each set of data lines are also mapped to one another, so that each time slot in one set of data lines is mapped to only one corresponding time slot in the other set of data lines.

Abstract: Broadband switching including the implementation of and control over a massive sub-microsecond switching fabric. To effect the attributes of the switching fabric, conditionally nonblocking components are used a building-blocks in an interconnection network which is recursively constructed. The properties of the interconnection network are preserved during each recursion to thereby configure the massive switching fabric from scalable circuitry.

Abstract: A sub-network of a communication network includes four nodes, with each node having two input ports and two output ports. The first node and the fourth node each link both of their input ports and one of their output ports to other nodes of the sub-network, with each of their remaining output ports operable to send signals outside of the sub-network. The second and third nodes link both of their output ports and one of their input ports to other nodes of the sub-network while each of their remaining input ports is operable to receive signals from outside of the sub-network.

Abstract: A switch fabric for routing data has a switching stage configured between an input stage and an output stage. The input stage forwards the received data to the switching stage, which routes the data to the output stage, which transmits the data towards destinations. Each input device of the input stage transmits bids to the crossbar devices of the switching stage to request connections through the switching stage for routing the data to the output devices of the output stage. In one aspect, each crossbar device has (1) a bid arbitrator that determines whether to accept or reject each received bid, wherein, in response to a collision between multiple bids, the bid arbitrator accepts two or more of the colliding bids in a single time slot; and (2) memory for storing one or more accepted cells for the same output device, wherein the crossbar device can transmit grant signals for two or more accepted bids for the same output device in a single time slot.

Abstract: The invention relates to a switching device comprising a plurality of inputs and outputs which are interconnected by a matrix of interconnection points for transmitting electric signals supplied from the inputs to the outputs via transmission lines in accordance with a predefined switching plan. The device comprises a control member for controlling the operation of the matrix with control signals and local decoding for locally decoding the control signals and for deducing the switching state of the interconnection points. Application: packet switching in optical transmissions.

Abstract: A self-routing data switching system is disclosed. The data switching system includes a plurality of repetitive switching matrix planes, each of which is electrically connected between a less number of input terminals and a larger number of output terminals, thereby reducing the head-of-line blocking effect. Each switching matrix plane includes a switching element array interconnected between the input ports and the output ports for determining whether the data packet from an input port can be transmitted to a designated output port. The data switching system further includes a plurality of pre-processors to manage the input timing of data packets into the switching matrix array in order to avoid output conflict.

Abstract: A crossbar switch system with redundancy has N+1 cross-bar switches. A first cross-bar switch has first outputs of each of a plurality of nodes applied to N input terminals thereof, an (N+1)th cross-bar switch has Nth outputs of each of the nodes applied to N input terminals thereof, and second to Nth (Ith) cross-bar switches each have first to Nth selection circuits, which are provided at respective input terminals thereof, to each of which are input mutually adjacent (I?1)th and Ith outputs among outputs of each of the nodes. Each (Jth) node has N selection switches, which are provided at input terminals thereof, to each of which are input Jth outputs of two mutually adjacent cross-bar switches among the first to (N+1)th cross-bar switches. In response to a selection control signal output from a failure processing circuit that executes crossbar switch failure processing, each of the selection circuits selects and outputs one of its two inputs.

Abstract: There is provided a method for routing packets on a linear array of N processors connected in a nearest neighbor configuration. The method includes the step of, for each end processor of the array, connecting unused outputs to corresponding unused inputs. For each axis required to directly route a packet from a source to a destination processor, the following steps are performed. It is determined whether a result of directly sending a packet from an initial processor to a target processor is less than or greater than N/2 moves, respectively. The initial processor is the source processor in the first axis, and the target processor is the destination processor in the last axis. The packet is directly sent from the initial processor to the target processor, when the result is less than N/2 moves. The packet is indirectly sent so as to wrap around each end processor, when the result is greater than N/2 moves.

Abstract: A data storage system wherein end-user data is transferred between a host computer and a bank of disk drives through an interface. The interface includes a memory and a plurality of directors interconnected through an interface state data bus and a plurality of end-user data busses. At least one front-end one of the directors is in communication with the host computer and at least one rear-end one of the directors is in communication with the bank of disk drives. The interface state data bus section is in communication with: both the at least one front-end one and the at least one rear-end one of the directors; and to the memory. Each one of the plurality of end-user data buses has a first end coupled to a corresponding one of the plurality of directors and a second end coupled to the memory.

Abstract: One embodiment of the present invention is an arrangement for establishing connectivity between the inputs and outputs of n ports in a switching system includes first and second matrices of cross points and a control circuit. The first matrix includes n×n cross points, each first matrix cross point establishing a unilateral path between two of the n ports. The second matrix includes n×n cross points, each second matrix cross point establishing a unilateral path between two of the n ports. The control circuit is associated with a first cross point of the first matrix and a complementary cross point of the second matrix, the first cross point operable to establish a unilateral path from a source port (i) to the destination port (j), the complementary cross point operable to establish a unilateral path from the destination port (j) to the source port (i).

Abstract: A data communication system and method are provided to communicate in a multiprocessor interconnection network or other network. In one embodiment, the present system includes a number of logical circuits that are located in a number of nodes interconnected in a multiprocessor interconnection network. In this regard, the nodes include at least one source node, at least one destination node, and at least one intermediate node. The logical circuits include source logic located in the source nodes to identify data routes between respective source nodes and destination nodes through the one or more intermediate nodes. The data routes are specified by at least one destination port value and a current hop count that are attached to a data packet to be transmitted between respective source and destination nodes.