Abstract: A informational element (IE) is provided which permits the user to assign a precedence level to a call. A precedence/preemption connection admission control (P/P CAC) for use with any bandwidth allocation algorithm is also provided for processing a virtual circuit connection (VCC) request having an assigned precedence level, and for preempting one or more VCCs when a VCC request having a relatively higher precedence level is received at an ATM switch. Preferably, a resource allocator containing two databases, one listing all active virtual circuit connections and a second listing all preempted virtual circuits, is provided for storing the call parameters of preempted VCCs. According to a preferred embodiment, preempted VCCs may be reestablished. Reestablishment occurs according to various criteria. In addition, a second embodiment of a P/P CAC is provided in which active VCCs identified for preemption are buffered until the requested VCC is accepted by a downstream ATM switch.

Abstract: A plurality of cell switches that operate at a basic switching rate are provided, and a unit including (FIFO buffers) for queuing cells from the transmission line are provided in correspondence with respective ones of the cell switches. Cells from the transmission line are demultiplexed and written to the prescribed FIFO buffer by a cell demultiplexer, cells are read out of each FIFO buffer at the basic switching rate and entered into the corresponding cell switch, and cells switched by each of the cell switches are multiplexed and sent to a transmission line by a multiplexer.

Abstract: Methods and apparatus for processing cells in an asynchronous transfer mode (ATM) communication system. A group of bits comprises a primary scoreboard indicative of the scheduling status for cell time slots in a periodic container of cells, with each bit indicating the availability of a corresponding cell time slot. A connection identifier (ID) table is maintained with each location in the table corresponding to one of the cell time slots and thus a single primary scoreboard bit. A cell scheduling instruction specifies a connection ID for a virtual connection on an ATM transmission link. A processor searches the primary scoreboard until a bit corresponding to an available cell time slot is located, reserves the located cell slot by setting the corresponding bit, and stores the connection ID in the corresponding location in the connection ID table. A cell servicing instruction specifies an address in the connection ID table.

Abstract: A call reception control circuit 1 sets each guaranteed band width required for assuring communication quality of the respective band width demand classes in the corresponding N counter Nc, Ntv and Nv at a certain time interval Ts. The call reception control circuit 1 also sets values defined by the ratio of the W counter Wabr and Wubr of the respective best effort class to use the remained band width. The value 1 is subtracted from each value of the N counter Nc, Ntv and Nv and W counter Wabr and Wubr at every output of the cell from the corresponding class. A priority control process circuit 2 outputs cells to an output channel 3 according to priority levels giving a priority to the band width demand class having the value of the N counter not set to 0 over the band width demand class and the best effort classes having the value of the N counter set to 0.

Abstract: An apparatus for controlling network switches which includes a central network controller node having a call task for booking and executing calls by setting up the switches that interconnect a first terminal and a second terminal and a switch master task for receiving commands to control all of the switches in the network, maintaining status information for all of the switches and distributing requests for particular connections, a switch controller task for converting control commands for a generic switch into commands that control a hardware switch and a codec connected to a port thereof, wherein in response to a client request, the central network controller communicates with the switch controller task to create a generic switch and to convert commands for the generic switch to commands for the switch and the codec so as to permit communication between a digital terminal and an analogue terminal.

Abstract: Methods for performing origination and termination processes to control reserved semi-permanent virtual path connections in an asynchronous transfer mode virtual path switching system. A service can flexibly be provided based on semi-permanent virtual path connection information for a desired time in response to a reserved semi-permanent virtual path registration command received through an operator interface during the operation of the system. Also, the reserved semi-permanent virtual path connections can be controlled up to 256 per subscriber link of 155 Mbps class. A subscriber service using time is designated and resources in a network are occupied only for the designated time. Therefore, a plurality of subscribers are set at different service time zones in such a manner that the network resources can be utilized at the maximum at each service time zone.

Abstract: Method for the transmission of information packets between a source LEC of a first ELAN and a destination LEC of a second ELAN, having the following method steps: determination of the destination ATM address by transmission of an address resolution request of the source LEC to the second ELAN via a CLS wideare network offering a connectionless service and resolution of the destination MAC address in the second ELAN into the appertaining ATM address; initiation of a connection setup between source LEC and destination LEC via an ATM network ranking higher than the first ELAN and the second ELAN upon employment of the identified destination ATM address; and transmission of the information packets via the higher-ranking ATM network. In one exemplary embodiment, the determined ATM address is transmitted to the first ELAN via the CLS wide-area network as address resolution response and is transmitted thereat to the source LEC, and the source LEC initiates a connection setup to the destination LEC.

Abstract: A method and apparatus for an in-home communication system based on the use of a telecommunications terminal of a Fiber-to-the-Curb (FTTC) network is described. In this system signals are sent from a first device in a home to the FTTC terminal over a subscriber coaxial cable network, and routed from the telecommunications terminal back to the home, where they are received by a second device in the same home. Signals are routed back to the home at the telecommunications terminal by recognizing a particular address which corresponds to in-home signals or by timing information. In the event that the information is contained within Asynchronous Transfer Mode (ATM) cells, the Virtual Path Identifier (VPI) field of the ATM cells can be used to indicate that cells are to be redirected back to the home.

Abstract: A status queue in a host and a control queue in a segmentation and reassembly (SAR) subsystem are on opposite sides of a host bus in a control plane. Buffer descriptors in the host and the SAR and buffers in the host are in a data plane. To transfer cell payloads to a first line interfacing the SAR, the host writes the SAR that it has such cell payloads. The host writes the host buffer descriptors into the control queue to obtain the transfer of the buffer payload to the first line. The SAR writes the status queue when the transfer has been completed. To transfer cell payloads to the host memory, the host writes into the control queue the address of the buffers to receive the payload from the SAR. The SAR then writes the buffer descriptors to the status queue to obtain the transfer of the cell payloads to the buffers. Each of the control and status queues may be respectively considered to constitute two (2) control queues and two (2) status queues.

Abstract: A multiported LAN switch comprised of legacy local area network ports and ATM ports. Each ATM port comprising a hardware forwarding engine for bridging LAN frames from the LAN ports to the ATM port. The hardware forwarding engine converts layer 2 protocols between the dissimilar ports expediently, without requiring intervention by a microprocessor. A substantial performance gain is attained compared to microprocessor controlled format converters. Both LAN emulation and virtual LANs are supported.

Abstract: An ATM transmitter distributes an ATM transmission process function to plural electronic circuit packages and performs transmission process by forming routes between the plural circuit packages. The routes can be flexibly varied while a configuration of a variety of process functions are managed. The cell distribution section which has plural input and output terminals connected to respective electronic circuit packages forms a route among respective ones of the arbitrary input and output terminals so that receive ATM cells are input and output between respective electronic circuit packages. Process functions are arranged for each electronic circuit package. The function configuration of all the electronic circuit packages is previously set. Thus, a route formation is indicated to the cell distribution section. In other case, input and output terminals for each route are sequentially arranged along the route. The control order of receive ATM cells is previously set.

Abstract: A communication network system comprising pairs of connection lines (3) composed of input lines and output lines, a switchboard (1) which relays a packet received from one of the input lines to one of the output lines specified by the header information contained in the packet, and terminals (2) connected to the switchboard through the connection lines (3). Each terminal (2) is provided with a communication controller (222 or 23a) which converts call control messages to be transmitted to the switchboard (1) and information messages to be transmitted to other terminals into packets of predetermined formats, sends them through the input lines, and converts packets received through the output lines and the switchboard (1) into messages. A master terminal (2a) which is one of the terminals is provided with a call processing program (224) for performing the call control of the switchboard (1).

Abstract: An input-buffered multipoint switch having input channels and output channels includes multi-level request buffers, a data path multiplexer, and a scheduler. The switch has a distinct multi-level request buffer associated with each input channel and each request buffer has multiple request registers for storing data cell transfer requests of different priorities. The multi-level request registers are linked in parallel to the scheduler to allow arbitration among requests of different input channels and different priority levels. The preferred arbitration process involves generating masks that reflect the output channels required by the same priority level requests. Utilizing masks to arbitrate between multiple requests in an input-buffered switch reduces arbitration cycle time and minimizes HOL blocking.

Abstract: In a client having (i) an upstream device driver for controlling an upstream device which sends data to a server; (ii) a downstream device driver for controlling a downstream device which receives data from the server; and (iii) a dialer application for establishing an upstream connection using the upstream device driver, the present invention initiates a connection in response to upstream traffic generated by an application including the steps of receiving the upstream traffic in the downstream device driver; constructing a dial packet in the downstream device driver in response to the upstream traffic; transferring the dial packet from the downstream device driver to the dialer application; and, issuing a call command to the upstream device driver.

Abstract: This relates to a voice signal transmitting method and exchange system using this whereby excellent speech quality can be maintained by reducing the celling delay on voice compression and celling/decelling delay on relay-exchanging. Voice compression/framing/celling units 20A, 20B, 20C corresponding to ATM exchanges 10A, 10B, 10C within the network are provided. When a call is made between telephone set 50-1 and telephone set 50-3 or 50-5, voice compression/framing/celling unit 20A distributes the voice signal that is input from PBX 30A to each remote party PBX 30B, 30C; the voice signal distributed to each of these remote stations is compressed, and, at fixed time intervals, only busy channels are multiplexed on to a variable-length TDM frame, this multiplexed frame being then converted into ATM cell form at each PBX 30B, 30C and transferred from ATM exchange 10A to ATM exchange 10B or 10C.

Abstract: An idle address controller for a shared buffer type ATM switch controls the addresses of output cells in a common memory to be stored directly in an idle address buffer without passing through the conventional idle address delay controller, by improving the idle address control scheme of a unit switch. The idle address controller includes an idle address control signal generator for generating idle address control signals based on the buffer length information from counters, idle address control signal buffers for storing the idle address control signals, and an idle address control signal multiplexer. Therefore, the idle addresses can be efficiently provided, and this mechanism lowers cell loss and reduces required memory capacity.

Abstract: An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory.

Abstract: An asynchronous transfer mode scheduler schedules connection utilizing available bit rate (ABR) modes of traffic, unspecified bit rate (UBR) modes of traffic, variable bit rate (VBR) modes of traffic, and constant bit rate (CBR) modes of traffic. The scheduler communicates with a dynamic schedule table which includes a programmable number of slots. Each slot includes a CBR entry, a tunnel entry, and a number of VBR entries. The VBR entries store a slot tail pointer which indicates the end of a linked list. The scheduler utilizes the single bucket algorithm or dual bucket algorithm to dynamically schedule connections on future slots. The scheduler places connections using the VBR mode of traffic in a priority queue and takes the highest priority connection in the priority queue for transmission on the network.

Abstract: A telephone and video telecommunications distribution network (10) includes a telecommunications switch (12) and an optical network unit configuration (20b). The telecommunications switch (12) receives telephony traffic at a common control section (14) and video information at a video bank section (18). The video bank section receives telephony traffic from the common control section (14) and places the telephony traffic into telephony ATM cells. Video information is carried in video ATM cells. The Video Dank section (18) multiplexes telephony ATM cells and video ATM cells onto a fiber optic communication link for transport to the optical network unit configuration (20b). The optical network unit configuration (20b) includes a full service optical line unit (80) that segregates telephony ATM cells from video ATM cells. The full service optical line unit (80) transfers video ATM cells to a video brick (31) for processing.

Abstract: An apparatus and a method are disclosed for arbitrating between streams of ATM cells, or sources for a connection, on multiple input port processors vying for an opportunity to be transmitted as a fixed bandwidth, or allocated, connection on a single output port through a network switch. The network switch maintains a plurality of input port processors, at least one output port, and input and output buffers associated with the respective input and output ports. Streams of ATM cells enter the network switch as sources for a connection through the multiple input port processors and are buffered in the input buffers. The ATM cells are then routed from the input buffers to an output buffer in the output port. The network switch also provides a multipoint topology controller (MTC) and a bandwidth arbiter (BA) for performing the arbitration.

Abstract: An ATM cell sending system includes a first memory, a second memory, a retrieval circuit, and a memory control circuit. The first memory temporarily stores an input cell, outputs a cell storage address, and, in response to input of the cell storage address, outputs the cell stored at the input cell storage address. The second memory stores the cell storage address from the first memory and outputs the readout cell storage address to the first memory. The retrieval circuit uses an address corresponding to a reservation time for cell sending as a start address to retrieve a first free address after the reservation time from the second memory. The memory control circuit writes the cell storage address of the first memory at the free address of the second memory, which is retrieved by the retrieval circuit, and reads out the cell storage address of the first memory from an address of the second memory which corresponds to a current time.

Abstract: A digital switching system is provided for coupling with one or more external specific physical interface data signal sources regardless of signal protocol, and includes input subsystems for receiving and processing the data signal sources into data cells, a data multiplexer for multiplexing the processed data, an addressable memory for storing the multiplexed data, a queue controller for creating and managing memory queues which store the multiplexed data, a data demultiplexer for demultiplexing the stored multiplexed data in response to the queue controller, and output processors for outputting the demultiplexed data.

Abstract: The capacity of switching elements, for instance 8.times.8 elements, is expanded, to originate single-stage elements with greater capacity (16.times.16 or 32.times.32), by arranging an even plurality of such elements in an output substage and by placing upstream of the output substage at least a first input substage comprising a corresponding even plurality of the switching elements. The even and, respectively, the odd outputs of the elements of the input substage are connected in an orderly manner to the inputs of the switching elements of the output substage. A routing management logic to obtain single-stage elements is also provided within each individual switching element.

Abstract: An ATM communication system with a modular structure for the switching of packeted cells (Z) between ATM communication terminals (KE) over dial-up or fixed connections has a switching device (SB) and a remote control device (CB). Arranged in the switching device (SB) is an ATM switching matrix module (ASN), at least one subscriber line module (SLMP), a communication module (KM) and a clock module (TM), and the control device (CB) is formed by a personal computer (PC) which controls the switching device (SB) in terms of operation, switching and administration and in which a processor-controlled communication adaptor (CA) is provided for the exchange of information with the switching device (SB).

Abstract: Input port numbers are assigned so as to allow formation of a unit switch having a given scale of module characteristic for a 3-dimensional installation of a switching network in an asynchronous transfer mode on basis of the Banyan network. A multiplicity of unit switches of a small (n.times.n) scale, positioned in a front portion of the switching network, are partitioned in front unit switches. A multiplicity of unit switches of the same small (n.times.n) scale, positioned in a rear portion of the switching network, are partitioned in rear unit switches. Output ports of the front unit switches are coupled in sequence in a crossed manner to input ports of the rear unit switches. Further, the input port numbers of said front unit switches are reassigned in accordance with a given formula, and the output port numbers of said rear unit switches are assigned in sequence from the uppermost position to the lowermost position.

Abstract: An ATM switching system which includes PVC allocation circuits corresponding to output queues. At the time of arrival of the leading cell of each burst data, if the output line has room, the PVC of the burst data is stored as information for admission and identification. The subsequently-arriving cells having the same PVC identification information as the stored identification information are input to an output buffer, and the cells of the remaining burst data are all discarded. Even when a plurality of burst data compete for the same output line, the fact that all the cells other than the first-arriving admitted burst data are discarded prevents the cells from being input other than within a predetermined bandwidth and localizes the burst data affected by the cell discarding due to output queue overflow.

Abstract: An asynchronous transfer mode scheduler schedules connection utilizing available bit rate (ABR) modes of traffic, unspecified bit rate (UBR) modes of traffic, variable bit rate (VBR) modes of traffic, and constant bit rate (CBR) modes of traffic. The scheduler communicates with a dynamic schedule table which includes a programmable number of slots. Each slot includes a CBR entry, a tunnel entry, and a number of VBR entries. The VBR entries store a slot tail pointer which indicates the end of a linked list. The scheduler utilizes the single bucket algorithm or dual bucket algorithm to dynamically schedule connections on future slots. The scheduler places connections using the VBR mode of traffic in a priority queue and takes the highest priority connection in the priority queue for transmission on the network.

Abstract: An ATM communication system has a connection setting section for controlling a plurality of ATM switches to set an n:n bidirectional ATM connection having n terminals of a plurality of constituent terminals as terminal points and using the VPI/VCI for identifying the n terminal points, and a process ID allocating section for allocating an MID as a process ID to a plurality of processes, executed by the n terminals for sending a message to the bidirectional ATM connection. The ATM communication system migrates a process executed on an arbitrary terminal to another terminal while keeping the process ID allocated to the processes. Where a dead-lock occurs due to that a process becomes a sleep state for the reason of that the bandwidth of a physical link is insufficient for executing in parallel the processes on the ATM communication system, the bandwidth of the physical link that a sleeping process occupies is intercepted to avoid a CAC dead-lock.

Abstract: A switch fabric controller comparator system (200) is provided for comparing the contents of a foreground port mapping memory (25) and a background port mapping memory (125). The switch fabric controller comparator system (200) includes the foreground port mapping memory (25), the background port mapping memory (125), and a switch fabric controller comparator (150). ?? The foreground port mapping memory (25) is populated with foreground port mapping data identifying the mapping of an output port of a foreground switch fabric (26) to an input port of the foreground switch fabric (26), and the background port mapping memory (125) is populated with the background port mapping data identifying the mapping of an output port of a background switch fabric (126) to an input port of the background switch fabric (126).

Abstract: A function of a switch apparatus is realized as an adapter. Signaling data which cannot be processed in the adapter, is output to a mainframe bus of a computer through an AAL controller, a RAM, and a bus controller. The computer processes the signaling data and sends it to a switch adapter through the mainframe bus. The signaling data is input to an 8.times.8 switch through the bus controller, the RAM, the AAL controller. Usual user information is switched by a PHY unit, a TC/ATM controller, an address converter, and the 8.times.8 switch. By connecting the switch adapter to the computer, it is possible for the computer to operate as a switch apparatus without damaging its function.

Abstract: An asynchronous transfer mode (ATM) based service consolidation switch (10) includes an input/output module (22) having a to-switch port (TSPP) processor (90) and a from-switch port processor (FSPP) (92). The TSPP (90) and the FSPP (92) communicate with a bandwidth arbiter (114), multipoint topology controllers (116), and a data crossbar (117) on a switch control module (32). The TSPP (90) receives traffic over links for conversion into an internal cell format. Internal cells are buffered until allowed to transfer to an appropriate FSPP (92). Multipoint topology controllers (116) performs translations for internal switch flow control through interactions between the TSPPs (90), FSPPs (92), and the bandwidth arbiter (114). The bandwidth arbiter (114) performs appropriate bandwidth arbitration to allow internal cells to flow from TSPPs (90) to FSPPs (92) over the data crossbar (117).

Abstract: A multicast connection control apparatus provided in a branching-and-consolidating node connecting a source terminal to a plurality of destination terminals for branching information over the forward connection or consolidating information over the backward connection in a multicast connection ATM network system includes a congested status management table for managing congested status in all RM cells and a controller. The controller transmits only an uncongested status RM cell transmitted thereto last over the backward connection when all the connections in a sequence are found to be in the uncongested state. The controller also transmits only a congested status RM cell over the backward connection when one of the connections is found to be in the congested state and cancels the subsequent transmission of the congested status RM cells in the same sequence over the backward connection.

Abstract: In a method of transferring packets in a network for a parallel processor system handling a one-to-one transfer packet to be transferred from a processor to another processor and a broadcast packet to be transferred from a processor to a plurality of other processors, a transfer request of a broadcast packet is preferentially selected and a check is made to detect whether or not a plurality of processors specified as receivers are in a state in which the packet can be received. The broadcast packet is transferred to the processors found to be in the state in which the packet can be received. The packet transfer is delayed for the other processors in a state in which the packet cannot be received. Namely, only when the state of the processors is changed to the state in which the packet can be received, the broadcast packet is transferred thereto.

Abstract: One embodiment of the invention is an ATM switch comprising a switch fabric, a controller, a buffer, a plurality of input line cards and a plurality of output line cards. The input line cards comprise input connectors and output connectors, with the number of input line card input connectors exceeding the number of input line card output connectors, and the output line cards comprising output connectors and input connectors, with the number of output line card output connectors exceeding the number of output line card input connectors. In another embodiment, the invention is an ATM switch comprising a switch fabric, a controller, a buffer, a plurality of input line cards and a plurality of output line cards, with the input line cards comprising input connectors but no output connectors and the line output line cards comprising output connectors but no input connectors. The invention is also drawn to a line card having either an input switch interface or an output switch interface.

Abstract: A network (10) includes a broadband customer service module (B-CSM) (20). The B-CSM (20) includes a plurality of feeder interface cards (FICs) (36) and optical line cards (OLCS) (38) which are coupled together through a midplane assembly (34) so that each FIC (36) couples to all OLCs (38) and each OLC (38) couples to all FICs (36) through junctor groups (68). The B-CSM (20) interfaces many OC-12 SONET feeders to many OC-12 SONET lines. Within the B-CSM (20) circuit switching is performed electrically at an STS-1 rate. A reference clock which oscillates at a frequency lower than the data rate is routed with payload data so that it receives delays similar to those imposed on the payload data due to processing. At second stage switching fabrics (50) where data need to be extracted from signals flowing within the B-CSM (20), a clock regeneration circuit (32) generates a master clock signal oscillating at twice the data rate and phase synchronized to a delayed reference clock.

Abstract: A method (1200, 1500, 1600, 1700, 1800) and packet switch (500, 600, 700, 1400,1900, 2000) for efficient switching of a plurality of received packets from a plurality of ingress ports to a plurality of egress ports, using the steps of: A) storing the packets in memory; B) sending arrival information for each packet to a destination egress port for the packet; C) storing, in memory at each destination egress port, the arrival information; D) requesting, by each destination egress port, the packets from the packet memory in accordance with a predetermined scheme; and E) sending, by the packet memory, to the destination egress ports, the packets requested.

Abstract: An application specific integrated circuit (or "ASIC") chip for building a scaleable, multicast, asynchronous transfer mode (or "ATM") switch having on the order of 100 to a few thousand input and output ports. The ATM switch has a regular structure and may be easily expanded. Furthermore, the ATM switch permits synchronization for data and clock signals to be relaxed. Moreover, the switch system may be built using economic CMOS technology. The switch fabric of the ASIC chip can handle high line rates, supports multicasing functionality, and permits output groups to be flexibly altered. The ASIC chips may be arranged in an array thereby permitted the switch size to be scaled.

Abstract: A switching matrix has a plurality of inputs and outputs which may be connected to each other. Pairs of inputs and outputs are examined sequentially to determine whether a connection can be made across the matrix. If the evaluated input and output are busy a connection cannot be made, and the input remains idle. When a connection can be made a connection is scheduled, taking into account the time for which that connection has been available. Inputs and outputs have controllers which continuously monitor, e.g. by using counters, the time for which connections have been available. Idle time at inputs is reduced, thereby increasing switching capacity. The switching matrix may be one which handles ATM traffic.

Abstract: A local area network switch which implements packet segmentation and reassembly for cell-based switching on a backplane cell bus. A plurality of packet processing units are each coupled to a backplane cell bus wherein each packet processing unit hosts a plurality of local area network ports. Each packet processing unit is associated with a single packet buffer memory that is shared by the ports associated with the packet processing unit. The segmentation of local area network packets into fixed-size cells facilitates an efficient local area network switch which provides dedicated bandwidth for each of the ports associated with the switch. There is also provision for coupling the local area network ports to communicate with a high-speed network interface.

Abstract: The input/output buffer type ATM switch capable of traffic control depending on the traffic type at the time of cell congestion is provided. There are provided an input buffer memory and an output buffer memory for storing cells at each of a plurality of input ports and a plurality of output ports. Each of the input buffer memories is provided with queues corresponding to each of the output ports, logically independent for traffic types and sharing a memory area. Each of the output buffer memories is provided with queues logically independent for traffic types and sharing a memory area, and outputs an overflow signal corresponding to a remaining memory capacity against each of the input buffer memories. Cell transmission from the input buffer memories is controled in response to a remaining memory capacity and the traffic type indicated by the overflow signal.

Abstract: Methods and apparatus for processing cells in an asynchronous transfer mode (ATM) communication system. An ATM cell processor implements a "bubble" count technique which efficiently accommodates multiple layers of scheduling requests and/or external cell sources. In the case of multiple layers of scheduling requests, first and second primary scoreboards are provided for scheduling/servicing of, for example, higher and lower priority traffic, higher and lower cell rate traffic, or externally and internally generated traffic, respectively. A bubble count is maintained for the second scoreboard, and the count is incremented each time the first scoreboard is serviced and decremented each time an idle slot is encountered on the second scoreboard but not queued for transmission. Scheduling requests for the second scoreboard are then made at a target time plus the bubble count.

Abstract: The present invention relates to a fixed length packet switching apparatus using multiplexers and demultiplexers in which the apparatus has an output buffer-type construction, protects itself from a temporary overflow occurrence of an output terminal and has the construction of the mutual flow control to enhance its entire performance. The present invention can protect the entire operations as well as enhance the entire performance of the switching apparatus by preventing an obstacle of the switching apparatus due to an overflow temporarily generated from an output terminal, process without a loss of excessive cells a traffic phenomenon of one output port in the switching apparatus, reduce the necessary buffer according to the effect of the rate gain and process smoothly input traffic of the internal buffer having a burst characteristic.

Abstract: A data switch is described with a multi-port data switching element, one or more input/output adapters for receiving user data cells from outside the switch and for transmitting cells switched through the switching element to a network outside the switch, and a control element including a control processor. To reduce the complexity of the data switch, the single control processor is used to control operations of hardware modules on both the the control element on which the processor is located and on the input/output adapters. The control is provided by means of control cells which generally traverse the same data paths as user data cells and generally conform to the format of user data cells, at least within the data switch. Both the control processor and the hardware modules are capable of generating control cells and transmitting them toward a target, either the control processor or hardware modules.

Abstract: An ATM telecommunications switch includes a plurality of parallel data switching planes and a parallel central plane, each plane having an equal number of input ports and output ports and a central switching unit to switch each input port to any output port. The switch further includes a first rotator to connect each input port cyclically to each timeslot of the central switching unit and a second rotator to connect each timeslot of the central switching unit cyclically to each output port.

Abstract: AN ATM communication system having both dynamic bandwidth allocation capability comprising storage mechanism for DBA traffic, the storage mechanism further including dedicated storage mechanism for ABR traffic. The system being such that ABR bandwidth requests are allocated after all other DBA bandwidth allocations have been satisfied. A device for interrupting an ABR transmission, before a bandwidth allocation within which the said ABR transmission is included has been fully used, for the transmission of other higher priority DBA traffic is provided.

Abstract: In a duplicated arrangement for an ATM switching system, first and second store-and-forward buffers are provided for storing and forwarding an ATM cell stream and first and second counters are responsive to a timing signal for producing a first cell count and a second cell count representative of counts of cells stored in the first and second store-and-forward buffers, respectively. A detector is provided for detecting a difference between the first and second cell counts. A buffer controller controls the second store-and-forward buffer in accordance with the difference so that the count of cells in the second buffer approaches the count of cells in the first buffer. A switching circuit normally couples the ATM cell stream forwarded from the first buffer to an output port of the ATM switching system and couples the ATM cell stream forwarded from the second buffer, instead of from the first buffer, to the output port in response to a switching command signal.

Abstract: The techniques required to switch an ATM cell between an input adapter and an output adapter are enhanced by performing two look-up operations. The first look-up operation is performed in the input adapter which receives the cell to be switched. The first look-up operation retrieve the address of the target output port and a connection control block. The second look-up operation is performed in the target output adapter and makes use of the results of the input adapter search to retrieve the information need to complete the transfer of the cell to the target output port.

Abstract: A method and apparatus is provided for generating and implementing a "smooth" schedule for forwarding of cells across a switch in a communication network, such as an AIM network. The schedule is obtained by recursively dividing bandwidth requests into nearly equal subrequests, and selectively allocating the subrequests to slots of a frame in a manner that obtains approximately uniform temporal distribution of cell forwarding over the duration of the frame. Implementation of such a schedule can eliminate clustering of cell forwarding across the switch, thereby reducing latency and space requirements for input and output buffering.

Abstract: Automatic provisioning of dedicated circuits (40, 44, 48, 49, 55, 56, 64, 68, 72, and 74) within a network (10) to obtain connectivity of a prescribed bandwidth between an origin (12) and an end point (16) is accomplished by first identifying circuits having a prescribed bandwidth and suitable location from a map of such circuits maintained in a data base (80). Once the circuits having the prescribed bandwidth and suitable location are identified, then a group of circuits is selected, based on one or more predetermined criteria. Thereafter, provisioning commands are generated for receipt by Digital Access Cross-Connect Devices (42, 46, 50, 54, 58, 62, 66 and 73) that interconnect the circuits to provide the desired conductivity between the origin and the end point.