Abstract: A communications network switch includes a plurality of network ports for transmitting and receiving packets to and from network nodes via network links, each of the packets having a destination address and a source address, the switch being operative to communicate with at least one trunking network device via at least one trunk formed by a plurality of aggregated network links. The communications network switch provides a method and apparatus for balancing the loading of aggregated network links of the trunk, thereby increasing the data transmission rate through the trunk.

Abstract: A circuit switched switching system and method includes a plurality of matrix transposition memories. The memories permute the order of incoming and outgoing data, and thereby increase the efficiency of the switch. The switch and matrix transposition memories may be disposed in a satellite. The switch may further include batching circuits for grouping together data from a single terminal device for more efficient transmission through the switch and for more efficient error correction.

Abstract: A bit stream multiplexer includes an input ordering block, a plurality of multiplexers, an output ordering block, and a Pseudo Random Bit Stream (PRBS) function. The input ordering block is operates to receive a first plurality of transmit bit streams at a first bit rate, order the first plurality of transmit bit streams based upon a first order select signal, and produce a first plurality of ordered transmit bit streams at the first bit rate. The input ordering block may also deskew the first plurality of transmit bit streams. The plurality of multiplexers operate to receive the first plurality of ordered transmit bit streams at the first bit rate and produce an interface plurality of transmit bit streams at an interface bit rate. The output ordering block operates to order the interface plurality of transmit bit streams based upon an interface order select signal. The PRBS function produces a PRBS that is coupled to at least one of the interface plurality of transmit bit streams.

Abstract: In a method of controlling a transmitting buffer and a receiving buffer of a network controller and in a network controller operating under such a method, at least one request for access to a system bus from the transmitting buffer and the receiving buffer is received, and the occupancy level of data in the receiving buffer and the vacancy level of data in the transmitting buffer are determined. Access to the system bus by the transmitting buffer or the receiving buffer is granted based on the determination result. According to the method and system, buffers in the transmitting path and buffers in the receiving path are treated as a single virtual transmitting buffer and a single receiving virtual buffer, respectively, and bus priority is determined in consideration of the occupancy level of data in each virtual buffer along with any increase or decrease in the occupancy level.

Abstract: A method and system for prioritizing connection data that is associated with different classes of service for transmission in a frame based communication system. These classes of service can include CBR, nrt-VBR, MGR, and UPR traffic. One embodiment of the scheduling method and system uses hierarchical round-robin (HRR) with deficit round-robin (DRR). In this embodiment, the scheduling method and system guarantees minimum rates of nrt-VBR and MGR traffic to the connections. The excess bandwidth is then fairly allocated between the existing connections and their classes of service. For example, the excess is allocated for UBR traffic and for the excess demands of the nrt-VBR and MGR connections. In one embodiment, the scheduling method and system allocates the excess bandwidth in a frame to the existing connections using weighted round robin to differentiate between different classes of service.

Abstract: A method and apparatus for admission control in a communication system. An Access Network (AN) element determines available resources. When available resources are sufficient to support the requirements of a requested application flow, the AN admits the application flow. The AN periodically, and on trigger events, updates a measure of available resources. The admission control may operate in coordination with a scheduler applying a compensation factor to each flow type, and a compensation factor for aggregate flows of a given user.

Abstract: Disclosed herein is a system and method to implement end-to-end QoS for connections in IP-based networks, even when the communications are between different subnetworks. In accordance with an embodiment of the invention, QoS is provided between subnet routers that are attached to the network through a network backbone. An embodiment of the invention can differentiate connections between routers and can classify data streams for both inter-subnet and intra-subnet connections using only information provided in the IP headers and without requiring any special tags or other identifiers to be added to the packet.

Abstract: A switch for use with an InfiniBand network having a management port adapted to arbitrate among equal priority signals requesting attention from ports on the switch. In particular, the management port included three registers that are used to arbitrate between the requests. The first register stores an indication of each type of signal from each port issuing the signal. The second register to indicate which single type of signal from which port has the priority to be handled next. The third register that indicates which signal is to be handled next or is currently being handled.

Abstract: A scheduling system for IP routers is provided. A programmable scheduler for IP routers can support single stage and multistage scheduling. This allows flexible combinations of scheduling and widens dramatically the available QoS solutions to operators. With this kind of scheduling the router can be configured to support almost any known scheduling method or combination. Priority Queuing (PQ) and Deficit Round Robin (DRR) scheduling is scheduling is used according to one embodiment of the invention.

Abstract: A method for integrating Asynchronous Transfer Mode (ATM) and frame-based traffic flows within a telecommunications network is disclosed. The telecommunications network includes a network processor having upside processing means for delivering an incoming flow from the telecommunications network to a switch and downside processing means for delivering outgoing network traffic from the switch to the telecommunications network. The incoming flow is initially received at the upside processing means as a frame-based flow. The incoming flow may be characterized as belonging to a group having frame-based flows and ATM flows. In response to the receipt of the incoming flow, the incoming flow is determined if it is destined for a legacy, ATM-only device. The incoming flow is then processed according to the determined routing requirements and the incoming flow characterization before delivering the incoming flow to the switch.

Abstract: A multimode queuing system for DiffServ routers is provided. The multimode buffering and scheduling system that can be adjusted to show either “pure” AF/EF behavior, “pure” DSUI behavior, or a combination of the AF/EF behavior and the DSUI behavior. An operation point parameter may be set to select the desired behavior. DiffServ products utilizing the combination of the behaviors are flexible and more configurable as compared to only AF/EF products. The multimode queuing system deployment is simple and is a low cost modification to DiffServ routers. The same hardware and/or software implementation can support both mechanisms with very small additional cost and effort. Also the management of the system is simplified. For example, there is no need for several parallel queuing systems.

Abstract: A technique is provided for facilitating writing of messages to multiple adapters connected to a high speed switch in a distributed computing environment. The technique employs a first, relatively quick filter to initially test whether a previously used adapter of the multiple adapters should be used to send a new message. If the first filter fails to select the previously used adapter, then the technique includes employing a second, more complicated filter to determine which adapter of the multiple adapters should be used to send the message. The first filter includes a first set of tests, and the second filter includes a second set of tests.

Abstract: A router for supporting differentiated qualities of service (QoS), and a fast Internet protocol (IP) packet classification method performed in the router, are provided. The router hierarchically divides a memory having flow tables into a fast internal cache memory and an external typical memory. The internal cache memory stores recently searched table entries. The router preferentially searches the flow tables of the internal cache memory. Only when the internal cache memory searching fails, the flow tables of the external memory are searched. Consequently, the frequency of interactions between a packet classifier and the external memory decreases to improve the speed of packet classification.

Abstract: A switch for switching traffic from N sources to M destinations, where M and N are each an integer greater than or equal to 2. The switch includes K segments, where K is greater than or equal to 2 and is an integer. Each segment receiving traffic from R of the N sources, where 1≦R<N and is an integer, and all K segments in total receiving traffic from the N sources. Each segment collecting and queuing traffic from the respective R sources. The switch includes an arbitrator which receives information from the destinations regarding if they can receive data or not, and from the K segments about the traffic they have for different destinations. A method for switching traffic from N sources to M destinations, where M and N are each an integer greater than or equal to 2. The method includes the steps of receiving traffic from the N sources at input ports of K segments, where K is greater than or equal to 2 and is an integer.

Abstract: A packet transfer apparatus, a scheduler, a data transfer apparatus, and a packet transfer method which can control a transfer rate for each attribute according to an operational situation. When a packet is input, the buffer control circuit determines an attribute of the packet. The input packet is stored by the buffer control circuit in a buffer area which is associated with the determined attribute in advance. Thereafter, when it becomes possible to transmit a packet, the selector refers to information set in a register, and selects a buffer area which has a highest priority among at least one buffer area storing at least one packet. The selection result is sent to the buffer control circuit. Then, buffer control circuit outputs a packet stored in the selected buffer area.

Abstract: A new approach is described for scheduling uplink or downlink transmissions in a network having remote terminals communicating with a central hub. The scheduler keeps track of a token count. The token count for a given remote terminal is incremented by a target amount in each pertinent timeslot, but is also decremented each time that the remote terminal is served. The amount of the decrement for one timeslot is the amount of data served, i.e., transmitted to or from the remote terminal, in that timeslot. In exemplary embodiments of the invention, the target amount by which T is incremented depends on the current value of T. Whenever the token count is non-negative (i.e., whenever it has a positive or zero value), the target amount is a desired floor, or lower limit, on an average amount of data delivered to or from the given remote terminal in one timeslot. Whenever the token count is negative, the target amount is a desired ceiling, or upper limit, on the same average amount of data delivered.

Abstract: A buffering structure including a number of storage structures and associated diversion and/or insertion logic, is provided to facilitate one or more selected ones of post-switching, pre-medium placement, diversion and/or insertion of egress packets, and post-medium extraction, pre-switching, diversion and/or insertion of ingress packets, during data link/physical layer processing of networking traffic. In selected applications, the buffering structure is provided as an integral part of a single ASIC multi-protocol networking processor having data link/physical layer processing components for a number of datacom and telecom protocols. In one of the selected applications, the single ASIC multi-protocol networking processor is employed in conjunction with other optical and electro components to form an integral optical networking module in support of optical-electro networking for the datacom/telecom protocols.

Abstract: This invention relates to a method for reconstructing non-continuous packetized data of a continuous data stream like streamed media, voice, audio, or video from a data connection into a continuous data stream at the receiving point of a packet-based network, comprising the steps of

Abstract: A queue management system and a method of managing a queue. The queue management system includes primary and secondary queues for storing messages, and a processor for determining on which queue to place received messages. This processor means includes (i) means for receiving messages, and (ii) means for determining, for each received message, whether the message is logically related, according to a predefined relationship, to one of the messages stored on the primary queue. If the received message is logically related to one of the messages stored on the primary queue, then placing the received message on the secondary queue; and if the received message is not logically related to one of the messages stored on the primary queue, then placing the received message on the primary queue.

Abstract: System and method for determining expiration of a timestamp using a counter. Upon the occurrence of a first event, a time value derived from a binary counter with a length N is associated with the first event. At a later second time value derived from a binary counter with length N, the first time value is checked for expiration with respect to an expiration period. The second time value is summed with a predetermined offset value and the sum formatted as a number with length N+2. The first time value is subtracted from the sum and the two most significant bits are removed. The result is then compared to the expiration period to determine whether expiration has occurred.

Abstract: Shaping data transmitted in a communication system includes determining whether to authorize transmission of received data having a variable size within a predetermined range. The determination is based on whether a predetermined amount of a time-based variable has substantially elapsed, the predetermined amount being related to a rate shaping criterion, and the determination is made without regard to the size of the received data.

Abstract: A switch, switched architecture and process for transferring data through an FCAL switch is disclosed. The switch uses multiple switch control circuits each coupled to one FCAL [net]work and all connected to a crossbar switch. The switch control circuits are coupled together by a protocol bus for coordination purposes. Local conversations can occur on each FCAL loop and crossing conversations through the switch can occur concurrently. The OPN primitive is used to establish the connection before any data is transferred thereby eliminating the need for buffer memory in the switch control circuits. The destination address of each OPN is used to address a lookup table in each switch control circuit to determine if the destination node is local. If not, the destination is looked up and a connection request made on the protocol bus. If the remote port is not busy, it sends a reply which causes both ports to establish a data path through the backplane crossbar switch.

Abstract: A processor includes scheduling circuitry and a priority computation element associated with the scheduling circuitry. The scheduling circuitry schedules data blocks for transmission from a plurality of transmission elements, in accordance with a transmission priority established by the priority computation element. The priority computation element, which may be implemented as a script processor, is operative to determine a transmission priority for one or more constituent transmission elements in a specified group of such transmission elements. The group of transmission elements corresponds to a first level of an n-level hierarchy of transmission elements, with the constituent transmission elements corresponding to at least one lower level of the n-level hierarchy of transmission elements. The transmission priority is preferably made adjustable under software control so as to facilitate the maintenance of a desired service level for one or more of the transmission elements.

Abstract: A processor includes scheduling circuitry and an associated interval computation element. The scheduling circuitry schedules data blocks for transmission from a plurality of transmission elements, and is configured for utilization of at least one time slot table in scheduling the data blocks for transmission. The interval computation element, which may be implemented as a script processor, is operative to determine an interval for transmission of one or more data blocks associated with corresponding locations in the time slot table. The transmission interval is adjustable under control of the interval computation element so as to facilitate the maintenance of a desired service level for one or more of the transmission elements.

Abstract: A processor includes scheduling circuitry for scheduling data blocks for transmission from multiple transmission elements, and traffic shaping circuitry coupled to the scheduling circuitry and operative to establish a traffic shaping requirement for the transmission of the data blocks from the transmission elements. The scheduling circuitry is configured for utilization of at least one time slot table which includes multiple locations, each corresponding to a transmission time slot. The scheduling circuitry is operative in conjunction with the time slot table to schedule the data blocks for transmission in a manner that substantially maintains the traffic shaping requirement established by the traffic shaping circuitry even in the presence of collisions between requests from the transmission elements for each of one or more of the time slots.

Abstract: A system, method and computer software for handling overload conditions in a request queue of a server in a client-server architecture. When request queue overload conditions are detected, one or more of the next-to-be serviced requests in the request queue of the server are removed and the remaining requests in the queue are forwarded by the same number of requests that were removed. By preventing the servicing of requests that may have already experienced a timeout by the requesting client, the overall performance of the system is increased.

Abstract: A data transmission system comprising a packet switch module interconnecting LAN adapters, a plurality of input and output ports connected to the LAN adapters such that each pair of input and output ports defines a crosspoint within the switch module, and a memory block located at each crosspoint of the switch module for storing at least one data packet. At each clock time, a scheduler causes a data packet stored in a memory block, among all memory blocks corresponding to a given output port, to be transferred to that output port.

Abstract: A system and method for facilitating the scheduling and transmission of transmit protocol messages. Initially, a write credit count is maintained indicating the number of write credits available to a transmit message processor. Upon receipt of a data frame for transmission to a data pump, the transmit message processor determines whether the write credit count is greater than 0. Of so, the frame is dequeued and the message is sent to the data pump for transmission on the wire to a receiving peer end. However, if the write credit count is 0, a waiting_for_write_credit flag is set to true indicating that the transmit processor has a frame waiting for transmission, but lacks sufficient write credits to send the frame to the data pump. Once an additional write credit is received from the data pump, the write credit count is incremented and the waiting_for_write_credit flag is checked to see if any frames are waiting to be send.

Abstract: A computer-based system that permits a service-provider to monitoring other computer systems includes a plurality of relays. A monitored relay collects data from one or more monitored computers in the system. This data is forwarded through a secure communication pipeline implemented by the monitoring system to a forwarding relay. The forwarding relay controls data flow between a service provider node and the monitored relays, and includes an instrumentation process that collects data regarding one or more message threads in the relay and sends the data downstream to a service provider system. Computers at the service provider node analyze the data to generate meaningful information about the monitored system, which can be accessed by the service provider or by the owner/operator of the computer system. In addition, the information may be used to generate notices or alarms of specific events.

Abstract: A technique for physically implementing a running sum adder network and configuring the concomitant adder network of elements. A 2k+1×2k+1 adder network has the size 2k+2−k−3 and depth 2k+1; thus the adder network achieves a very good balance between the measures of size. The adder network utilizes a systematic design method based upon a recursive construction algorithm.

Abstract: An insertion sorter circuit and method are provided which are particularly useful for sorting channel response values of a communication signal. The sorter circuit includes a series of sorter elements which each have a register. The circuit is configured to cascade values downwardly when one register receives a greater value than it has stored, which value is not greater than the value stored in any upstream register. At the end of processing the values, the most significant values are stored in the registers, the sum of which are the channel power estimate. The channel noise variance is obtainable by applying a system dependent scaling factor to the sum of the least significant values processed.

Abstract: An apparatus, a search tree structure, methods and computer devices for constructing and using the structure to efficiently accomplish policy based service differentiation in packet networks is presented. This invention reduces the number of steps performed to implement packet classification. It uses a method of preprocessing a given set of policy rules by modeling the conditions in the rules as multidimensional hyper-cubes, a simple and compact search tree is constructed. Using this search tree, packet classification is achieved determining all applicable policies for a packet with a few compare and branch instructions.

Abstract: An augmented ring-banyan network utilizing an adaptive, self-routing control algorithm in an ATM switching system with a qth (where q≧1, and an integer) augmenting stage having prescribed switch elements each connected to corresponding switch elements of a final stage in the network, and a g+1st augmenting stage having prescribed switch elements each connected to the prescribed switch elements of the qth the augmenting stage. Topology for the output links of each of the switch elements is represented, by: &bgr;1[(Pl, Pl−1, . . . , P1)i]=(Pl, Pl−1, . . . , P1)i+1 connected with link (Pl, Pl−1, . . . , P1, 1,)i, and &bgr;0[(Pl, Pl−1, . . . , P1)i]=(Pl, Pl−1, . . . , P1)i+1 connected with link (Pl, Pl−1, . . . , P1, 0,)i, provided that: l=(log2N)−1, and i≧l+1.

Abstract: The size of a Jitter Absorption Buffer (JAB) is automatically changed in response to changes in network conditions. The JAB size is changed based on the fullness of the JAB and the recent variations in JAB depth. Automatic adjustment allows for a balance of providing adequate correction for Packet Delay Variation (PDV) while avoiding unnecessary increases in Absolute Packet Delay (APD) from the prolonged use of an oversized JAB. This abstract is provided as a tool for those searching for patents, and not as a limitation on the scope of the claims.

Abstract: An adaptive scheduling method, systems and apparatus for streaming data service for either single-carrier channel or multi-carrier channel are provided. This adaptive scheduler assigns data transmission using mixed round-robin and maximum CIR user selections based on a predetermined threshold relative to the target streaming data transmission rate. It can provide a very high flexibility for a streaming data service and exploits a multi-user diversity in single-carrier system and an additional frequency diversity in multi-carrier system.

Abstract: A subscriber interfacing apparatus included, for example, in an ATM switching system operates as an interface between an internal switching apparatus and an external transmission line having a relatively high speed compared with the processing speed of the internal switching apparatus. The subscriber interfacing apparatus includes a high speed cell interfacing unit which performs a multiplexing/de-multiplexing function in association with a number of FIFOs to transmit data cells from a high-speed external transmission line to an internal interfacing apparatus which operates at a lower speed. In performing this function, the transmission order of cell data for each connection to the switching system is guaranteed by distinguishing the transmission route of each of the data cells to be transmitted to respective connections in the switching apparatus.

Abstract: A new approach to providing both bounded-delay and best-effort operation in a packet network node is described. The bounded-delay mode is capable of providing a firm end-to-end delay bound, but in contrast to the combination of RSVP and Guaranteed service proposed within the IETF, it does this with minimal complexity. Network nodes are provided with dual packet buffers associated with bounded delay and best effort classes of service respectively. Appropriate dimensioning, if necessary enforced through CAC methods, ensure that packets admitted to the bounded delay buffer are provided the firm delay bound. CAC methods are described which are applicable for packet flows as small as a single packet. A means is also offered for removing the traditional network signalling phase. A related architecture for use with hosts is also described.

Abstract: A system and method reduces the delay of speech processing over a packet-switched network in a discontinuous transmission system. According to exemplary embodiments, a base transceiver station assigns priority indicators to information received therein. When the information is speech or a first SID frame, a high priority indicator is assigned. When the information is a SID update frame, a low priority indicator is assigned. The information is transferred from the base transceiver station to a base station controller in an order determined by the priority indicators. As such, the delay in transferring and processing speech information is reduced.

Abstract: A system and method for late-dropping packets in a network switch. A network switch may include multiple input ports, multiple output ports, and a shared random access memory coupled to the input ports and output ports by data transport logic. Packets entering the switch may be subject to input thresholding, and may be assigned to a flow within a group. A portion of a packet subject to input thresholding may be accepted into the switch and assigned to a group and flow even if, at the time of arrival of the portion, there are not enough resources available to receive the remainder of the packet. This partial receipt of the packet is allowed because of the possibility of additional resources becoming available between the time of receipt of and resource allocation for the portion of the packet and receipt of subsequent portions of the packet.

Abstract: This coordinate input apparatus comprises an optical movement detection device and a switch device. The optical movement detection device projects a light on a detection object moving on an input portion, and receives the light reflected from the detection object so as to generate a move signal according to the light reflected from the detection object. The move signal includes moving direction information and moving distance information of the detection object. The switch device switches on and off by the optical movement detection device being displaced by the input portion being pressed.

Abstract: A method for resetting a MAC-hs (Medium Access Control-high speed) layer entity in a communication system using HSDPA (High Speed Downlink Packet Access). When an RLC (Radio Link Control) layer entity is reset due to occurrence a protocol error, the system resets both a MAC-hs layer entity of the RLC layer entity and its counterpart RLC, thus preventing unnecessary data transmission.

Abstract: A short cell multiplexer includes a sequence designating unit, in which reading intervals corresponding to QOS classes are set in respective reading interval setting registers. A counter memory is stored with the number of timings at which the short cells can be read. The sequence designating unit specifies the QOS class in which the number of timings reaches the reading interval on the basis of the reading interval and the number of timings, and gives to a reading unit an indication of reading the short cell belonging to this class.

Abstract: A system and method for controlling the flow of data from a data network to a mobile user over a wireless link. A data flow controller is provided in an inter-working gateway between the mobile switch center of the wireless network and the data network. The data flow controller determines the amount of available space in the mobile switch center buffer and ensures that the amount of data sent to the mobile switch center is no greater than the available buffer space. The data flow controller continually updates the available buffer space by determining the amount of data sent periodically to the mobile user according to a given airlink data rate. The data flow controller includes a buffer to store any remaining data that could not be sent to avoid overflowing the mobile switch center buffer.

Abstract: In packet data transmission method, a packet data connection is indicated with a connection identifier and the destination of the packet data connection is indicated with a destination identifier. A destination identifier is involved in the initialization of a transmission queue, at least one connection identifier is related to each transmission queue, and a set of proper connection identifiers is the union of the connection identifiers related to the initialized transmission queues. A data packet having a proper connection identifier is placed (504, 505) to the corresponding transmission queue. The method is characterized in that the initialization of a new transmission queue is triggered (506, 508) by a data packet not having a proper connection identifier and having a destination identifier and after a successful initialization of a new transmission queue the data packet that triggered the initialization is placed (509) to the new transmission queue.

Abstract: A statistically-multiplexed link for transporting aggregated data from multiple clients to a central server. A concentrator is used to separate packets containing valid data (live packets) from invalid (dead) packets. When combined with a conventional multiplexer, the concentrator circuit provides arbitration on a first-come first-served basis and allows a smaller multiplexer to service a larger number of inputs thereby enabling a more statistically efficient multiplexed link.

Abstract: A Pipelined-based Maximal-sized Matching (PMM) scheduling approach for input-buffered switches relaxes the timing constraint for arbitration with a maximal matching scheme. In the PMM approach, arbitration may operate in a pipelined manner. Each subscheduler is allowed to take more than one time slot for its matching. Every time slot, one of them provides the matching result. The subscheduler can adopt a pre-existing efficient maximal matching algorithm such as iSLIP and DRRM. PMM maximizes the efficiency of the adopted arbitration scheme by allowing sufficient time for a number of iterations. PMM preserves 100% throughput under uniform traffic and fairness for best-effort traffic.

Abstract: A switching control cell is inserted into an input cell in a switching control cell generator. In a period between the detection of a switching control cell in a first or second switching control cell detector and the detection of the switching control cell in a third switching control cell detector, in active and stand-by switches, when a cell is discarded in any one of the active and stand-by switches, in addition to priority discard control, the same cell is discarded in the other switch independently of the priority discard control. Further, upon detection of a switching control cell in the switching control cell detector, all the cells accumulated within the cell buffer are discarded, and until the detection of the switching control cell in the switching control cell detector, reading from the cell buffer is stopped so that the same cell is written into the cell buffer in the active switch and the cell buffer in the stand-by switch.

Abstract: A method and apparatus for scheduling static and dynamic traffic through a switch fabric are described. The method comprises for each switch slice in a distributed switch fabric, scheduling static traffic by reserving time slots for transmission of the static traffic to at least one destination, and scheduling dynamic traffic so as not to be transmitting the dynamic traffic to the at least one destination during the reserved time slots. The apparatus implements the method and comprises a memory storing a schedule of static traffic, shifters storing dynamic traffic scheduling requests, and a grant scheduler.

Abstract: An interface to interconnect Network Processor and Scheduler chips in a multi-chip system includes a limited set of messages and circuit arrangements to generate the limited set of messages. The messages include FlowEnqueue.request, FlowEnqueue.response, PortEnqueue.request and PortStatus.request.

Abstract: Method and apparatus is described for decoupling data from a clock signal and recoupling the data to a different clock signal for subsequent synchronous processing by a pointer processor. More particularly, on a receive or drop side, one buffer is configured to store payload pointers and a synchronous payload envelope arriving clocked by a line clock signal, while another buffer is configure to store TOH or SOH arriving clocked by the line clock signal. Each buffer clocks out such stored information off of a same system clock signal, such as a drop clock signal. On a transmit or add side, a buffer is configured to store payload pointers and a synchronous payload envelope. This buffer clocks in such stored information off of a system clock signal, such as an add clock signal, and clocks out such stored information off of a transmit reference clock signal.