Abstract: An apparatus comprising a register circuit, a detector circuit and an output circuit. The register circuit may be configured to present a parallel signal in response to (i) a serial input and (ii) a first clock. The detector circuit may be configured to generate a control signal in response to (i) the parallel signal and (ii) a selection signal. The output circuit may be configured to generate an output in response to (i) the control signal and (ii) the parallel signal.

Abstract: In a light transmission equipment which can generate a desired concatenation signal from a maximum concatenation signal standardized in a synchronous transmission mode, a master and a slave circuit for clock change are provided respectively inputting at least two data at a maximum transmission rate based on a concatenation standard of a synchronous transmission mode obtained by dividing a desired transmission rate not prescribed in the concatenation standard to perform a concatenation control to the slave circuit by control information from the master circuit side.

Abstract: A method, apparatus, and system for originating a packet.

Abstract: A network interface controller connects a processing system to receive data from a network fabric through a serial link. The data on the link is clocked in a link clock domain that is different than the core clock domain of the network interface controller. A physical interface operates in the link clock domain. It has a pipeline architecture partitioned into an input register block, a decoder block and a link synchronization manager. The input register block receives the link clock and the data on the link, and transfers the data into the link clock domain. The decoder block has dual cascaded 8B/10B decoders receiving and decoding the data transferred by the input register block. The link synchronization manager manages the synchronization of the serial link according to the decoded data. An elastic buffer is connected to the output of the link synchronization manager. It is configured to output the decoded data in the core clock domain.

Abstract: Pointer justification event induced low frequency jitter is attenuated during desynchronization of a synchronous input data stream into a plesiosynchronous output data stream. The output data stream has a clock rate T and is made up of tb byte multi-frames containing a nominal number tdb of data bits (tdb=772 and tb=104 for T1 data; tdb=1024 and tb=140 for E1 data). An integer number pc of phase adjustment commands are provided (in the preferred embodiment, pc=12 for T1 data and pc=9 for E1 data). A count having a total value pjT, where 1≦pjT≦tb, is maintained of the total number of positive pointer justification events previously encountered in the data stream. A separate count having a total value pcT, where 1≦pcT≦tdb*pc, is maintained of the total number of previously issued phase adjustment commands. If a positive pointer justification event is detected in the data stream, pjT is incremented by one.

Abstract: A group of data frames from a plurality of communication channels is received. At least one idle frame including a sequence number of a last frame in the group of data frames is then received. A delay period of time is allowed to elapse after receiving the idle frame before sending a negative acknowledgement message, if at least one data frame is missing.

Abstract: In a frame synchronization circuit, which prevents the occurrence of synchronous error due to a data loss/insertion while restraining a false synchronization/out of synchronization based on typical code error in a conventional data transmission system, the frame synchronization circuit is provided with a frame synchronization code detector which detects a frame synchronization code from a received data sequence to output a frame position and outputs a checked result by checking a frame synchronization code detected and a correct frame synchronization code. The frame synchronization circuit is also provided with and a data loss and data insertion period judgment circuit which determines which presumes whether a data loss or data insertion has occurred in the received data sequence according to the checked result.

Abstract: A correlator for use in a timing recovery apparatus of a receiver in a multicarrier transmission system. The correlator locates the beginning of a data frame and initializes a pointer register with an address to a location within the receive signal buffer. Data is transferred to a signal converter from the receive signal buffer where the samples that are fed into the converter are determined by the address stored in the pointer register.

Abstract: The objective is to provide a data transfer control device and electronic equipment that implement bit insertion, encoding, decoding, and bit deletion at a slow clock frequency. A bit stuffing circuit and NRZI encoder are provided in a stage before a parallel-serial conversion circuit on the transmission side and an NRZI decoder and a bit unstuffing circuit are provided in a stage after a serial-parallel conversion circuit on the reception side, so that bit stuffing, NRZI encoding, NRZI decoding, and bit unstuffing are implemented on parallel data, not serial data. Any bits that have overflowed due to the bit insertion are carried forward to data for the next clock cycle and any deficiency of bits caused by bit deletion is moved up from the data of the next clock cycle. Insertion (or deletion) of bits is based on the thus calculated bit stuffing (or bit unstuffing) position and the range of parallel data to be output is based on the accumulated total of the number of bits that overflow (or contract).

Abstract: A method of operating a packet network for carrying voice traffic, wherein the packets carrying voice traffic include voice samples. The method identifies a replacement packet opportunity, creates a replacement packet based on a selected packet, and inserts the replacement packet in the replacement packet opportunity. The replacement packet includes samples based on samples of the selected packet, but in an order that differs from the order of the samples in the selected packet. The method may further comprise identifying another replacement packet opportunity directly following the replacement packet opportunity, creating another replacement packet based on the replacement packet, and inserting the another replacement packet directly after the replacement packet. The another replacement packet differs from the replacement packet.

Abstract: A receiving terminal 2 calculates jitter moving average from the transmission and the reception time of each packet and sends the moving average to a transmitting terminal 1, and based on the jitter moving average, the transmitting terminal predicts an available bandwidth in a radio path.

Abstract: A DS3 frame structure, video data transmitting/receiving apparatus and method for transmitting and receiving video data can minimize the transmission error during the video data transmission, and can multiplex and transmit two video signals using the DS3 formatted frame. The DS3 frame structure includes a plurality of unit frames each of which includes a frame field for controlling data transmission, an information field of signal data, and a channel coding overhead field for correcting an error in the signal data.

Abstract: An asymmetrical digital subscriber line (ADSL) downstream high speed cell bus interface protocol allows ADSL cell packets to be transmitted downstream from an ADSL bank control unit (ABCU) to a plurality of ADSL line units at a high rate of downstream throughput with flexible and efficient allocation of bandwidths and reduced error probability. The frame boundaries of an ADSL frame are derived from a conventional subscriber bus interface (SBI) frame for carrying conventional narrowband plain old telephone service (POTS) traffic, thereby allowing the ABCU and the ADSL line units to be implemented in existing channel banks with standard channel bank backplane traces.

Abstract: A method and system enable cross connection of an incoming data stream to one or more outgoing data streams. Each data stream comprises respective incoming and outgoing frames. Each frame includes one or more rows, and each row comprises a respective plurality of data segments. A reserved memory space is provided having a data storage capacity equal to an integer multiple of a data segment and less than one complete row. A data segment of an incoming row of an incoming frame is written to the reserved memory space. Subsequently, the data segment of the incoming row is read to an outgoing row of an outgoing frame from the reserved memory space. The writing and reading steps are timed such that the data segment is read from the reserved memory space before being over-written by another data segment.

Abstract: A clock synchronization scheme for use with an access network element having scalable architecture. A point-to-point, high-speed communication link provided between two adjacent banks of the access network element logically interconnects a plurality of banks in a linear stack, thereby creating a stackplane hierarchy for local traffic. A primary bank includes a central master timing and frame alignment control block operable based on a master reference clock. A secondary bank immediately coupled to the primary bank is operable to synchronize its local clock based on a delay preset signal provided by the primary bank. Each remaining secondary bank is operable to synchronize its local clock based on the delay preset signal provided by a local master timing control block disposed in the secondary bank immediately above it.

Abstract: The invention provides an apparatus and method for transparently transporting four plesiosynchronous OC-48 signals over a network. Multiple plesiosynchronous data streams are aggregated onto an independent clock source at an ingress circuit through the use of “stuffing” bits. The independent clock is selected such that the output data rate is greater than the composite input data rate of all the plesiosynchronous data streams. The signal is encapsulated with forward error correction at the transport interface, serialized, and modulated across the transport system. An egress circuit at the receiving end recovers the modulated signal and extracts the data stream and timing extraction resulting in a return of the original data frames with the same timing as the originals. In this manner, the timing is reproduced identical to the timing of the incident signal at the ingress path, ensuring the data is identical in content and timing.

Abstract: A communication device for transmitting a sequence of data, which is transmitted thereto at a given transmission rate, at a desired transmission rate greater than the former transmission rate over a transmission line. The device comprises a mapping unit, in order to map the sequence of data into a plurality of frames in a predetermined form, each of which consists of a plurality of blocks, for assigning a predetermined amount of data to a data transmission area in each of the plurality of blocks included in each frame so that the sequence of data is nearly-uniformly arranged over the plurality of blocks included in each frame.

Abstract: A system and method for transporting telephony signals across an ATM network using AAL1 while eliminating the jitter associated with the AAL1 cells. The present invention uses starve/inspect techniques to dynamically buffer the ATM frames such that jitter associated with the cells can be reduced while avoiding unneeded buffering that would cause excessive delay.

Abstract: The present invention provides a frame synchronous circuit wherein the number of devices handling a high-speed digital signal is limited to the minimum without deteriorating frame pull-in time and an erroneous synchronization rate. For the sake of it, synchronous word decision devices decide frame synchronization from four lines of low-speed digital signals into which the high-speed digital signal is converted by a serial-parallel converter. An OR circuit synthesizes respective outputs of the synchronous word decision devices, and an aperture circuit applies an aperture to the output synthesized. A selection circuit fetches only one output corresponding to the change of the apparent synchronous word after establishment of synchronization. A frame counter circuit estimates a predetermined position of the next frame at the time of applying a narrow aperture. A leading-edge positioning/column change circuit performs leading-edge positioning and column change of data to the output of the selection circuit.

Abstract: A desynchonizer for a synchronous digital communications system serves to recover a useful signal from a synchronous digital input signal. It comprises a buffer for temporarily storing the input signal, a write circuit for writing the input signal into the buffer, a clock-generating circuit for generating a clock signal, and a read circuit for reading the contents of the buffer at the recovered clock rate. According to the invention, the clock-generating circuit includes a calculating circuit for determining an average over the interval between two pointer actions of the input signal, and derives from the average a tuning signal which serves to adjust the recovered clock signal. In this manner, jitter caused by pointer actions which result from a constant offset of the effective bit rate of the received virtual containers is eliminated.

Abstract: A satellite payload processing system for processing an uplink signal consisting of a plurality of single-channel-per-carrier, frequency division multiple access carriers comprises a polyphase demultiplexer processor for separating the uplink signal into a time division multiplexed data stream of symbols. The polyphase demultiplexer processor presents the symbols corresponding to each of a plurality of carriers at respective ones of the frequencies in the uplink signal sequentially to an output of the polyphase demultiplexer processor. A phase shift keying demodulator and differential decoder demodulates the stream of symbols into corresponding time division multiplexed stream of digital baseband bits, which are then rate-aligned with respect to an on-board clock.

Abstract: A transmit virtual concatenation processor for multiplexing channelized data onto a SONET/SDH frame is disclosed. The processor is scalable and is able to handle mapping a number of data channels to a number of different frame sizes including STS-12, STS-48, STS-192 and STS-768. The processor supports virtual concatenation with arbitrary channel mapping at both STS-1 and STS-3c granularities. The processor also supports contiguous concatenation with STS-12c, STS-24c, STS-48c, STS-192c, etc. capacities (i.e., STS-Nc where N is a multiple of 3). In addition, the processor supports mixed concatenation where some channels are using contiguous concatenation and some other channels are using STS-3c-Xv virtual concatenation. Alternatively, the processor is able to support any virtual concatenation, any contiguous concatenation and any mixed concatenation.

Abstract: It is proposed that currently unused portions of transport overhead in frames sent on a high-speed outgoing channel be used to carry error count information from each of four low-speed input channels. At a 4:1 combiner, error monitoring bytes are extracted from transport overhead of frames received on each of the four input channels. Error counts are determined and accumulated for each input channel before being passed to a transport overhead generator for the outgoing channel, where they are inserted as bit patterns in unused portions of the transport overhead. At a receiving demultiplexer, the error counts are extracted from the transport overhead of incoming frames. The extracted error counts are then used to alter the error monitoring bytes included in the transport overhead of frames sent on each of four outgoing channels such that, at the far end of those outgoing channels, a correct number of errors for the three part path may be determined.

Abstract: In the conventional data communication apparatus, there has been arisen a flag emulation due to a false pattern similar to the pattern of the true flag in a frame signal including a plurality of frames. To avoid the flag emulation, the data communication apparatus according to the present invention comprises detecting circuit and a preparing circuit. The detecting circuit detects a false pattern in the bit stream while the preparing circuit prepares a frame using the portion of the bit stream other than the detected false pattern, thus enabling avoidance of the flag emulation due to the false flag.

Abstract: A method and apparatus for performing bit stuffing operations for transmission signals are described. In an embodiment, a method includes receiving data for a number of channels of a signal. The method also includes recursively processing the data for the number of channels in an order. The processing of a channel of the number of channels includes retrieving a previous state for the channel upon determining that a timeslot for the channel is being processed. The previous state includes a history of values of a depth of a First In First Out (FIFO) for the channel. Moreover, the processing of the channel of the number of channels within the signal includes determining whether to make a bit stuffing decision for the channel upon determining whether the timeslot is associated with a bit stuffing opportunity for the channel. The bit stuffing decision is based on a current value and the history of the values of the depth of the FIFO for the channel.

Abstract: A method for data communications includes receiving a time-division-multiplexed (TDM) input signal on a first circuit, the signal including an input sequence of frames of data, each such frame divided into sections for carrying respective sub-rate payloads. After determining which of the sections are active, such that the data in the sub-rate payloads of the active sections include user data, and which of the sections are inactive, the user data in the active sections are encapsulated into data packets for transmission over a packet network, while omitting from the packets at least some of the data from the inactive sections.

Abstract: A direct spread spectrum communication system in accordance with a delayed multiplex mode in which improvement in correlation and improvement in error rate can be perfectly realized in any data length. A data generating section appends addition bits so as to generate an integral multiple of information to be transmitted, from data received from an upper (MAC) layer. The symbol length of a data part is determined from information obtained from the upper layer, and the generating section knows the symbol length of a bit synchronization section, a frame synchronization section and a various information section in the system, which should be originally appended as a packet. Therefore, the number of additional bits are added so that the total number of symbols amounts to an integral multiple of the data to be multiplexed.

Abstract: An apparatus for reducing the effects of pointer adjustments, wander, and jitter during desynchronization of a non-uniformly gapped data stream from a payload of a synchronized signal is disclosed. The apparatus utilizes a combination of two pointer adjustment signals embedded in the synchronized signal to determine a bit leak rate of bits from an elastic store following a pointer adjustment event such that the elastic store provides as an output a more-uniformly-distributed-gapped data stream.

Abstract: The invention provides an apparatus, and related method, for providing a reconfigurable frame counter that can accommodate differing start of frame pulse locations in a synchronous communication system. The frame counter may be integrated with existing devices thus providing a cost effective advance in the functionality of existing communication devices. The reconfigurable frame counter includes a multiplexer, a byte processor and a frame counter. The multiplexer byte interleave multiplexes a plurality of lower data rate SONET signals to generate a higher data rate SONET signal of framed data bytes. The byte processor processes transport overhead bytes of the higher data rate SONET signal in accordance with a frame byte count value. The frame byte counter counts clock pulses that are each associated with the arrival of a framed data byte and generates a frame byte count value that corresponds to a frame byte location of the currently received framed data byte.

Abstract: A method and an apparatus are provided for interrogating bits of a data frame. The apparatus comprises configurable logic that can be reconfigured to enable the apparatus to vary its configuration in accordance with various criteria to make it suitable for use in different domains. The apparatus locates and selects a bit pattern from a data frame for interrogation, compares a comparison bit value to the selected bit pattern to obtain a comparison result, and determines a location to which the comparison result is to be routed. The method relates to the steps of selecting the bit pattern from the data frame, comparing the selected bit pattern to the comparison bit value to obtain the comparison result, and determining the location to which the comparison result is to be routed. The logic of the apparatus is variable to enable the bit pattern to be interrogated to be varied, to enable the comparison bit value to be varied, and to enable the location to which the comparison result is routed to be varied.

Abstract: A modem system having two modem devices digitally connected to a digital telephone network includes an inband control signal channel. The inband control signal channel is formed by using the most significant bit position of every sixth transmitted codeword for the transmission of control data. The control signal includes a predetermined header section that is monitored by the receiving modem to maintain frame synchronization and to correct for digital frame slippage. The control signal also includes a number of control data packets that contain information related to the initiation of control procedures such as rate renegotiations and retraining requests. The disclosed inband transmission techniques may additionally (or alternatively) be utilized to define a secondary data channel.

Abstract: Improved approaches to provide flexibility in setting user data rates and managing delay in data transmission systems using a superframe structure and Time Division Duplexing (TDD) are disclosed. These improved approaches operate to provide intelligent insertion of dummy words (bits or bites) into a data stream to be transmitted. By inserting the dummy words, the invention is able to render codewords, symbols and superframes independent from user data rates. As a result, a wide range of user data rates are available in data transmission systems using a superframe and TDD.

Abstract: A method and system for avoiding data loss in communications systems. The method and system achieve their objects via communications equipment adapted to do the following: designate a first data-producing system controlled by a first clock; designate a second data-producing system controlled by a second clock; record a timing mismatch between the first clock and the second clock; and dynamically adjust data flow between the first and the second system in response to the recorded timing mismatch.

Abstract: A method, system and apparatus for decreasing the time frame synchronization and resynchronization in a data communication uses an long frame sync word formed by combining a frame sync word with stuff bits, wherein the stuff bits are necessary for timing adjustments.

Abstract: A parallel-to-serial-to-parallel circuit are disclosed, the circuit interfacing with a data bus, preferably with a processor for byte alignment and other operations. The parallel-to-serial-to-parallel circuit includes an input bit shift register having a predetermined number of register positions and an output bit shift register with the same number of register positions. The output of the input bit shift register is fed into the output bit shift register through a multiplexer. The input bit shift register may receive a bit write from a bit bus, a partial parallel write from a data bus with corresponding data validity data received on a shadow bus, and full parallel write from the data bus. The output bit shift register may transmit a bit read to the bit bus or a full parallel read to the data bus. Data received is shifted to the output bit shift register and compiled into full parallel data or read out as single bits. Offset bits may be introduced in the data stream for data alignment.

Abstract: A communications system includes N parallel communications channels connecting first and second devices. The N channels may include N-1 channels for carrying information symbols, and an Nth channel for facilitating deskewing and word framing. The first device may include an alignment symbol generator for generating alignment symbols on the Nth channel, and a word framing code generator for generating word framing codes on the Nth channel. The second device may include a deskewer for aligning received information symbols based upon the alignment symbols, and a word framer for determining word framing based upon the word framing codes. The word frame code generator in the first device or transmitter, and the word framer in the second device or receiver provide the desired feature of knowledge of where each word starts or begins. The start of each word may be determined in terms of a time and a corresponding one of the N-1 channels where the word starts.

Abstract: A method and apparatus for determining synchronization and loss of synchronization in a high speed multiplexed data system. The system also includes a plurality of justification control bits and a backwards compatibility flag that allows the system to operate with older systems that have fewer justification control bits.

Abstract: A data switching apparatus selects and transmits one of a plurality of received data and switches coded data while holding a coding unit of the coded data. A data switching apparatus includes plural data unit detectors each for detecting a coding unit of a data from a received data; plural data storages each for storing a received data in a buffer and transmitting the received data at a given time from a point specified by the data unit detector; and a data selecting unit for selecting and transmitting only one data stream from a plurality of data streams which are transmitted respectively from the plural data storages.

Abstract: The present invention concerns a modular expandable telecommunication system, such as a private automatic branch exchange system (PABX), comprising a main cabinet and at least one expansion cabinet, which are interconnected with each other in order to obtain an extended telecommunication system with increased connection possibilities for extensions and trunks. System characterized in that the main cabinet and each of the expansion cabinet comprise a transmission interface unit allowing connection of the said expansion cabinet(s) with said main cabinet via a single transmission link conveying voice/data channels and low level or local signaling for performing at least mutual synchronization and clock recovery for all interconnected cabinets, the main cabinet comprising in particular a master clock device, a CPU for running the application and a DSP for routing the higher level messages issued by the CPU depending on the physical location of the destination cabinet.

Abstract: A system and method providing a structure to the data sent over the air interface of a wireless communication system. The system and method allow compensation for transmitting and receiving frequency variations, synchronization at the receiver and provision of a virtual signaling channel for system alarms and status. In one embodiment, the system uses bit stuffing, a frame preamble and a signaling preamble to transmit data at a high data rate in the ISM band.

Abstract: A system for bit synchronous communications over packet networks with adverse delay conditions is provided by sequencing in association with a local terminal fixed-sized payloads from an input bitstream and reassembling in association with a remote terminal the received payloads in sequence. Delayed, dropped, duplicated, and mis-sequenced packets are repaired through the use of a smoothing buffer associated with the remote terminal.

Abstract: Pointer action in an SDH transmission apparatus is performed in a temporally evenly dispersed manner. Timings of a received VC-4 clock and a transmit VC-4 clock, whose portions corresponding to overhead are inhibited in a clustered fashion, are evened out by a receiving-side PLL circuit and a transmitting-side PLL circuit, respectively, after which their phases are compared in a phase comparator to generate a justification request. In another aspect of the present invention, the phase comparison is made between VC-4 clocks whose clock inhibit timings are dispersed. In a further aspect of the present invention, a justification request arising from a frequency difference between the transmitting and receiving sides is combined with the justification contained in the received frame.

Abstract: A method of detecting the loss-of-signal condition at the input of a transmission line interface when the input signal is coded. The input signal decoding includes an additional procedure allowing the detection of loss-of-signal condition. Since the pseudo-random sequence of the input signal transitions includes sequences of code violations, the additional procedure, over a certain threshold error rate, corresponding to a number of code violations in a unit of time, detects the loss-of-signal condition.

Abstract: An integrated digital loop carrier (IDLC) system includes digital line feeders and signal processors to interface with the feeders and to ultimately provide data to subscriber instruments. The system can be employed as a central office terminal (COT) or remote digital terminal (RDT) with analog, T1 or SONET feeders and any conventional link medium. Data are put in DS1 format and multiplexed onto token ring optical loops for delivery to banks of channel units wherein the optical signals are translated to electrical signals for delivery to the CUs and subscribers. A method and apparatus is provided for mapping and demapping signals between virtual tributaries (VT) and digital signal formats in the RDT of an integrated digital loop carrier.

Abstract: A method and apparatus for analyzing and monitoring packet streams in “real time”. The packet analyzer comprises an input buffer, a real-time analysis unit, a non-real-time analysis unit, a graphics unit, a monitor and a flushing circuit. A packet stream is received into the input buffer where the data is either read by the real-time analysis unit or flushed by the flushing circuit. Messages are passed between the real-time analysis unit and the non-real-time analysis unit to report on detected errors or to update packet stream information. In turn, real time packet stream information are displayed and updated on a display via the graphic unit. A method of detecting framing errors in a packet stream is incorporated by setting a 9th bit in the input buffer for each byte of data in a packet.

Abstract: When carrying out pre-processing of image signal transmission using the control channel of a full-duplex modem and switching image signal transmission to the primary channel of a half-duplex modem, the answer modem stops the transmission carrier upon confirmation that all “1” signals with 40 bit or more have been received from the calling modem, restarts the reception of all “1” signals after the elapse of a certain period of time, confirms the end of all “1” signals and switches to the primary channel.

Abstract: An audio decoder architecture makes use of various component sharing techniques to conserve hardware and reduce implementation cost. In one embodiment, the audio decoder comprises a bitstreamer, a synchronization controller, a first and second decode controllers, a memory module, a data path, and an output buffer. The bitstreamer retrieves compressed data and provides token-aligned data to the synchronization controller and decode controllers. The synchronization controller initially controls the bitstreamer to locate and parse audio frame headers to extract decoding parameters. The synchronization controller initiates the decode controller which corresponds to an identified compression format, and turns control of the bitstreamer and data path over to the selected decode controller. The selected decode controller then controls the bitstreamer to parse the variable length code compressed transform coefficients.

Abstract: A microcontroller provides an asynchronous serial port with a serial clock derived from the processor clock. Although the serial clock cannot be exactly programmed to yield an ideal frame length at a particular baud rate, an additional register is provided for tuning the frame length. Each transmitted asynchronous serial frame is stretched by a number of either serial clock phases or processor clocks defined in the tuning register. This provides for improved reception of the asynchronous data, because the frame length more nearly matches the ideal baud rate frame length.

Abstract: A method and apparatus for analyzing and monitoring packet streams in “real time”. The packet analyzer comprises an input buffer, a real-time analysis unit, a non-real-time analysis unit, a graphics unit, a monitor and a flushing circuit. A packet stream is received into the input buffer where the data is either read by the real-time analysis unit or flushed by the flushing circuit. Messages are passed between the real-time analysis unit and the non-real-time analysis unit to report on detected errors or to update packet stream information. In turn, real time packet stream information are displayed and updated on a display via the graphic unit. A method of detecting framing errors in a packet stream is incorporated by setting a 9th bit in the input buffer for each byte of data in a packet.

Abstract: An ADSL physical transmission layer retrieves data to be transmitted from either a transmit data buffer, or a dummy cell buffer in the case when no actual data is being transmitted to maintain a continuous data stream in an ADSL data link. The ADSL physical transmission layer and an associated ATM protocol layer are implemented as an interrupt service routine and delayed procedure call respectively in an ADSL software modem application. Because the ATM protocol layer does not fill the transmit data buffer with dummy cell data, it is simpler and faster. Moreover, latency is minimized, and overall system throughput enhanced since the maximum latency is independent of any operating system latency, and is no greater than the size of the cell stored in the dummy cell buffer.