Abstract: A method and apparatus for synchronizing to a time structure associated with base station transmissions in a radiocommunication system are described. A broadcast control channel can contain synchronization symbols within one or more of a plurality of timeslots. The symbols can be provided as periodic, e.g., exponential, signals which introduce a frequency deviation into the broadcast control channel. This frequency deviation can be recognized by the receiver to synchronize to the time structure of the base station transmissions. Moreover, the variation in the frequency deviation caused by phase rotation associated with local oscillator inaccuracy can also be compensated to achieve frequency synchronization.

Abstract: In a terminal apparatus to which an SDH transmission mode is applied, there is a method including a pseudo-synchronization detecting step of detecting, by one transmitter-receiver, that a pseudo-synchronization state is established by finding in data the same pattern as a synchronization pattern in byte information, a pseudo-synchronization posting step of inserting, by the one transmitter-receiver, information to the effect that the pseudo-synchronization state is established in an overhead of an STM frame, and posting the information to the other transmitter-receiver, and a changed synchronization pattern transmitting step of changing a synchronization pattern into an additional synchronization pattern different from the synchronization pattern in the byte information, and transmitting the synchronization pattern obtained by the change from the other transmitter-receiver to the one transmitter-receiver.

Abstract: A method and system for updating clock references in a digital data stream is proposed, wherein all clock references present in the data stream are updated by means of a single system clock. A time recovery unit compares time tpcr transported in the clock reference (PCR) with the time of the system clock tclock and stamps the difference (tclock−tpcr) of the two times into the clock reference. After remultiplexing, a stamping unit reads out the time difference (tclock−tpcr) of the two times from the time stamp, subtracts it from the actual time in the system clock and stamps the value (tpcr+d) into the clock reference. Due to similarities in operation, the time recovery unit and stamping unit may share common circuitry.

Abstract: Synchronizing wireless base stations by reception of a synchronization signal that is transmitted in an unused B channel of an ISDN link interconnecting a switching network and the base stations. The synchronization signals are generated by the tone circuit of the switching network which advantageously is a digital signalling processor (DSP). Each base station is interconnected to the switching network via two basic rate interface (BRI) links. Each base station can handle a maximum of three wireless handsets thus leaving one of the four B channels present in the two BRI links unused. It is this unused link that is utilized to transmit the synchronization signals from the switching network to the base stations. Furthermore, the switching network is configured in such a manner that all base stations receive the synchronization signals at the same time over the unused B channels.

Abstract: In a communication system in which an asynchronous mode is employed as a media access control system, a synchronizing signal of digital data, which are sent out from a sender terminal apparatus and separated into the synchronizing signal and the bit stream data, is converted into block synchronizing signals which consist of a start signal indicating head position of bit stream data and an end signal indicating end position thereof, then the bit stream data and converted block synchronizing signals are converted into compressed block data by multiplexing them not to be overlapped on a time base respectively, and then the compressed block data are transmitted to a destination terminal apparatus via a data transmission line.

Abstract: A method and system for time aligning a frame (60) in a communication network (10) involves the steps of; i) determining if a frame needs to be advanced at a BTS (14), and ii) sending a shortened synchronization pattern from the BSC (12). The BTS (14) then determines if a short or long synchronization pattern has been sent by determining (256) if the received data stream matches a long synchronization pattern and setting a first flag when they do match. If the received data stream does not match the long synchronization pattern and the first flag is set (264), the data stream is compared (266) to the short synchronization pattern. When they match a second flag is set (268).

Abstract: New methods for synchronizing previously unsynchronized BTS's of time division multiple access cellular networks are disclosed. Timing information that is readily available throughout the network is used to determine for each BTS when information representing a particular event is transmitted relative to the timing information. The time differences that are detected are used for steering the clock of each BTS to have the next or some other subsequent event transmitted at the same time.

Abstract: A de-framer (72) in a communications gateway (22) translates videoconferencing information from a circuit-switched format to a packet-switched format. A demultiplexor (78) extracts a bitstream containing video information that includes error-correction-code fields disposed at predetermined locations with respect to synchronization bits spaced by a synchronization interval and forming a predetermined synchronization sequence. A frame checker (88) for checking the error-correction code finds codeword boundaries by comparing the predetermined synchronization sequence with sequences of synchronization-interval-spaced video-bitstream bits until it finds a match. To do so, the frame checker (88) takes a group of video-bitstream words offset from each other by the synchronization interval. It compares each word in the group with a respective synchronization word consisting of a word-width replication of a respective synchronization bit.

Abstract: There is provided an apparatus for detecting a synchronizing signal, including a first circuit for extracting bit clocks from serial data received, a shift register for shifting the serial data bit by bit on the basis of the bit clocks, and latching the thus shifted serial data, a second circuit for counting the bit clocks, and generating word clocks in accordance with the number of count of the bit clocks for outputting parallel data, a third circuit for detecting a synchronization pattern from the serial data stored in the shift register, and generating a first synchronization-detecting signal, a fourth circuit for detecting a synchronization pattern from the parallel data, and generating a second synchronization-detecting signal, and a fifth circuit for determining whether frame synchronization is made, by the first and second synchronization-detecting signals, and generating a frame synchronization indication signal indicative of whether frame synchronization is made or not.

Abstract: In a method and apparatus for detecting a wake packet among data bytes in a packet frame issued by a network device, the data bytes in the packet frame are initially compared with a sync byte to detect start of a synchronization stream of the wake packet. The number of consecutive sync matches of the data bytes in the packet frame with the sync byte is counted, and a partial match flag is set upon detection that the number of consecutive sync matches has reached a predetermined number of sync duplications of the sync byte to indicate that the synchronization stream has been detected in the packet frame. When the partial match flag is set, the data bytes that follow the synchronization stream in the packet frame are compared with address bytes of a destination address assigned to a sleeping node.

Abstract: The invention presents a method of frame synchronization of Digital Video Broadcasting (DVB) data using a temporary storage area (regfile) of substantially smaller dimension than the repetition rate of the sync pattern. Synchronization is achieved by detecting the sync pattern by correlation and determining if the pattern has a fixed repetitive separation. The synchronization scheme of the invention is simple and easily implementable as an integrated circuit, using software and a microprocessor, or as discrete circuitry.

Abstract: There is provided a method of transmitting and receiving a frame including unique pattern information indicative of a starting point of digital information. Step (a) performs a receive synchronizing process in which the frame is pulled in a given phase of a machine cycle equal to m which is equal to (1/N).times.L where L denotes the number of bits forming the frame, N is a positive integer and m is a positive integer larger than 2. Step (b) performs, in a receive process executing phase forming part of a same machine cycle as that of the step (a), a receive process in which receive control channel data contained in a received frame is written into a shared memory in accordance with first m-bit stream program information which defines the receive process and is stored in the shared memory.

Abstract: A transmission apparatus has units to which main signals are input for subjecting these main signals to predetermined processing and then transmitting them. One of these units is a master unit and the others are slave units and they are interconnected by a clock cable and processor-to-processor cable. Each slave unit detects a synchronization status message that has been inserted into a main signal input from a line and notifies the main unit of this synchronization status message via the processor-to-processor cable. Using synchronization status messages acquired from the slave units and a synchronization status message that has been inserted into a main signal input thereto, the main unit obtains the synchronization status message indicative of the best quality level and adopts, as a master clock, a clock extracted from the main signal into which this synchronization status message has been inserted.

Abstract: In an interactive audio-video digital distribution system a pointer is transmitted at least once every T milliseconds to indicate the position of a time marker. An interruption (V) occurs every T milliseconds. A given number N of integer frames being transmitted in T milliseconds, there remains only space for transmitting a portion containing R symbols of the N+.sup.th frame before the next interruption. Following transmission of a signaling packet (x) with a pointer indicating a number (x) of symbol periods, during the next interruption N packets will have been completely transmitted since the last pointer, plus R symbols. The end of the transmission of this packet is waited for, that is, U.dbd.C-R symbol periods before a new signaling packet (x-U) is transmitted. The value of the pointer contained in this packet will thus have to take this offset into account as it is decremented by U symbols, that is, x-U, and so on.

Abstract: In a digital communication system for voice signals, a system and method for recovering the timing of a pseudo-random noise (PN) sequence used for direct-sequence spreading and despreading of the communicated signals. In one embodiment, a received signal is a time-division duplexing (TDD) or time-division multiple access (TDMA) signal, and a receiver performs a complete "sliding correlator" examination of the received signal in a fixed time by using the timing of the TDMA or TDD frames. This examination allows a rapid initial acquisition of the PN synchronization. In another embodiment of the receiver, the initially acquired PN phase is verified by reading a SYNC field from the received signal and by checking that shifting the receiver's local PN phase results in a degraded correlation between the local PN sequence and the received signal.

Abstract: To test the processing of a data frame processing unit (FPU) which, in a normal working mode, processes input data frames applied to a data frame input (FI) thereof, the data frame processing unit (FPU) is brought in a test mode. Therefore, an active test signal is applied to a test mode control input (TCI) of this data frame processing unit (FPU). When brought in the test mode, the frame counters of the data frame processing unit (FPU) have lower limits and test data frames with smaller dimensions than the input data frames applied to the data frame input (FI).

Abstract: A burst frame phase synchronizing circuit is disclosed, whereby the generation of erroneous synchronization caused by the phase fluctuation of received data or a bit error is prevented. A transmission error monitoring circuit 15 monitors a transmission error and outputs error information, and a transmission error statistical circuit 14 outputs protection information obtained by summing up the statistics of transmission errors. A frame synchronizing pattern comparator circuit 11 makes a comparison for bit strings between burst data at the time of transmission and a specified synchronizing pattern and outputs comparison information obtained based on the production state of a noncoincidence bit. A synchronization protective circuit 13 selects a permissible noncoincidence bit number and outputs a frame synchronizing signal satisfying a specified protection condition.

Abstract: A TDMA system receiver detects an offset amount of a carrier frequency of a received signal. A receiver for receiving a signal, including a periodic burst signal, includes a receiver unit for receiving a signal including a burst signal, a phase detecting circuit for detecting a phase of a predetermined pattern in a first burst signal and for detecting a phase of a predetermined pattern in a second burst signal, a calculating circuit for calculating an offset amount of a carrier frequency, and a correcting unit for correcting the offset amount of the carrier frequency.

Abstract: A radio base station inter-station synchronizing circuit is disclosed that is provided in a radio base station device of a TDMA digital mobile communication system and that synchronizes the frame timing generated by each radio base station. The synchronizing circuit includes: data reception/comparison circuit 4 that outputs data match signal S9 when synchronizing signal data transmitted from a synchronized timing control station provided in a mobile communication system match with the same synchronizing signal data held by that radio base station; delay time correction counter 5 that, upon receiving the data match signal S9, subtracts from the timing of the received synchronizing signal data line delay time from the synchronized timing control station to that radio base station; timing holding circuit 8 that holds the corrected synchronized timing; and frame timing generation circuit 9 that generates and outputs frame timing from the output pulse of the timing holding circuit 8.

Abstract: A transmission frame comprises a locking row, synchronization bits and data bits, the synchronization bit being placed immediately after the locking row. The frame terminates with a synchronization bit. A transmitter and a receiver are linked by a transmission channel carrying these frames.

Abstract: A byte aligner and frame synchronizer for 622 Mbit/s high speed data includes a clock divider, a data width extension circuit, a byte alignment controller, a byte alignment circuit, a pattern selector, a continuous pattern detector, a frame pulse generator, a frame sync detector, a frame sync loss detector, and frame sync error detector, and performs byte alignment very fast while also stabilizing frame synchronization by reinforcing an error correction function.

Abstract: A method of transferring payload, control and messaging data in a communications system, in a serial data stream at a pre-set bit rate per second is disclosed. The method comprises, transferring a chosen integer number of frames of serial data per second. Each frame comprises a number of timeslots of data. Each timeslot comprises a predetermined number of first bits comprising payload related data or messaging bits and a calculated number of second bits comprising control bits. The calculated number is calculated so that the sum of the predetermined number and the calculated number multiplied by the number of timeslots and the chosen integer number equals the number of bits transferred in one second at the pre-set bit rate. Preferably, bits from the second bits at fixed intervals within the serial data stream comprise a out-of-band communications channel with the stream. Preferably, the pre-set bit rate is synchronized to the clock of a host communications system.

Abstract: A synchronization method and apparatus for synchronizing a receiver, such as a radiotelephone operable in a cellular communication system with a transmitter. Synchronization signals are transmitted as parts of a control signal to the receiver. Such synchronization signals are of high margins and also permit synchronization of the radiotelephone responsive to a reduced number of calculations. The time for such synchronization is reduced by use of nonlinear transformation metrics, such as logarithmic metrics, which reduce the impact of a noise or error component within the control signal.

Abstract: A timing generator synchronizes a mobile station internal timing with a base station in a TDMA cellular communication system. A random access memory is used to store an event list comprising a series of events which must be executed periodically at precisely timed intervals. Each event in the event list includes an event time and an event code. The events are stored in the random access memory in the order in which they are to occur. The timing generator of the present invention uses a primary counter, a secondary counter, a synchronizing register, a comparator and a signal generator to control the execution of the event in the event list. The primary counter and secondary counter are both clocked at the same rate. The events are read one at a time from the event list into a compare resister. The event time is compared to the value of the secondary counter. When the event time matches the secondary counter value, the event action is passed to the signal generator which decodes and executes the events.

Abstract: A central station and each base station have a timer indicating time instants coincident with each other. A common transmission start time instant is provided from the central station to each base station so as to match the transmission start time instant to start transmission of the signal frame in each station. The central station makes the call requests of different bit rates contained in one signal frame and broadcasts to each station the transmission start time instant for the signal frame, the order of the call requests within the signal frame, and bit rate switch timings. When the transmission start time instant arrives, the base station reproduces call signals from the call requests in accordance with the designated order. Reproducing clock pulses are switched with reference to the bit rate switch timings sent from the central station. Thus, each station can transmit the call signals of the different bit rates in one signal frame with their phases coincident with each other.

Abstract: A method for frame synchronization including the detection of an n-bit pattern with predetermined characteristics in a bitstream is described. The subject method includes the steps of extracting a first set of m bits, with m being smaller than or equal to n, from a first position in said bitstream, deriving from said first set an address of a location in a first memory, deriving from the contents of said location in said first memory at least one second position in said bitstream and at least one second set of bits to be extracted therefrom until said n-bit pattern is detected in said bitstream. An apparatus for performing the subject method is additionally described.

Abstract: In a time division multiplex (TDM) signal in which a symbol is sent one by one periodically, a unique word in the TDM signal is recognized quickly in a receiving station. A receive station has essentially N number of correlators each having a specific unique word pattern. A unique word pattern in each correlator is obtained by shifting by predetermined symbols cyclically from a reference unique word pattern. Each correlator provides a correlation value between a received TDM signal which includes a unique word and a unique word pattern defined in the correlator. Among outputs of N number of correlation values, which exceed a predetermined threshold value, the correlator which provides the maximum correlation value is selected, and the receive timing of the unique word is determined by the correlator thus selected.

Abstract: A data communication device (500) which is capable of providing inverse multiplexing, avoids having to perform address offset calculations by storing the incoming data from each of its incoming data channels in corresponding data buffers having predefined data structures which eliminate the need for offset calculations during data transfers and protocol processing. The communication device (500) compares the actual address location that a particular byte, such as a frame count byte, is presently stored in the data buffer and the address location it should be stored in order to avoid using offset calculations. If the actual location the frame count (FC) byte is located in is not the desired location the frame count byte should be located, the communication device (500) programs its SCCs (508, 510) to commence storing subsequent data bytes in the appropriate address locations in each of the data buffers found in memory (538) so as to avoid having to perform offset calculations during memory accesses.

Abstract: A method of processing wireless signal of data pulses or packets in a communication system, in which a portion of the data pulses in an individual signal are utilized to determine a rate of time shift for eliminating or minimizing the effects of Doppler shift in the intra-data pulse processing. One embodiment of the invention provides a method of utilizing the time refinement section of a JTIDS waveform for the purpose of determining an intra-burst data correction factor based upon the average shift of the midpoint of the sampled time refinement section pulses.

Abstract: In a packet transmission system for transmitting a bit stream of a prescribed rate while also packeting the bit stream, a transmission side is provided with a unit for periodically providing the packeted bit stream with the position information of the head bits thereof and a circuit for adding each packet with the time of the supplied head bit position, and a reception side is provided with a temporary storage memory for temporarily storing the received packet, a data extractor for extracting the time of the head bit position which is added to the received packet, and a read-out controller for controlling the rate of a read-out operation of the bit stream from the temporary storage memory using the extracted time.

Abstract: A method to encode and to decode frames of data used in synchronous protocols, including HDLC and SDLC. The invention operates on blocks of data, such as data bytes or data words, in a parallel rather than a bit serial manner. The invention compares an aligned block of data with reference bit sequences for flag or abort signal detection, for zero detection, for zero deletion, for detection of consecutive one bits, and for zero insertion following a stream of consecutive one bits, for encoding and decoding according to various protocols. The invention also maintains proper data alignment following such zero insertions or deletions, and provides encoding and decoding under both data overrun and data underrun conditions.

Abstract: A frame synchronization circuit which detects a frame synchronization bit allotted in a particular position within a receiving data string includes a shift register, a synchronization pattern detection circuit and a control circuit. The shift register receives and stores the receiving data string and outputs a parallel data string. The synchronization pattern detection circuit receives the parallel data string outputted from the shift register in synchronization with a clock signal and makes decisions simultaneously on the matching/non-matching of a parallel data string of totally r bits disposed in an n bit cycle within the receiving data string with r kinds of predetermined synchronization patterns of r bits. The control circuit receives an output of the synchronization pattern detection circuit, and outputs either a signal indicative of the in-synchronization state through a terminal or a signal indicative of the out-of-synchronization state through a terminal.