Abstract: A novel clock method and synchronization mechanism for recovering and distributing a centralized clock source synchronously over legacy asynchronous network devices such as legacy optical Ethernet devices that do not support synchronous Ethernet. An external device functions transparently to provide legacy optical Ethernet devices a clock synchronization and distribution mechanism. The external devices implement a clock conversion scheme whereby multiple clocks having diverse rates are converted to clock signals all having a common rate. One of the converted clocks is selected and all downstream clock signals are then derived from this clock. A high quality clock source located anywhere on the network is distributed throughout the network thus turning an asynchronous Ethernet network into a synchronous Ethernet network. Synchronous TDM data streams can then be easily transported over the Ethernet network.

Abstract: High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.

Abstract: In one embodiment of the invention, a clock-and-data-recovery (CDR) system has a multi-phase clock generator that generates a plurality of phase-offset clock signals and one or more channel circuits, each receiving a (different) input data signal and all of the phase-offset clock signals and generates an output data stream and a recovered clock signal. Each channel circuit has a plurality of data registers (e.g., flip-flops), each receiving the input data signal at its clock input port and a different one of the phase-offset clock signals at its data input port, such that the flip-flop is triggered at each (rising) edge in the input data signal. The channel circuit processes the outputs from the different flip-flops to select an appropriate phase-offset clock signal for use in sampling the input data signal to generate the output data stream, where the recovered clock signal is generated from the selected phase-offset clock signal.

Abstract: One disclosed embodiment may comprise an interpolation system that includes an interpolator that interpolates between a selected phase from a preceding cycle and a selected phase from a current cycle to provide an interpolated phase for the current cycle. An edge of the interpolated phase for the current cycle has reduced jitter relative to an edge of a corresponding phase of the current cycle. A delay system delays a plurality of other phases of the current cycle to provide delayed other phases, the delayed other phases and the interpolated phase for the current cycle collectively defining a set of adjusted phases for the current cycle.

Abstract: One or more clocks are synchronized across a communication link using a synchronization signal sent from a master to a slave clock. The synchronization signal may be an expected signal pattern sent at intervals expected by the slave. The slave clock may correlate received signals with a representation of the expected synchronization signal to produce a correlation sample sequence at a first sample rate. The synchronization signal receipt time is compared to the expected time and the slave clock is adjusted until the times match. Master and slave clocks synchronized across the communication link constitute a noncommon clock which may be compared on each side of the link to secondary independent clocks. The secondary independent clocks may be separately synchronized by adjusting one to have the same difference from its local noncommon clock as the secondary clock on the other side of the link has from its local noncommon clock.

Abstract: A communications system includes a physical layer device (PLD) and a logical link device (LLD), each having respective send and receive interfaces being substantially identical to define symmetrical interfaces for the system. Accordingly, design and manufacturing is simplified compared to conventional systems. In addition, advantages are also provided in terms of loopback capability and packaging options. The PLD comprises a PLD send interface including PLD parallel information outputs, and a PLD receive interface including PLD parallel information inputs. Similarly, the LLD comprises an LLD receive interface including LLD parallel information inputs, and an LLD send interface including LLD parallel information outputs. Parallel communications channels connect the PLD information outputs to respective LLD information inputs, and connect the LLD information outputs to respective PLD information inputs.

Abstract: In a packet-based (e.g., Ethernet) network, such as the network of central offices and base stations of a wireless telephone system, a node receives one or more incoming packet-based signals from one or more other nodes of the network and recovers a clock signal from each incoming packet-based signal. The node selects one of the recovered clock signals as the node's reference clock signal. When the node is part of a base station, the node uses the selected clock to generate and transmit one or more outgoing packet-based signals to one or more central offices. The node also uses the selected clock to generate the base station's wireless transmissions. In one implementation, the base stations and central offices are connected by Ethernet facilities.

Abstract: An improved DDR interface uses single-ended technology and phase-shifts all output data signals and the output source clock signal so that each output signal switches at a different time so that IDDQ spikes caused by I/O switching do not accumulate. A dynamic phase adjustment circuit on the receiver compensates for the phase differences. Clock jitter and skew is reduced and the number of IDDQ pins is reduced to provide a more effective design and high density package.

Abstract: A communications system includes a physical layer device (PLD) and a logical link device (LLD), each having respective send and receive interfaces being substantially identical to define symmetrical interfaces for the system. Accordingly, design and manufacturing is simplified compared to conventional systems. In addition, advantages are also provided in terms of loopback capability and packaging options. The PLD comprises a PLD send interface including PLD parallel information outputs, and a PLD receive interface including PLD parallel information inputs. Similarly, the LLD comprises an LLD receive interface including LLD parallel information inputs, and an LLD send interface including LLD parallel information outputs. Parallel communications channels connect the PLD information outputs to respective LLD information inputs, and connect the LLD information outputs to respective PLD information inputs.

Abstract: A method and apparatus for processing packetized data spanning multiple clock cycles includes at least one comparator, for comparing a present clock cycle count to a reference clock cycle count, wherein the reference clock cycle values may be anywhere within the packet and may be non-contiguous with other reference clock cycle values. At least one word recognizer, compares a presently clocked word to a reference word, and an output circuit provides an indication of a favorable word comparison that occurred in response to a favorable clock cycle count comparison.

Abstract: Provided are a clock signal selecting apparatus and method that can guarantee the continuity of an output clock signal. The clock signal selecting apparatus and method can synchronize the phases of at least two clock signals by continuously controlling the phases of the clock signals. Accordingly, even when an active clock signal and a standby clock signal have different frequencies, it is possible to guarantee the continuity of the output clock signal regardless of whether the clock signals are switched from one to another. In addition, it is possible to guarantee the stability of the output clock signal.

Abstract: In a wireless communication system using a reference channel used for error rate measurement and associated with a plurality of transport channels multiplexed on a coded composite transport channel (CCTrCH), a method is employed for reselection of the reference channel from favorable candidate transport channels. A channel is initially selected from the plurality of multiplexed channels as the reference channel. Channels are monitored based on quantitative data content criteria to determine whether an ON or OFF state exists. A different channel is selected from the plurality of multiplexed channels as the reselected RTrCH when a better candidate transport channel in the ON state becomes available, or when the monitored RTrCH reflects an OFF state.

Abstract: A method for optimizing phase factors in partial transmit sequence orthogonal frequency division multiplexing system. The method includes initializing sub-block signals by applying an initial phase factor to the sub-block signals in all sub-blocks; setting a reference peak value with a peak value of a signal formed by combining the sub-block signals; selecting a phase value that minimizes the peak value of an output signal as the phase factor of each sub-block by applying a next phase value to each sub-block signal as the phase factor, and repeating this with respect to the remaining available phase values.

Abstract: Systems and techniques are disclosed for establishing a reference corresponding to the timing of a received signal from the first source, determining the timing for each received signal from a plurality of second sources, adjusting the reference to the timing of the received signal from one of the second sources, the timing of the received signal used to adjust the reference being closest in time to the unadjusted reference, and synchronizing a signal to the reference for transmission.

Abstract: In a method for the set-up of a connection in a communication network, the set-up is initiated with an initial message (12) from an originating control node (ON) to a terminating control node (TN) of the connection and the establishment of a bearer for the connection is initiated according to a reply to the initial message (12). A control timer (CT) is started according to the initial message (12) and an expiry of the control timer (CT) before an indication of the bearer establishment triggers a release for the connection. In the method, after receiving the initial message (12) at the terminating control node (TN), a paging (13) a user equipment (UE?) for the connection and starting a first timer (FT) according to the paging (13) initiation is performed, the expiry value of the first timer (FT) being set lower than the expiry value of the control timer (CT).

Abstract: Method embodiments for achieving hyperframe symbol synchronization are disclosed, along with device and system embodiments for implementing such methods. In one embodiment, the method comprises: receiving a pilot signal having at least two phase states; measuring the pilot signal as a sequence of measured symbols; and determining an alignment offset upon detecting between adjacent measure symbols a phase difference greater than a predetermined threshold. The alignment offset determination may include: forming a data field of four measured symbols around the detected phase difference; searching for the position of a two-symbol window in the data field that maximizes a phase difference; and calculating the alignment offset from this position.

Abstract: A high-speed bit stream data conversion circuit receives a first bit stream(s) and recovers a clock signal from the first bit stream(s). The data conversion circuit then produces a second bit stream(s) having a second lower bit rate. A control loop adjusts the phase relationship of the recovered clock signal to the first bit stream(s) to minimize data loss when the first bit stream(s) is sliced to produce the second bit stream(s). A reference clock signal produced within a clock circuit is divided to produce a reduced frequency reference clock, which is multiplexed with a test clock signal to produce an output signal. Differentially dividing the output signal produces a series of input signals for an interpolator that selectively weighs and sums the input signals as directed by the control loop to produce the recovered clock signal with the desired phase relationship relative to the first bit stream(s).

Abstract: A clock reconstruction mechanism for synchronous TDM communications traffic transported over asynchronous networks such as Ethernet networks. The invention is applicable to edge switches in Metropolitan Area Networks (MANs) that transport legacy TDM traffic using a Circuit Emulation Services (CES) module whereby TDM traffic is encapsulated and transported across the Ethernet network where it is de-encapsulated and clocked out to the destination. The mechanism encapsulates the input TDM data stream into Ethernet packets and inserts a network timestamp within the packet. At the destination CES, a local timestamp is generated for each received packet as it is received. The network timestamp is extracted and input along with the local timestamp to a Digital Time Locked Loop (DTLL) which is operative to accurately reconstruct the original transmit TDM clock.

Abstract: Apparatus for use in providing full-rate clock data retiming in a time division multiplexer, wherein the time division multiplexer includes an N to 1 time division multiplexer circuit and a retiming circuit, comprises the following circuitry. The apparatus comprises first circuitry for generating a half-rate clock from a full-rate clock used by the retiming circuit and for providing selective adjustment of a phase associated with the half-rate clock within a range of D degrees. The apparatus further comprises second circuitry, coupled to the first circuitry, for generating a set of sub-rate clocks from the phase-adjustable half-rate clock for use by the N to 1 time division multiplexer circuit in generating a multiplexed data stream from N parallel data streams, such that the retiming circuit is able to operate within a clock phase margin associated therewith. Phase adjustment need not be dependent on a rate associated with the multiplexed data stream, and may be continuous or discrete.

Abstract: When a map screen is displayed in a navigation system of a subject vehicle, a position of any other vehicle is estimated and is displayed in the map screen. Influence of delay due to the following is eliminated or reduced: time consumed in processing in a navigation system of the other vehicle; time consumed in communication between the navigation system of the other vehicle and the navigation system of the subject vehicle; time from when the navigation system of the subject vehicle receives communication information to when it generates information to be notified; and the like. In cases where the influence of delay is taken into account, as mentioned above, accuracy of a notified position of the other vehicle is enhanced. Thus, an accurate operation support system is provided to minimize occurrence of errors.

Abstract: The uplink transmission timing from a mobile communications device is defined with reference to the downlink reception timing of signals from a particular reference cell. When that reference cell is removed from the active set, there is defined a virtual reference cell, the timing of which is defined with reference to one or more of the cells remaining in the active set, such that the timing of this new virtual reference cell corresponds to the timing of the previous reference cell. The timing of the uplink transmission from the user equipment are then defined with reference to the new virtual reference cell, in the conventional way. This has the advantage that, following a soft handover, it is not necessary to adjust the timing of uplink transmissions from the user equipment.

Abstract: A programmable layered sub-system interface includes an extension sub-layer module, a physical coding sub-layer module, a physical media attachment module, an input module, an output module, a 1st switch module and a 2nd switch module. The 1st switch module is coupled between the physical media attachment module and the physical coding sub-layer module. The 2nd switch module is operably coupled between the physical coding sub-layer module and the extension sub-layer module. The input and output modules are operably coupled to the 1st and 2nd switch modules. The 1st switch module provides various combinations of coupling between the physical media attachment module, the physical coding sub-layer module, the input module and the output module. The 2nd switch module provides combinations of coupling between the extension sub-layer module, the physical coding sub-layer module, the input module and the output module.

Abstract: System and method for compensating for DS0 timing source transients, such as may occur during a switchover to a new external reference, is described. In one embodiment, an SFI control signal is monitored for embedded frame position information. When the frame position information is initially detected, a 10-bit frame clock counter is reset to zero. The counter is then incremented using an 8.192 MHz clock. From that point on, each time the SFI frame position information is detected, the value of the frame clock counter is checked. If the counter value is zero, the counter continues to run freely. If the counter value is non-zero and the most significant bit (“MSB”) thereof is zero, the count of the frame clock counter is held for one clock period. If the counter value is non-zero and the MSB thereof is one, the count of the frame clock counter is advanced by a value of two, rather than one, for one clock period.

Abstract: An integrated services digital network private branch exchange, which is capable of automatically choosing a synchronization clock source. The integrated services digital network private branch exchange comprises a plurality of trunk chips, a plurality of subscribe chips, and a plurality of priority selection circuits. Wherein, the trunk chips connect to the network terminal via the trunk interface, and then connect to the central office via the network terminal to receive the frame synchronization clock output signal and the data clock output signal. Whereas, the subscribe chips connect to the terminal equipment via the subscribe interface. The priority selection circuits that are connected to each other in a daisy chain circuit manner are connected to the trunk chips to send out the frame synchronization clock output signal and the data clock output signal.

Abstract: A timing error correction technique for use in data communications receivers such as WLAN (Wireless Local Area Network) receivers is provided where an input signal is received that has a timing error, the timing error is corrected, and a signal having a corrected timing error is output. The timing error correction comprises performing an early-late correlation on the signal that has the corrected timing error. The early-late correlation comprises the generation of at least one early and late sample pair, the generation of an error signal that is indicative of the difference between the early and late samples, and the generation of at least one control signal based on the error signal. A time offset correction algorithm is performed dependent on the control signal.

Abstract: In an oversampling clock recovery circuit comprising first through fourth phase comparators (PD1 to PD4) and a majority circuit (10), DOWN signal output terminals (DN2(out), DN3(out)) of the second and the third phase comparators are connected to UP signal input terminals (UP3(in), UP4(in)) of the majority circuit and UP signal output terminals (UP3(out), UP4(out)) of the third and the fourth phase comparators are connected to DONW signal input terminals (DN2(in), DN3(in)) of the majority circuit.

Abstract: There is disclosed a sample selection and data alignment circuit that is able to recover (retime) a data on a predefined phase of a multiphase clock signal. A plurality of over sampled signals (G0, . . . , Gn?1) is obtained by over sampling an incoming serial binary data (bits) stream with the n phases (G0, . . . , Gn?1) of a multiphase clock signal. A reliable over sampled signal is selected according to a selected signal (G0, . . . , Gn?1) generated by an edge detector which designates which over sampled signal is the best for subsequent processing.

Abstract: Method and circuitry for de-skewing data in data communication networks such as a SONET. The data is sent from a system chip to a framer chip where the data is de-skewed. To detect data skew, the system chip sends a training sequence to the framer chip. The information bits sent to the framer chip are searched in order to detect the training sequence. The training sequences contain clear transition patterns at which all 16 bits of the transmit data and the TCTL signal line are inverted. If any bit does not invert, this bit must be a skewed bit. Based on the data one clock cycle before and one clock cycle after this transition, the skewed bit can be corrected back. After the data skew is detected, a multiplexing logic circuitry is used to correct the skew based on one clock cycle either before or after the transition. The multiplexing logic circuitry includes at least three registers coupled to the inputs of the multiplexing logic circuitry.

Abstract: Method and apparatus for reducing effect of jitter is described. More particularly, one or more taps of a delay line are selected for a reference clock signal. These selected taps each have an associated index, which is stored, and stored indices are statistically processed to select a tap of another delay line.

Abstract: A changeover arrangement for the clock signals of parallel transmission connections of an assured data transmission link, wherein a clock signal is sent for the transmission paths by parallel outdoor units (OU) located in succession to a common indoor unit (IU), the clock signal is received by a corresponding set of second outdoor units, where phase locked loop signals are used to achieve the lock to the signal, and subsequent to which a second IU receives information of the mode of the phase lock. In addition, when errors are caused in the employed connection, the receiving unit selects a transmission path that has fewer errors based on mode information obtained from the outdoor unit.

Abstract: A method for synchronizing a service clock at a destination node with a service clock at a source node is provided. The method includes receiving data packets from a source node at at least one port of the destination node. At the destination node, the method determines control values for a numerically controlled oscillator for a plurality of time periods. The method selectively uses the control values to set the frequency of a service clock at the destination node for use in receiving data packets.

Abstract: A technique for embedding a first clock phase within a second signal is described. In one embodiment, the invention comprises a method of embedding a phase of a first signal within a second signal comprising the steps of monitoring a first signal for a frame event, responsive to detection of a frame event in the first clock signal, determining a position of the frame event relative to a current segment of a second signal, and embedding in the current segment of the second signal a value representative of the relative position of the detected frame event.

Abstract: A digital-to-phase or digital-to-time-shift converter (100) includes a delay line (106), a multiplexor (108) and synchronization circuit (110). In the converter (100) the clock edges of a reference signal are shifted in response to the value of a multi-bit digital word, IN (104). The synchronization circuit (110) gates the output of the multiplexor (108) such that a pulse appears at the synchronization circuit's (110) output port (114) only when the circuit is gated by a signal at input TRIG (112). The synchronization circuit (110) creates a time aperture for the multiplexor output.

Abstract: Method and apparatus is described for decoupling data from a clock signal and recoupling the data to a different clock signal for subsequent synchronous processing by a pointer processor. More particularly, on a receive or drop side, one buffer is configured to store payload pointers and a synchronous payload envelope arriving clocked by a line clock signal, while another buffer is configure to store TOH or SOH arriving clocked by the line clock signal. Each buffer clocks out such stored information off of a same system clock signal, such as a drop clock signal. On a transmit or add side, a buffer is configured to store payload pointers and a synchronous payload envelope. This buffer clocks in such stored information off of a system clock signal, such as an add clock signal, and clocks out such stored information off of a transmit reference clock signal.

Abstract: A method and an apparatus are provided for synchronizing clock signals in spatially distributed nodes in large, synchronous electronic, optical, optoelectronic or wireless systems, such as systems comprising arrays of microprocessors and memories, and telecommunication systems. The nodes comprise a master node and a plurality of slave nodes. The master node generates first and second identical pulse trains and propagates them to the slave nodes via a first and second propagation channels, respectively, so that a pair of pulses, one from each pulse train, arrive at each slave node substantially simultaneously, travelling in opposite directions. Each slave node generates a clock signal event in response to the substantially simultaneous arrival of each pair of pulses. The master node maintains the rate of the two pulse trains such that there are “pN” pulses in each propagation channel at any time, where “N” is the number of nodes and “p” is an integer.

Abstract: A detector detects timing in a digital data flow with a bit-time equal to T. A first circuit generates four local timing signals each having periods substantially equal to the bit-time. Each of the four local timing signals are out of phase with one another by ¼ period. A second circuit samples the four local timing signals upon each transition of a first type for determining, based upon the sampling, whether two of the four local timing signals forming a pair of reference signals that are out of phase by ½ period are advanced or delayed relative to the timing of the data flow. The second circuit controls the first circuit for delaying or advancing the four local timing signals based upon the pair of reference signals.

Abstract: An apparatus comprising an analog circuit and a digital circuit. The analog circuit may be configured to generate a plurality of samples of an input signal in response to a plurality of phases of a reference clock. The digital circuit may be configured to generate an output signal and a clock signal in response to the plurality of samples and the plurality of phases. The clock signal is generally aligned with the output signal.

Abstract: Systems and methods are disclosed for time synchronization of operations in a control system. Synchronization networks and devices are provided for transferring synchronization information between controllers in a distributed or localized control system, which is employed in order to allow operation of such controllers to be synchronized with respect to time. Also disclosed are synchronization protocols and hardware apparatus employed in synchronizing control operations in a control system.

Abstract: A switching circuit is for switching an output thereof to one of a plurality of N input clock signals which are delayed relative to one another. The switching circuit includes at least one circuit responding to a control signal to enable the transmission, on an output signal, of a new signal of the plurality of input signals. The new signal is advanced or delayed relative to a current signal of the plurality of input signals which is currently transmitted on the output signal. The at least one circuit enables the transmission of the new signal before disabling the transmission of the current signal on the output signal. This substantially prevents the production of false signals during the switching of the output signal from one of the clock signals to another.

Abstract: A desynchronizer for desynchronizing one or multiple channels of SONET/SDH data signals, which includes a first in first out (FIFO) buffer having an input coupled to said data signals and an output for outputting asynchronous data obtained from one or more of said SONET/SDH data channels. An arithmetic unit coupled to the FIFO performs all operations required for single or multi-channel desynchronization. An endless phase modulator is coupled to the arithmetic unit and to the FIFO and is operative, in response to input from the arithmetic unit, to produce a single output desynchronized clock or multiple output desynchronized clocks.

Abstract: A high-resolution, per-packet measurement tool for analyzing a computer network that operates by sending a predetermined number of packets from a sender machine to a receiver machine with measurement information inserted into the packet. The system kernel at the sending machine stamps a sequence number and the sender's local time into the data section of each packet. When packets arrive at the receiver machine, they are similarly stamped by the receiving machine's kernel with the receiving machine's local time. The maintained packet information serves as the basis for latency analysis. For example, one set of latencies can be obtained with QoS mechanisms turned on, and another set with QoS mechanisms turned off, whereby the benefits of the QoS mechanisms can be accurately determined. To analyze the latencies, the present invention normalizes each time and each latency into relative latency information. Clock skew and timer jumps may be handled as part of the normalization.

Abstract: Apparatus and methods are provided for exploiting the existence of a shortest path between a source device and a destination device by identifying the shortest path and using the signal which has taken the shortest path in preference to delayed transmissions or delayed images of the same signal, thereby improving signal distribution. The present invention provides a processor between a phase-sensitive detector and a low pass filter of a phase locked loop for selecting and driving the PLL primarily from the signal which has taken the shortest path.

Abstract: Real-time communication of multimedia data over heterogeneous networks that may include constant delay networks, variable delay networks that have a common reckoning of time, and variable delay networks that do not have a common reckoning of time. If there are any variable delay networks in which there is no common reckoning of time in the heterogeneous networks, a common reckoning of time is established in each of those networks. Then, a constant delay network is emulated for each variable delay network using the specific common time reckoning present in each variable delay network.

Abstract: A broadband terminal interface unit for use in an HFC communication network includes a phase-locked loop for providing a smooth transition between a CMTS-provided “national” clock and a local clock when the CMTS clock is lost (or before it is required). By controlling the tracking range of the PLL, the sensitivity of the circuit is controlled so that some drift in the national clock can be accommodated without unnecessarily reducing the performance of the components within the broadband terminal interface unit.

Abstract: A method, apparatus and system detects a loss of synchronization between a transmitter and a receiver in a multiple-carrier communication system such as an OFDM system. A phase-frequency synchronization detector determines when the receiver has lost synchronization with the transmitter based on a phase-frequency relationship of plurality of pilot signals transmitted at different frequencies from the transmitter and received at the receiver. A loss of synchronization is detected when a slope of a line defined by the phase-frequency relationship exceeds a timing threshold more at a rate in excess of an occurrence threshold within a time period.

Abstract: A receiver portion of a multichannel communications link uses optical components to receive data in parallel. Further, the receiver portion of the link provides various functions, including clock recovery, clock-to-data alignment and deskewing. The clock-to-data alignment provides for a dynamically adjusted clock that is used to regulate the output flow of data from the receiver portion, either in parallel or in series.

Abstract: A method and a circuit for regenerating a clock signal based on a flip-flop and on two complementary signals at the clock rate, the flip-flop being assembled as a divider by two of a combination of shaping signals each translating a direction, respectively rising or falling, of the edges of one of the complementary signals, and one of said shaping signals being used to reset the flip-flop.

Abstract: A method of recovering data from a modulated data signal includes tracking a transmitted clock with a plurality of locally-generated clock phases, estimating an average phase of previously detected edges, registering a pulse edge in the received stream of data at a transition phase corresponding to one of the plurality of locally-generated clock phases, determining whether a first symbol was received multiple times consecutively prior to the registered pulse edge, and using the determination of whether the first symbol was received multiple times consecutively in a receiver decision process.

Abstract: A method of extracting a clock signal from a data stream, by generating a plurality of multiphase clock signals, selecting one of the multiphase signals based on synchronization states identifying which of the multiphase clock signals is most closely aligned with the data stream, and sampling the data stream using the selected multiphase signal to produce a retimed data signal. The multiphase clock signals may be subharmonics of the data stream. The selecting step may include the determination of whether the multiphase clock signals are either early or late with respect to the data stream, particularly using D-type flip-flops. The synchronization states are used to define which of the rising edges of the multiphase clock signals is most closely aligned with an edge of the data stream. A multiphase voltage-controlled oscillator may be used to provide the multiphase clock signals.

Abstract: In a communication system capable of establishing synchronization among a plurality of communication apparatuses, a master node transmits a WC packet including a system time and a sample count to a transmission node and a reception node. The transmission node transmits a data packet to the reception node while establishing synchronization by using the WC packet. The reception node processes the received data packet while establishing synchronization by using the WC packet.