Abstract: A transmission apparatus performs communication with a transmission side transmission apparatus via a transmission path of an active system and a transmission path of a standby system. The transmission apparatus includes: a memory configured to have a capacity that is as large as delay caused due to a maximum path difference between the transmission path of the active system and the transmission path of the standby system is allowable; and a memory connection control unit configured to switch connection of the memory and cause a signal of the transmission path of the active system or the transmission path of the standby system to be accumulated in the memory.

Abstract: A communication method enables a base station to allocate a radio resource to a data packet of a time sensitive networking (TSN) network in a scenario in which the TSN network transmits the data packet through a 5G network. The method includes: obtaining, by an access network device, a first traffic pattern, and allocating a radio resource to a first traffic based on the first traffic pattern. The first traffic pattern includes time information of the first traffic with respect to a first clock. The first clock is a clock used by a first network. The access network device belongs to the first network. The time information includes a time point and/or a period at/in which a data packet of the first traffic arrives at the first network.

Abstract: Technology for identifying potentially fraudulent user behavior related to the capture and transmission of vehicle trip telemetry data is provided. Automatic and periodic attempts may be made to wake up (e.g., launch, or change to an active mode) an application installed on a mobile device configured to transmit mobile device data, including captured sensor data, to a remote computer device. Based on the sensor data, the remote computer device may determine a number, frequency, and/or duration of vehicle trips associated with the user of the mobile device. When one or more types of expected mobile device data are not received by the remote computer device after a particular attempt to wake the application, data indicating a failure to receive expected mobile device data may be recorded in a log. Based on the log, an alert indicating potentially fraudulent behavior associated with the user of the mobile device may be generated.

Abstract: A management device of a transmission system includes a new path information input unit, a statistical information collecting unit that collects statistical information of actual traffic from nodes, and an uninterruptible path designing unit that calculates a delay fluctuation in an entire path with respect to a fluctuation for each section of the path, and designs a path in which the calculated delay fluctuation is smaller than a maximum fluctuation amount according to a buffering amount in the reception node as an uninterruptible path, a path information setting unit that updates path information of the path and stores the updated path information in an existing path information storage unit, and sets a bandwidth permitted in a node constituting the path in the node, and a notification unit that notifies a user of a path that was not designed as the uninterruptible path.

Abstract: A communication method includes generating at a first node, a message of a predetermined message temporal length that indicates an input value to be encoded and transmitting, at the first node, a signal including a pulse train corresponding to the generated message. The signal including the pulse train includes two pulses that define start and end of the message, respectively, and further two pulses that define within the message, a first time interval calculated from the input value in accordance with a first function and a second time interval calculated from the input value in accordance with a second function, respectively.

Abstract: Audio systems in which a primary audio device (28) communicates wirelessly with a second audio device (36) include a latency caused by the communication between the two audio devices. For example, a truly wireless audio device can comprise a first earpiece and a second earpiece. The electronic device (10) that is playing a media file transmits audio data to the first earpiece. The first earpiece then transmits a portion of the audio data to the second earpiece. This communication between the first and second earpiece causes a latency that the system can account for in order to synchronize a video playback with the corresponding audio playback on the wireless headset.

Abstract: Disclosed in the embodiments of the present invention are a security auditing system and a method for same. The security auditing system comprises an eSIM module. The eSIM module is configured to: on the basis of pre-stored auditing rules, perform a security check on each received network connection request; if the security check is passed, determine said network connection request to be a legitimate request and allow the main control terminal that sent the network connection request to perform mobile network connection; and if the security check is not passed, determine the network connection request to be an illegitimate request and prohibit the main control terminal that sent the network connection request from performing mobile network connection.

Abstract: A data handoff controller includes a counter coupled to supply a count value indicative of a skew between a first clock signal and a second clock signal. The first and second clock signal have a fundamental beat frequency. A greatest common factor circuit is used to determine the fundamental beat frequency and the second is reset based on the beat frequency. A sampling circuit samples first clock domain data with the second clock signal. The sampling circuit is controlled to sample, at least in part, based on the count value. The count value can be used to impose a blackout window in which data is not sampled to avoid sampling data around data transitions of the first clock domain data. The count value can also be used to select an edge of the second clock signal to use for sampling the first clock domain data to ensure first clock domain data is not sampled during data transitions.

Abstract: An integrated circuit which adjusts a period for enabling a transmitter, and includes a data delay circuit delaying data to generate transmission data; a transmission/reception terminal; a receiver receiving reception data transferred to the transmission/reception terminal, in response to a reception enable signal; a transmitter transmitting the transmission data to the transmission/reception terminal in response to a transmission enable signal; a shift circuit generating a plurality of preliminary transmission enable signals by sequentially delaying a signal; a phase comparison circuit comparing a phase of each of the plurality of preliminary transmission enable signals and a phase of the transmission data; and a selection circuit selecting one of the plurality of preliminary transmission enable signals as a transmission enable signal according to a phase comparison result of the phase comparison circuit.

Abstract: The invention relates to a method for fast reconfiguration of GM clocks in the TSN network by means of an explicit teardown message. Carrying out a network-wide cleansing of the outdated information ensures that outdated GM information having a higher priority cannot overwrite new information. The current BMCA+ relies on the hold time mechanism in order to quickly carry out the GM reconfiguration on all nodes. The problem is solved by the introduction of a specific advertising schema for the BMCA+ protocol in order to resolve the described instability during the GM reconfiguration period. The method uses an announce+ message for an extra messaging that displays a clock having outdated information and disseminates new information in the complete network. The aim is to inform all clocks that outdated information is present such that the GM reconfiguration can be carried out quickly and without extra conflicts.

Abstract: Provided herein is an implementation of a finite impulse response (FIR) filter that uses a distributed arithmetic architecture. In one or more example, a data sample with multiple bits is processed through a plurality of bit-level multiply and accumulate circuits, wherein each bit of the data sample corresponds to a bit of the data sample. The output of each bit-level multiply and accumulate circuit can then be shifted by an appropriate amount based on the bit placement of the bit of the data sample that corresponds to the bit-level multiply and accumulate circuit. After each output is shifted by the appropriate amount, the outputs can be aggregated to form a final FIR filter result.

Abstract: Various embodiments of the present invention relate to an apparatus and a method for transmitting data between internal modules in an electronic device. Here, a transmission apparatus of a digital interface may comprise: multiple transmission lines connected to a reception apparatus; and multiple transmission circuits connected in parallel to each other and provided for each of the transmission lines, wherein the transmission apparatus may be configured to transmit data having different voltages to the reception apparatus, using at least one transmission circuit among the multiple transmission circuits for each of the transmission lines on the basis of a variation of the voltage of data to be transmitted through each of the transmission lines. Other embodiments are also possible.

Abstract: A processor applies offset values to read and write pointers to a first-in-first-out buffer (FIFO) for data being transferred between clock domains. The pointer offsets are based on a frequency ratio between the clock domains, and reduce latency while ensuring that data is not read by the receiving clock domain from an entry of the FIFO until after the data has been written to the entry, thereby reducing data transfer errors. The processor resets the pointer offset values in response to a change in clock frequency at one or both of the clock domains, allowing the processor to continue to accurately transfer data in response to clock frequency changes.

Abstract: A power system including a first grid and a second grid, each grid having power flow parameters. A breaker installed at a point of common coupling between the first grid and second grid. A first sensor and a second sensor, each located on a side of the point of the common coupling for continually determining the power flow parameters of the first grid and second grid. Wherein the power flow parameters for the first and second grid are indicative of a frequency and a phase. A power source for supplying power to either the first grid or second grid. A controller for synchronizing the frequencies and the phases of the first and second grid, by continually adjusting an amount of power supplied, based on continually determining a frequency mismatch and a phase mismatch between the first grid and second grid, until a first predetermined condition is met.

Abstract: A multiphase serialization system for a voltage-mode transmitter includes a N-to-one stage driven by a N-phase input clock, a phase alignment unit driven by the N-phase input clock being operated to generated interpolated sampling clock signals by adjusting a plurality of reference clock signals provided to the phase alignment unit based on the N-phase input clock, and a preceding multiplexing stage driven by the interpolated sampling clock signals configured to receive incoming data streams and to output phase aligned data streams to the N-to-one stage.

Abstract: A network device receives a packet that conforms to a protocol that i) defines a time stamp field, ii) does not define a dedicated field for time correction information, and iii) defines a plurality of general purpose extension fields. The packet includes (i) a time stamp generated by a source node in the time stamp field, and (ii) a time correction value corresponding to multiple ones of the plurality of intermediate nodes, the time correction value being located in one of the general purpose extension fields. The network device identifies (i) a time specified by the time stamp, and (ii) time correction information specified in the one general purpose extension field, and uses the time correction information and the time specified by the time stamp to synchronize a clock maintained by the network device to a clock maintained by the source node.

Abstract: Various techniques are provided to efficiently implement user designs incorporating clock and/or data recovery circuitry and/or a deserializer in programmable logic devices (PLDs). In one example, a method includes receiving a serial data stream, measuring time periods between signal transitions in a serial data stream using at least one Grey code oscillator, and generating a recovered data signal corresponding to the serial data stream by, at least in part, comparing the measured time periods to one or more calibration time periods. In another example, a system includes a Grey code oscillator configured to increment a Grey code count between signal transitions in a serial data stream, and a Grey code converter configured to convert the Grey code count approximately at the signal transitions to a plurality of binary counts each corresponding to a time period between one or more signal transitions in the serial data stream.

Abstract: An excavation status monitoring system for a tunneling machine that includes a detecting portion mounted on a cutter head of the tunneling machine, including an accelerometer that detects a vibration or an acoustic sensor that detects a sound wave and a sound output portion that outputs a signal detected by the detecting portion as sound.

Abstract: Disclosed are a method and a device for recovering clock data of a tributary signal in SDH, wherein the method includes that: it is to extract valid data of the signal from a time slot of each tributary in a synchronous digital hierarchy SDH frame, and store into a storage space corresponding to a time slot of each tributary in a cache; it is to recover a clock signal and a readout signal for the time slot of each tributary by means of time division multiplexing; when the readout signal for the time slot of any tributary is valid, it is to read out contents of the data from the storage space corresponding to the time slot of the tributary in the cache, and latch into a latch corresponding to the time slot; the device includes: a data extracting module, a clock recovery circuit and a data recovery module.

Abstract: Aspects of the present disclosure provide a number of approaches to deploy out-of-standard (or proprietary) features/enhancements that are not supported in the current communication standards. A mobile terminal and a network can mutually agree to support certain out-of-standard features/enhancements, and communicate support of such out-of-standard or non-standard features/enhancements by adapting or repurposing currently unused (or reserved) signaling data.

Abstract: Methods and systems for inter-destination synchronization in first and second receivers for content parts associated with a play-out timeline are disclosed. First timing information comprising first content part identifiers and associated first clock times may be determined, where the first receiver may receive a first content part identifier comprising first fingerprints for identifying a first content part in a first media stream. Second timing information comprising second content part identifiers and associated second clock times may be determined, where the second receiver may receive a second content part identifier identifying a second content part in a second media stream based on the first and second timing information. A timing difference in processing a content part in the first and second media streams may be calculated. Based on the timing difference, synchronization information for inter destination synchronization between said first and second streams may be generated.

Abstract: A method for transmitting measurement data includes receiving measurement data in a first communication module, time stamping the measurement data in the first module with a time tag, transmitting the measurement data to a second communication module via a packet switched data network, and outputting the transmitted measurement data after a predefined delay time ?tD after the time stamping of the measurement data.

Abstract: Selecting a network connection for data communications with a networked device, including: identifying a plurality of networks available for data communications with the networked device, each network having network connection attributes; and selecting one of the plurality of networks in dependence upon the network connection attributes and the direction of data transfer.

Abstract: Aspects of a method and system for a distinct physical pattern on an active channel to indicate a data rate transition for energy efficient Ethernet. In this regard, one or more distinct physical patterns may be transmitted on one or more active channels of a network link during an inter-packet gap to control a data rate on the link. The unique physical pattern may be transmitted instead of or in addition to one or more IDLE symbols. The distinct physical pattern may communicate a data rate to be utilized on the link and/or indicate when a data rate transition should occur on the link. The distinct pattern may be transmitted and/or the data rate transition may occur during a specified inter-packet gap or during a specified packet boundary. The distinct physical pattern may comprise one or more control characters and/or an ordered set of voltage levels, symbols, and/or characters.

Abstract: Systems and methods for operating cameras are described. An image signal received from an image sensor can be processed as a plurality of video signals representative of the image signal. An encoder may combine baseband and digital video signals in an output signal for transmission over a cable. The video signals may include substantially isochronous baseband and digital video signals. The baseband video signal can comprise a standard definition analog video signal and the digital video signal may be frequency modulated before combining with the baseband video signal and/or transmitting wirelessly. The digital video signal may be a compressed high definition digital video signal. A decoder demodulates an upstream signal to obtain a control signal for controlling the position and orientation of the camera and content of the baseband and digital video signals.

Abstract: First, a packet may be received and a timestamp value may be placed on the packet. The timestamp value may comprise a place time value comprising a time when the timestamp was placed on the packet plus a delay time value comprising an estimated time delay between when the timestamp was placed on the packet and when the packet leaves a port exit. Next, the packet may be sent to a first in first out (FIFO) memory. The packet may then be sent from the FIFO memory out the port exit.

Abstract: Methods, transmitter, receiver and computer program product for transmitting or receiving data of a real-time communication event, the data being transmitted from the transmitter to a jitter buffer of the receiver. At least one processing parameter describing how data is to be processed for transmission from the transmitter to the jitter buffer in the real-time communication event is determined at the transmitter. Data is processed for transmission from the transmitter to the jitter buffer in accordance with the determined at least one processing parameter. Control information based on the determined at least one processing parameter is transmitted from the transmitter to the receiver, wherein the control information is for use by the receiver to control a state of the jitter buffer. The processed data is transmitted from the transmitter to the jitter buffer of the receiver in the real-time communication event.

Abstract: A time-to-digital conversion circuit for converting a time difference between two input signals to a 1-bit digital value, and adjusting the time difference between the two input signals to generate two output signals includes: a phase comparator configured to compare phases of the two input signals with each other to generate the digital value; a phase selector configured to output one of the two input signals which has a leading phase as a first signal, and the other of the two input signals which has a lagging phase as a second signal; and a delay unit configured to output the first signal with a delay, wherein the time-to-digital conversion circuit outputs the signal output from the delay unit and the second signal as the two output signals.

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. A configurable clock tree includes a delay matrix that may be configured such that each the timing of clocks for each of a plurality of data lanes can be optimized for minimum skew. Selections between different versions of a base clock signal and different paths available to the selected version may provide a root clock used for transmitting data on a communications link. The versions of the one or more clock signals may include three versions of a first clock signal. Each version of the first clock signal may be subject to a different delay with respect to the clock signal.

Abstract: In a telecommunications network including at least a user device and a network node separated by at least a packet-switched part of the telecommunications network, the user device including a primary jitter buffer having a constant packet play-out rate, the network node including a secondary jitter buffer, incoming packets destined for the user device are received and passed through the secondary jitter buffer of the network node downstream towards the primary jitter buffer of the user device. The departure times of packets passing through the secondary jitter buffer of the network node downstream towards the primary jitter buffer of the user device are monitored. On the basis of the monitoring and one or more known characteristics of the primary jitter buffer, an estimate of a current state of the primary jitter buffer is maintained. Operation of the secondary jitter buffer is dynamically controlled according to the maintained estimate.

Abstract: A master device and slave devices are connected with each other through an SDA and an SCL, and at least one of a serial communication data signal communicated through the SDA and a serial communication clock signal communicated through the SCL is latched with use of a noise removal clock signal whose frequency is higher than that of the serial communication clock signal, and is taken in.

Abstract: Method, transmitter and computer program product for transmitting data of a real-time communication event from the transmitter to a jitter buffer of a receiver. The method comprises jointly determining (i) at least one processing parameter describing how data is to be processed for transmission from the transmitter to the jitter buffer, and (ii) jitter buffer control information for indicating to the receiver how to control a state of the jitter buffer. The jitter buffer control information is transmitted to the receiver. Data is processed for transmission from the transmitter to the jitter buffer in accordance with the determined at least one processing parameter. The processed data is transmitted from the transmitter to the jitter buffer of the receiver.

Abstract: Methods, transmitter, receiver and computer program product for transmitting or receiving data of a real-time communication event, the data being transmitted from the transmitter to a jitter buffer of the receiver. At least one processing parameter describing how data is to be processed for transmission from the transmitter to the jitter buffer in the real-time communication event is determined at the transmitter. Data is processed for transmission from the transmitter to the jitter buffer in accordance with the determined at least one processing parameter. Control information based on the determined at least one processing parameter is transmitted from the transmitter to the receiver, wherein the control information is for use by the receiver to control a state of the jitter buffer. The processed data is transmitted from the transmitter to the jitter buffer of the receiver in the real-time communication event.

Abstract: A digital broadcasting system and a method of processing data are disclosed. Herein, additional encoding is performed on mobile service data, which are then transmitted, thereby providing robustness in the processed mobile service data, so that the mobile service data can respond more strongly against fast and frequent channel changes. In a transmitting system including a service multiplexer and a transmitter located in a remote site, a method of processing data of the transmitting system includes comparing an output data rate of the service multiplexer and a transmission data rate of the transmitter, when a difference occurs between the two data rates, adjusting a burst size, wherein the burst transmits mobile service data, and encoding the mobile service data, and referring to the burst size so as to multiplex main service data and the encoded mobile service data in a burst structure.

Abstract: In calibration mode, a clock signal and a data signal are respectively transmitted via a clock lane and a data lane of an MIPI. A test clock signal is provided by adjusting the phase of the clock signal, and a test data signal is provided by adjusting the phase of the data signal. By latching the test data signal according to the test clock signal, a latched data may be acquired for determining an optimized phase relationship corresponding to the clock lane and the data lane. When transmitting the clock signal and the data signal in normal mode, the signal delays of the clock lane and the data lane may be adjusted according to the optimized phase relationship.

Abstract: This invention relates to methods and devices for clock synchronization. The invention makes particular use of IEEE 1588 with offset and skew correction. In embodiments of the invention, the IEEE 1588 Precision Time Protocol is used to exchange time stamps between a time server and a client from which the client can estimate the clock offset and skew. In embodiments of the invention a free running clock at the client is provided with an estimation technique based on the time stamps from the IEEE 1588 PTP message exchange between the server and client clocks. The offset and skew from the estimation process can be combined with the local free running clock to give a synchronized local clock which is an accurate image of the master clock.

Abstract: Method, transmitter and computer program product for transmitting data of a real-time communication event from the transmitter to a jitter buffer of a receiver. Jitter buffer state information is received at the transmitter from the receiver, the jitter buffer state information indicating a state of the jitter buffer. At least one processing parameter is controlled based on the received jitter buffer state information, the at least one processing parameter describing how data is to be processed for transmission from the transmitter to the jitter buffer in the real-time communication event. Data is processed for transmission from the transmitter to the jitter buffer in accordance with the determined at least one processing parameter. The processed data is transmitted from the transmitter to the jitter buffer of the receiver in the real-time communication event.

Abstract: A method of accelerated carrier signal acquisition for a digital communication receiver, the method comprising receiving a carrier signal by a receiver comprising a carrier recovery loop (CRL), setting the CRL to an open loop setting using a processor, setting a numerically controlled oscillator (NCO) within the CRL at a center frequency of the NCO, determining, by the processor, one or more initial parameters of the CRL, calculating an estimate and polarity for a sign frequency detection frequency using a sign frequency detector while simultaneously estimating a Fast Fourier Transform (FFT) frequency by running an FFT using the processor, comparing polarities of the estimates of the sign frequency detection frequency and FFT frequency and determining a frequency offset using the processor, and adjusting one or more parameters of the CRL based on the frequency offset using the processor.

Abstract: The proposed invention is about an improved method for serial-in and serial-out transceiver applications. The proposed system includes a dual loop phase locked loop (PLL) architecture having a PLL and a phase rotator (PR)-based delay locked loop (DLL). An advantage of this architecture is that a single PLL offers decoupled bandwidths; a wide jitter-tolerance (JTOL) bandwidth for receiving data and a narrow jitter transfer (JTRAN) bandwidth for the data transmission. Thus, the amount of jitter at the output can be substantially reduced relative to the input while offering sufficient jitter tracking bandwidth. Also, this architecture is suitable for low-power applications since a phase shifter in the data path, which is one of the most power-hungry blocks in conventional DPLL designs, is not required.

Abstract: Methods and systems for synchronizing a first and second media stream are describe, wherein said first and second media stream are being transmitted by at least one media source in a network via a first and second media path to one or more terminals. The method comprises: measuring timing information associated with arrival times of media packets in said first and second media stream using a measuring module positioned at a first location in said first and second media paths; in said network generating buffer instructions for at least one buffer on the basis of said timing information, said buffer being positioned at a second location in at least one of said first or second media path; and, delaying one or more media packets transmitted over said media path to said one or more terminals such that arrival times of media packets at said one or more terminals are substantially synchronized.

Abstract: A special rendering mode for the first few seconds of play out of multimedia data minimizes the delay caused by pre-buffering of data packets in multimedia streaming applications. Instead of pre-buffering all incoming data packets until a certain threshold is reached, the streaming application starts playing out some of the data packets immediately after the arrival of the first data packet. Immediate play out of the first data packet, for example, results in minimum delay between channel selection and perception, thereby allowing a user to quickly scan through all available channels to quickly get a notion of the content. The immediate play out is done at a reduced speed.

Abstract: A system and method are described to provide a next generation cable gateway/modem based on the DOCSIS standard with a scheme to synchronously combine channels in the physical layer to increase overall bit rates for coaxial cable data transmission. The systems and methods synchronize the counters associated with multiple channels, including continuity counters, at the transmitter to zero and then allow the counters on individual channels to increment individually. At the receiver, individual channel delays of individual channels will be thus recognizable based on the information provided by the counters associated with each channel. A buffer at the receiver is informed and used to individually delay one or more of the multiple channels to marry up continuity counter values. In this manner, the buffer acts to essentially equalize delays in individual channels with the continuity counter representing the mechanism for specifying the individual delays for the separate channels.

Abstract: One embodiment provides a data-receiving device component comprising a phase shifter, timer logic, and control logic. The phase shifter is configured to release a train of clock pulses with a controlled phase shift. The timer logic is configured to receive data from a data-sending device, and for each transition of the data received, to determine whether a clock pulse from the train is early or late with respect to the transition, and to tally the late clock pulses relative to the early clock pulses. The control logic, operatively coupled to the phase shifter and to the timer logic, is configured to incrementally advance the phase shift when the late clock pulses outnumber the early clock pulses by a non-integer power of two.

Abstract: To test the timing-recovery process of a receiving (i.e., slave) node in a packet-based network, a packet filter is configured in a test configuration that already contributes a natural delay distribution to the packet flow arriving at the slave node. The resulting delay distribution of the arriving packet flow is the combination of that natural delay distribution and the effects of the packet filter, which deterministically or statistically reduces the number of packets with delays within the anchor value window arriving at the slave node (i.e., received packets having packet delays within the slave node's anchor value window). The packet filter can be adjusted to test the slave node's timing-recovery process for a wide variety of packet-flow conditions (e.g., different rates of packets with delays within the anchor value window).

Abstract: Methods, systems, and apparatuses are described for aligning lanes of low speed serial links coupled to a transceiver. The transceiver cooperatively performs lane alignment operations with a low speed device during initialization of the transceiver and the low speed device. The lane alignment operations are performed in-band using the low speed serial links, and therefore, do not require additional out-of-band-signaling wires between the transceiver and the low speed device to perform the lane alignment operations. The lane alignment operations may be performed by a handshaking process performed by the transceiver and the low speed device, where the transceiver and the low speed device provide training pattern(s) of data that are used to align the low speed serial links. The low speed serial links are continuously monitored after initialization is complete to detect various transient impairments and to re-initiate lane alignment operations in response to detecting such impairments.

Abstract: The present invention provides a method for range extension is wireless communication systems. One embodiment of the method includes determining whether a mobile unit is within a first range corresponding to a range of timing advances supported by a timing advance command. This embodiment also includes transmitting a plurality of timing advance commands to the mobile unit when the mobile unit is outside the first range so that the mobile unit can synchronize with the base station by combining information in the plurality of timing advance commands.

Abstract: The invention concerns a device for transmitting packets in a packet communication network comprising at least two stations, characterized in that it includes means for: extract image cues from a synchronizing signal, initializing a first counter based on said image cues, initializing a second counter every “m” zero crossing of the first counter, sampling the second counter at all the Tech periods, where Tech is derived from a time base synchronized on all the network stations, and transmitting packets containing the samples in the network. The invention also concerns a device for receiving packets in a packet communication network comprising at least two stations.

Abstract: An apparatus for coarse phase alignment of an analog signal comprising: a tapped delay line, a coarse phase alignment logic circuit coupled to the tapped delay line, and a selector coupled to the tapped delay and the coarse phase alignment logic circuit. An apparatus for timing and data recovery for burst mode receivers comprising: a receiver, a coarse phase alignment circuit coupled to the receiver, at least one analog to digital converter (ADC) coupled to the coarse phase alignment circuit such that the coarse phase alignment circuit is positioned between the receiver and the ADC, and a fine phase alignment circuit coupled to the ADC such that the ADC is positioned between the coarse phase alignment circuit and the fine phase alignment circuit, wherein the fine phase alignment circuit produces a recovered data output.

Abstract: A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The memory controller can perform maintenance operations to update the phase relationship between the phase-providing and data-sampling signals.

Abstract: A system improves bandwidth used by a data stream. The system receives data from the data stream and partitions the data into bursts. At least one of the bursts includes one or more idles. The system selectively removes the idles from the at least one burst and transmits the bursts, including the at least one burst.