Abstract: A first aspect of the invention provides a system for prioritising faults in a transport network comprising network elements arranged to transport data signals comprising respective overhead data and payload data. The system comprises one or more first network elements arranged to include in said overhead data a priority indicator indicating the relative importance of the respective payload data. The system further includes one or more second network elements arranged to examine the respective priority indicator of data signals in respect of which a fault is detected. Detected faults are prioritised using the respective value of the priority indicator and hence on the relative importance of the information carried by the faulty signal.

Abstract: A method for interlinking regulation and/or control functions for a motor vehicle, the communication structure of the control or regulation functions is defined by way of graphs containing nodes and directed gridlines, the nodes of the graph representing control or regulation functions and its directed gridlines representing defined communication paths of the control or regulation functions.

Abstract: A processor is programmed to reduce a problem of adding a new connection to a time-space-time (TST) switch of a communication network into a problem of graph theory, and to solve the problem using a heuristic instead of an exact algorithm. A solution, if provided by the heuristic, is used to rearrange the connections in the TST switch. Several embodiments of such a programmed processor reduce a connection rearrangement problem of a TST switch into any one of the NP-complete problems (such as the vertex coloring problem or the boolean satisfiability (SAT) problem). In some such embodiments, the processor is programmed based on the Brélaz heuristic to find a solution to the vertex coloring problem. In other embodiments, other heuristics, such as a genetic algorithm, may be used.

Abstract: A communication apparatus that, in sending and receiving data between a LAN and a certain network, dynamically sets the capacity of a line used for sending and receiving data via the network based on the amount of use of a line used for sending and receiving data via the LAN, and a method for setting the line capacity thereof are disclosed.

Abstract: A subscriber platform for broadband communication, according to various aspects of the present invention, includes an antenna, a plurality of transceivers, and a processor. The antenna supports communication via a plurality of directional beams. The plurality of frequency agile transceivers operate simultaneously, each transceiver being coupled to the antenna for communication via a respective directional beam. The processor is coupled to the plurality of transceivers. And, the transceivers are coupled to the antenna to communicate data among the directional beams as directed by the processor, communication including directional diversity and frequency diversity.

Abstract: Systems and methods, consistent with the present invention, provide a high-speed line interface for networking devices. Such an interface may be used in networking devices, such as routers and switches, for receiving data from, and transmitting data to, high-speed links, such as those lines carrying data at rates of 2.5 Gbit/sec, 10 Gbit/sec, and 40 Gbit/sec and more. In a preferred embodiment, the interface deserializes data from an incoming data stream onto a multi-line bus so that the data may be processed at a lower clock speed. Packets are extracted from the data on the multi-line bus and distributed among a plurality of switching/forwarding modules for processing.

Abstract: A telecommunications node architecture is disclosed that facilitates the loop-back of a signal in an add/drop multiplexor (e.g., a SONET/SDH node, a dense wavelength division multiplexed node, etc.) that uses automatic protection switching.

Abstract: A SONET/SDH architecture is disclosed that enables the multiplexing of STS-1's from different SONET/SDH rings into a single STS-N for transmission via a single optical fiber, but while maintaining the association of each of the STS-1's with its respective SONET/SDH ring. For example, when an STS-48 carries 12 STS-1's from a first SONET/SDH ring and 12 STS-1's from a second SONET/SDH ring, the STS-48 carries: the automatic protection switching channel for the 12 STS-1's from the first SONET/SDH ring (with addresses specified in the address space of the first SONET/SDH ring); and the automatic protection switching channel for the 12 STS-1's from the second SONET/SDH ring (with addresses specified in the address space of the second SONET/SDH ring).

Abstract: A scalable multi-service node system uses a stackplane architecture which allows the transport capacity to be flexibly expanded while providing first traffic mode and second traffic mode link channels. The primary channel bank is provided, and one or more secondary channel banks are connected to the primary channel bank through the stackplane first traffic mode and second traffic mode links. The system is expandable by adding secondary channel banks to the system through the stackplane links.

Abstract: A composite add/drop multiplexor architecture is disclosed that facilitates the loop-back of a signal in a composite add/drop multiplexor (e.g., a SONET/SDH node, a dense wavelength division multiplexed node, etc.) that uses automatic protection switching.

Abstract: An apparatus comprising a distributed multiplexer configured to receive a distributed input group of signals. The distributed multiplexer may be configured to evenly load the distributed input groups.

Abstract: A multi-stage switching network that can hitlessly reconfigure itself comprising a controller that controls each stage separately. The controller designates the paths through each stage according to the set of paths currently active. If the set of paths changes, the controller sends a new set of paths to the first stage while using the old set of paths for the second stage during a first frame. On the next frame, the controller causes both stages to use the new set of paths.

Abstract: A serializer/deserializer pair with a discretionary loop-back mechanism is disclosed that enables a redundant high-bandwidth node architecture that benefits from the clever re-use of two identical integrated circuits. The first is an add/drop multiplexor and the second comprises the serializer/deserializer pair with discretionary loop-back. The illustrative embodiment comprises: a first serializer that serializes a first series of r-bit words to generate a first series of s-bit words; a first deserializer that deserializes a second series of s-bit words to generate a second series of r-bit words; and a multiplexor for selecting a third series of r-bit words from the first series of r-bit words and the second series of r-bit words; wherein r and s are both positive integers and r?s.

Abstract: A technique for disguising ATM cells as ATM cell-containing packets within a routing facility to permit the packet-only switch to also handle switching of the ATM cells. The technique has wide applications within the backbone infrastructure, Wide Area Networks, Metro Area Networks, Local Area Networks, and particularly within a routing facility to handle high speed traffic. The technique can receive both ATM cells and packets for switching via a single channel or optical fiber or receive ATM cells and packets via two separate channels or two separate fibers. The ability to handle both ATM cell and packet switching allows packet-only routers to handle ATM traffic, thereby reducing the cost of the switching infrastructure for network operators.

Abstract: An alarm collection and routing method using a multi-stage clock distribution scheme in a signaling server organized into a plurality of uniquely addressable shelves. The signaling server includes a system timing generator, one or more clock distribution modules arranged in a nested hierarchical manner, and a plurality of bus control modules, wherein each bus control module interfaces with at least a portion of line cards disposed in a shelf. The system timing generator provides a framed serial control signal, SFI, for controlling the operation of the multi-stage clock distribution scheme, which encodes the IDs of the clock distribution modules and bus control modules. Each bus control module generates a Status signal, encoding it with alarm data and line card status information. The Status signals from the bus control modules are received by the clock distribution modules connected thereto and are multiplexed into a serial TDM bitstream (EAS signal) by each clock distribution module based on its ID.

Abstract: A method and system for processing communication at a node in a communication system makes use a series of fixed-length data frames in which multiple data streams are multiplexed. Each of the data streams originates from a corresponding source of data in the communication system, and least two of the data streams originate from a same source of data. For each of the series of fixed-length frames that are processed at a node, multiple offsets within the fixed-length frame are identified, each of these offsets being associated with a different one of the sources of data. The data streams which are multiplexed in the series of fixed-length frames are then processed. For each of the data streams, in each of the series of fixed-length frames, that data stream is processed according to the offset identified for that frame that is associated with the source of that data stream.

Abstract: In a method of communicating a plurality of parallel data packets from a first data parallel bus to a second parallel data bus, each of the plurality of parallel data packets is separated into a first portion and a second portion. Each first portion is converted into a first serial data stream and each second portion is converted into a second serial data stream. The first serial data stream is transmitted over a first serial data channel and the second serial data stream is transmitted over a second serial data channel. The first serial data stream is converted into a plurality of first received portions and the second serial data stream is converted into a plurality of second received portions. Selected first received portions are combined with corresponding selected second received portions so as to regenerate the plurality of parallel data packets.

Abstract: A synchronous optical network (SONET) framer includes a frame dimension unit and a programming interface. The frame dimension unit can be programmed with a frame dimension through the programming interface. The SONET framer converts a data stream to and/or from a frame format based on the frame dimension programmed into the frame dimension unit. For instance, in various embodiments, a SONET framer can be programmed to support a variety of SONET frame sizes and to provide a number of testing and design advantages.

Abstract: A system and method are provided for transporting backward information in a digital wrapper format network of connected simplex devices. The system comprises a first simplex processor receiving downstream messages with overhead bytes. The first simplex processor selectively replaces overhead bytes with calculated overhead bytes and supplies the calculated overhead bytes. The system further comprises a buffer receiving the calculated overhead bytes from the first simplex processor and supplying the calculated overhead bytes. A second simplex processor accepts the calculated overhead bytes from the buffer and supplies an upstream message including the calculated overhead bytes. The first simplex processor receives messages in a frame format with an overhead section, drops the overhead section, and selectively reads backward message monitor bytes in the dropped overhead section to determine if upstream communication nodes are receiving transmitted messages.

Abstract: A scalable digital loop carrier system uses a stackplane architecture which allows the transport capacity of the scalable digital loop carrier system to be flexibly expanded while providing time division multiplex (TDM) and asynchronous transfer mode (ATM) data link channels. The primary channel bank is provided in the scalable digital loop carrier system, and one or more secondary channel banks are connected to the primary channel bank through the stackplane ATM and TDM data links. The scalable digital loop carrier system is expandable by adding secondary channel banks to the system through the stackplane TDM and ATM data links.

Abstract: A bound mode mechanism and technique efficiently accommodates high-bandwidth data traffic flow within an intermediate node of a computer network. The bound mode mechanism combines two half-slot line card connectors of a backplane in an aggregation router into a single full-slot line card arrangement to thereby increase the bandwidth provided to a high-speed, full-height line card of the router. The technique is also capable of accommodating generic half-slot (i.e., subslot) connectors, each of which is capable of supporting a variety of data formats. The bound mode mechanism further allows use of a high-speed trunk card without the penalty of supporting high trunk level bandwidth on all of the slot connectors of the router. The mechanism enables use of a simple backplane, while also maintaining a low pin count on a backplane logic circuit of the router.

Abstract: Disclosed is a serial data mapping apparatus and method for mapping DS serial data into VC parallel data which includes an STM-1 address generating unit for generating a mapping address; a VC mapping unit for mapping a DS asynchronous signal into a VC signal as byte unit, according to the mapping address; and an STM-1 formatting unit for pointer processing and multiplexing a virtual container of the mapped VC signal and generating an STM-1 signal.

Abstract: A SONET multiplexed system architecture that permits greater levels of integration. The architecture includes a time slot interchanger for routing information from at least one SONET input signal path associated with a respective first time slot to at least one SONET output signal path associated with a respective second time slot. Each input signal path includes a pointer interpreter, and each output signal path includes a FIFO buffer serially coupled to a pointer generator. The architecture further includes a synchronization buffer in each input signal path for transferring the input signal to the clock rate of the time slot interchanger. The architecture permits greater levels of integration when the time slot interchanger has more inputs than outputs, and/or the time slot interchanger provides the output signal to a pointer processor to transfer the output signal to the clock rate of the output signal path.

Abstract: A device, system and method for aligning data received on a plurality of data lanes in a data link are disclosed. One or more alignment vectors are generated for each of a plurality of data lanes where each alignment vector represents a location of an alignment character in an associated one of the data lanes. For each data lane, a plurality of alignment vectors may be associated with one or more alignment windows associated with the data lane. If the alignment vectors of the data lanes are associated with a common alignment window, an alignment position may be selected for each data lane.

Abstract: A method and system for transporting SONET signals over an optical telecommunications network, the method including generating a ComBus signal, including payload data, J1/C1 and synchronous payload envelope (SPE), per SONET path, Smart extracting of data from the ComBus signal (J1 detection and N/P detection), gathering the payload data and J1 into short packets, adding a packet header to each short packet, transporting the short packets to a destination, and generating C1 and SPE at the destination so as to reconstruct the SONET signals out of the ComBus signal.

Abstract: Disclosed is an apparatus for establishing a path in a synchronous digital hierarchy (SDH) system and method thereof. The present invention monitors all possible locations for the existence of the C2 byte of the VC-n (n=3,4) signal and a size bit (SS bit) of the TU-m (m=11,12,2,3) signal, thereby enabling it to decide the pointer interpretation and generation path automatically.

Abstract: Variable bit rate information is transmitted across a transmission link (20) at a constant bit rate by multiplexing individual variable bit rate elementary data streams (161 and 162) into a composite data stream (18) having a constant bit rate. A receiving device (22) receives the constant bit rate stream but delays processing thereof by an interval typically a fraction of the transmission interval. Following the delay interval, the receiving device processes the data at a rate that is independent of, but typically not greater than, the constant bit rate.

Abstract: A plurality of transmission circuits transmit data over one or more output lines. A plurality of receiving circuits receive data over one or more of a set of input lines A plurality of parallel-serial conversion circuits coupled to the plurality of transmission circuits and to the plurality of receiving circuits, the plurality of conversion circuits to convert parallel signals to one or more sets of serial signals and to send the converted serial signals to one or more corresponding transmission circuits, and to receive one or more sets of serial signals from one or more of the receiving circuits and to convert the serial signals to parallel signals.

Abstract: A pointer processing apparatus in an SDH transmission system used to serially conducting a pointer process on inputted multiplex data has an address generating unit for allocating an address to each channel of the multiplex data, a RAM for holding an information group obtained by a pointer extracting process and a pointer process, and RAM controlling unit for controlling a sequence of an operation to write-in/read-out the RAM to serially conduct the pointer process on the received multiplex data, thereby largely decreasing the circuit scale, the power consumption, the number of distributions and the like. A POH terminating operation process is conducted in a POH terminating operation process unit, and an obtained result of the POH terminating operation is stored in a storage area for a corresponding channel of a storage unit, whereby the POH terminating operation process can be conducted without separating a multiplex signal into channels.

Abstract: A communication node contains intelligence for directing both internet protocol (IP) packets and Asynchronous Transfer Mode (ATM) cells toward their destinations. The ATM cells and IP packets may be received within a common data stream. The respective devices process the ATM cells and IP packets to direct the cells and packets to the proper output ports towards their destinations. The device is capable of performing policing and quality of service (QOS) processing on both the ATM cells and the IP packets.

Abstract: The SONET/SDH multiplexing hierarchy is extended to very high rates by creating new virtual containers of a higher capacity, and their associate pointers. The multiplexing hierarchy nests the pointers into the payload, so that the number of pointers on the high capacity line is importantly reduced, as the high rate spans of the network do not see the STS-1/STM-1 pointer granularity. Fewer pointers result in reducing the current complexity of pointer processing. The complexity of the multiplexing hierarchy is also reduced by the use of larger containers. The hierarchy may be extended to higher rates, as needed, and may also be used for other technologies, besides SONET/SDH.

Abstract: For TV broadcasting purposes encoding systems with related video encoders and audio encoders are used. The audio and video delay are aligned before multiplexing and transmitting the audio and video streams. According to a time stamping mechanism input time stamps are generated which become linked with data to be encoded, and are replaced before output by output time stamps, which are derived from the input time stamps by using a data delay constant. The input time stamps are used to control the delay of the encoding process and the output time stamps are indicating the output time. In order to allow a switchable out-put delay the data delay constant can be changed. Already assigned output time stamps remained unchanged. For data for which output time stamps are not already assigned, the out-put time stamps are calculated using the new delay constant.

Abstract: A device for individually processing a plurality of data transmission channels, wherein data for each channel is contained at a predetermined position in a serially received frame, includes means for determining the position in the frame of currently received data of the frame; a channel memory providing a channel number in response to the position of the currently received data; and a plurality of FIFOs respectively associated to the channels, wherein each FIFO is responsive to a respective channel number provided by the channel memory for storing the currently received data.

Abstract: The present invention discloses novel network architectures for evolving traditional service provider networks. The network architecture of the invention has a transport layer including an optical network. At least one node of the network architecture includes a large packet switch that is coupled to the transport layer and to an access layer. The large packet switch aggregates a plurality of services from the access layer. The large packet switch also performs packet level grooming of the information from the services prior to transport of the information via the transport layer. The optical network performs restoration for the network architecture. In one embodiment, the optical network is an optical ring network including at least one optical switch and restoration is performed at the layer-0 (optical layer).

Abstract: A digital signal multiplexing device packetizes one or more bitstreams of digital signals to form packets and multiplexes the respective bitstreams on the packet basis to produce plural degree-one multiplexed streams which are received. The digital signal multiplexing device also sets the sequence of time-divisional multiplexing of the packets as interleaving patterns repeated at a pre-set period. The digital signal multiplexing device time-divisionally multiplexes the degree-one multiplexed streams on the packet basis to generate a degree-two multiplexed stream.

Abstract: An ATM (asynchronous transfer mode) cell transfer apparatus includes an input interface, a switch block, and an OAM cell processing hardware block having a memory unit. The input interface receives an SDH/SONET signal on each of a plurality of first transfer paths to output an input OAM cell corresponding to the SDH/SONET signal to one of a plurality of input ports of the switch block corresponding to the first transfer path for the SDH/SONET signal to be transferred. The switch block receives the input OAM (operation and maintenance) cell from the corresponding input port as an OAM input port to output to the OAM cell processing hardware block together with a port number of the OAM input port, and receives at least one output OAM cell from the OAM cell processing hardware block to output to at least one of the plurality of output ports based on the received output OAM cell.

Abstract: A system and method for automatically generating a protection route as an alternative to a working route through a network of switches prior to network failure. A switch selects the proposed protection route so that the protection route is disjoint from the working route. Next, a switch or switches determines whether bandwidth is available for the proposed protection route. If so, the protection route is set-up for activation when needed.

Abstract: Methods, apparatuses, media and signals for providing clear channel access on a network are disclosed. A first method involves receiving a communication signal from a remote network element. The communication signal includes a previous transport overhead (PTOH) portion indicative of transport overhead contents of the communication signal prior to arrival at the remote network element, and a previous path error (PPE) portion indicative of path errors present in the communication signal at the remote network element. The method then involves modifying a transport overhead portion of the communication signal in response to the PTOH and PPE portions.

Abstract: A method is described for transmitting/receiving STM-4 (SDH) or STS-12 (SONET) digital signals over two RF carriers in a radio regenerator section. The method provides for performing, in transmission, a de-interleaving operation of the standard frame to be transmitted in such a way as to subdivide it by columns into two sub-frames. The RSOH bytes of the standard frame are terminated and transmitted over the two working channels or over one service channel and one working channel so as to be protected in a 1+1 configuration: In reception, a column interleaving operation recombines together the two sub-frames and recovers and correctly rearranges the RSOH bytes so terminated as to obtain the standard frame originally received from the transmitter. The generated sub-frames are synchronized with the standard frame.

Abstract: A high speed, fiber optics communications network provides network connectivity throughout a multi-tenant building or facility and is integrated with other building systems. Network management and maintenance are automated and centralized in a network manager. Network bandwidth needs of the building are aggregated and delivered to building tenants as needed. Wireless LAN access points are coupled to the network to provide wireless network access throughout the building.

Abstract: A read port for selectively coupling one of a plurality of inputs to an output is disclosed. The read port comprises: a plurality of inputs; an output; a plurality of multiplexers operable to selectively couple a selected input to said output; and a multiplexer control signal input for inputting a multiplexer control signal, the multiplexer control signal comprising a plurality of control parameters and being operable to control switching of the plurality of multiplexers. The plurality of multiplexers are arranged in a plurality of layers, the layers being arranged between the inputs and output, such that a selected input is operable to be coupled to the output via a multiplexer from each of the different layers.

Abstract: Synchronous Optical NETwork (SONET) traffic is sent across a packet network. A SONET transmission is decoded into a data structure. The data structure is then converted into one or more packets and sent across the packet network.

Abstract: A system and method for autonomous data path verification in a multi-module shelf configuration, such as in a digital cross-connect system, are disclosed. The system generally includes a source port module, a destination module, and optional n-stage network of mapping interface modules. The source port module is configured to reuse transport overhead bytes of received SONET or SDH signals by inserting data path verification data therefor. The destination module is configured to perform autonomous data path verification between the source port module and the destination module by examining the reused transport overhead bytes of the signals received from the source port module. The method generally includes reusing transport overhead bytes by inserting data path verification data into the overhead bytes of signals received by a first module, e.g., a source port module, and transmitting the signals with the data path verification data toward a second module, e.g., a destination port module.

Abstract: Disclosed is a CDMA base station transmission device having: a first spread multiplex synthesis unit that spreads and multiplexes transmit data of a predetermined number of users to be selected from a plurality of users; and a second spread multiplex synthesis unit that is additionally provided when the number of users increases. The first spread multiplex synthesis unit is provided with a first multiplex synthesis part inside the unit, and the first multiplex synthesis part adds the spread-multiplexed data of the first spread multiplex synthesis unit and the spread-multiplexed data of the second spread multiplex synthesis unit, D/A-converts the added spread-multiplexed data, modulates it into radio frequency band, transmits it through the antenna.

Abstract: The present invention provides a method and apparatus for establishing dedicated local area network (LAN) connectivity between network elements (NEs) in an optical transmission network without using any of the payload transport capacity available. In order to provision dedicated LAN connections between NEs, the invention reallocates existing overhead functionality to provide dedicated bandwidth for LAN communications between NEs. At each NE, a respective LAN interface unit provides access to this dedicated bandwidth and allows LAN devices such as personal computers (PCs), servers and monitoring equipment to communicate across NEs of an optical transmission network without consuming any payload transport capacity available therein.

Abstract: A switching algorithm, a signaling protocol, and a switching decision method having improved optical network switching features is described. In one embodiment, a local node, during a switch from the service channel to the protection channel, propagates a switching signal to a remote node before the local node has finished switching from the service channel to the protection channel. The remote node, in response to the received switching signal, begins switching from the service channel to the protection channel and transmits a signal back to the local node before the remote node has finished switching from the service channel to the protection channel.

Abstract: Circuitry for a node of an optical communication network has a mux and/or a demux. In one embodiment, the circuitry has a mux and a demux implemented on a single circuit board, where (1) the mux is configured to combine up to eight different incoming OC3/OC12-rate electrical signals into a single outgoing OC48-rate electrical signal for conversion into two copies of an outgoing OC48 optical signal and (2) the demux is configured to split a working incoming OC48-rate electrical signal (selected from two incoming OC48-rate electrical signals converted from two incoming OC48 optical signals) into up to eight different outgoing OC3/OC12-rate electrical signals. The node is configured to perform automatic signal provisioning, which may be (a) the addition of a new OC3/OC12 signal; (b) the deletion of an existing OC3/OC12 signal; (c) the rate-upgrading of an existing OC3 signal to an OC12 signal; or (d) the rate-downgrading of an existing OC12 signal to an OC3 signal.

Abstract: A method and apparatus for high throughput multiplexing of data is described. It includes a circuit including: A first multiplexer having an output, a first input, a second input, and a selector. A second multiplexer having an output, a first input, a second input, and a selector, the output of the second multiplexer coupled to the first input of the first multiplexer. A third multiplexer having an output, a first input, a second input, and a selector, the output of the third multiplexer coupled to the second input of the first multiplexer; and the selector of the first multiplexer to select an input with a stable signal.

Abstract: Virtual concatenation circuitry is disclosed for implementation in a network element of a data communication network. The virtual concatenation circuitry in a preferred embodiment is operative: (i) to maintain, for each of the individual member streams of a virtual concatenation stream, a corresponding counter which tracks pointer adjustments for that member stream; and (ii) to generate pointers based on values of the counters so as to substantially equalize incoming and outgoing pointer adjustments for the member streams at the network element.

Abstract: An interface device for providing a gateway function between lines of a public switched telephone network (PSTN) that carry digital hierarchy signals and an asynchronous transfer mode (ATM) backbone network that carries signals in ATM format, the interface device comprising: a telephony transceiver operative to receive upstream digital hierarchy signals in a plurality of digital hierarchies from the PSTN; a hierarchy converter associated with the telephony transceiver and operative to convert at least some of said upstream digital hierarchy signals in a plurality of digital hierarchies to upstream signals in a single digital hierarchy distributed over a plurality of logical channels; an inverse multiplexing unit operatively associated with the hierarchy converter and operative to inverse-multiplex the upstream signals in the single digital hierarchy distributed over a plurality of logical channels; an ATM framer operatively associated with the inverse multiplexing unit and operative to map at least some of th

Abstract: Engine control apparatus for use in passenger cars and other applications includes a special calibration of the intake mixture preparation system. Although this calibration duplicates the optimum calibration for use with a continuously variable transmission (CVT), the apparatus instead includes, for reasons of practicality, a discrete-ratio powershift transmission. Also included is a feedback control system which dispenses with the conventional mechanical connection between accelerator pedal and engine throttle valve. This drive-by-wire control system operates the engine as closely as is practical to the optimum CVT engine operating schedule, a predominantly wide-open-throttle engine operating schedule. The overall combination of special engine calibration and drive-by-wire control with a discrete-ratio transmission can offer the majority of the fuel economy advantage available with a CVT.