Abstract: A digitally configurable multiplexer/de-multiplexer including several multiplexers, a switch matrix, and configuration logic. Each multiplexer receives multiple address signals, selects from among multiple first data signals and couples a selected first data signal to a corresponding one of several multiplexed signals. The switch matrix has a first interface coupled to the multiplexed signals and a second interface coupled to multiple second data signals. The configuration logic receives selection signals and controls the switch matrix to couple selected ones of the multiplexed signals to the second interface.

Abstract: A network element employing a universal mapper enables multiple services to be mapped onto a physical medium (metallic link with a particular physical layer protocol) so that the number of service mappers, and hence the complexity of the network element, may be reduced, the cost of provisioning the device may be reduced, and new services may be deployed, such as Ethernet over T1. The universal mapper may be configured to generate frames for transmission over multiple physical mediums utilizing a protocol known as Generic Framing Procedure (GFP). Using this embodiment, services such as ATM, Frame Relay, Ethernet, IP/PPP, Voice, and Infiniband may be transported in GFP frames over metallic links operating using xDSL, T1/E1, T3/E3, or cable access technologies by utilizing a single GFP framer and a single set of service mappers.

Abstract: A synchronous transfer mode (STM)-256 adder/dropper which provides a communication path between STM-64 optical channels in an apparatus of multiplexing STM-64 optical channels into STM-256 electrical signals, is provided. The STM-256 adder/dropper transmits STM signals by multiplexing the STM signals at a low speed and simultaneously provides a communication path between lower channels.

Abstract: The present invention provides a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data conversion circuits receive the first bit streams and produce second bit stream(s), wherein the number and bit rate of the first and second bit stream(s) differ. Symmetrical pathways transport the first bit streams from the input ports to the data conversion circuits, wherein their transmission time(s) are substantially equal. A clock distribution circuit receives and symmetrically distributes a clock signal to data conversion circuits. A central trunk coupled to the clock port and located between a first pair of circuit pathways with paired branches that extend from the trunk and that couple to the data conversion circuits make up the clock distribution circuit. The distributed data clock signal latches data in data conversion circuits from the first to the second bit stream(s).

Abstract: A single coder/decoder shared among several multiprocessors in a digital signal processing system through time-division multiplexing between multiple processors to enhance signal processing capabilities by assigning different digital-to-analog channels to different processors for digital-to-analog conversion, while allowing all processors to operate on the same analog-to-digital data for analog-to-digital conversion, thereby resulting in chip area reduction and power consumption saving.

Abstract: A data transmission apparatus using a virtual concatenated path in an SDH transmission system is capable of engaging one or more extra paths by an automated sequence execution to meet a traffic requirement that is higher than usual but up to a maximum speed of a user who is usually assigned virtual concatenated paths in a number smaller than capable of transmitting the maximum traffic.

Abstract: A subscriber platform for broadband communication, according to various aspects of the present invention, includes an antenna, a plurality of transceivers, and a processor. The antenna supports communication via a plurality of directional beams. The plurality of frequency agile transceivers operate simultaneously, each transceiver being coupled to the antenna for communication via a respective directional beam. The processor is coupled to the plurality of transceivers. And, the transceivers are coupled to the antenna to communicate data among the directional beams as directed by the processor, communication including directional diversity and frequency diversity.

Abstract: A cross-connect switch (1000) is adapted for a plurality of input channels in a synchronous network. Each input channel has a pointer processor (800) including a pointer interpreter (802), an elastic store buffer (804), and a pointer generator (806). The cross-connect switch (1000) further comprises a memory-less space switch (1020) interposed between a plurality of pointer interpreters (1010) and a plurality of elastic store buffers (1030). The space switch (1020) switches selected outputs of the plurality of pointer interpreters (1010) to inputs of each elastic store buffer (1000) in response to a switching control signal.

Abstract: A system, method, and article of manufacture suitable for transmitting a programmable message in place of or intermixed into a streaming media data stream to a receiving device upon receipt of an event is disclosed.

Abstract: First and second transmission links are established with a remote station. An information signal is encoded to provide an encoded information signal having more bits than the information signal. First and second transmission signals are provided wherein each transmission signal has bits selected from the encoded information signal. Each of the first and second transmission signals is transmitted to the remote station by way of a respective one of the first and second transmission links. The remote station receives and combines the first and second transmission signals transmitted by the remote station to provide a combined encoded signal. The combined encoded signal is decoded by the remote station to provide the information signal. The first and second transmission links can be formed between the remote station and a single base station or between the remote station and two separate base stations.

Abstract: Systems and methods are described for bonding asynchronous transfer mode permanent virtual circuits using a multi-link segmentation and reassembly sublayer. A method includes: transforming a stream of asynchronous transfer mode cells into a stream of bonded asynchronous transfer mode cells; demultiplexing the stream of bonded asynchronous transfer mode cells into a plurality of streams of inverse multiplexed bonded asynchronous transfer mode cells; and transmitting the plurality of streams of inverse multiplexed bonded asynchronous transfer mode cells to a remote location via a plurality of permanent virtual circuits, characterized in that the transmitted plurality of streams of inverse multiplexed bonded asynchronized transfer mode cells can be multiplexed into a multiplexed stream of asynchronized transfer mode cells after transmission via at least two permanent virtual circuits, which compose the plurality of permanent virtual circuits, that do not have an identical bit-rate.

Abstract: An optical packet switch switches optical packets according to bit-rates at which the optical packets are provided. For example, optical packets that are received at similar bit-rates may be routed to a destination at separate time slots over a single channel wavelength, and optical packets that are received at different bit-rates may be routed to the destination over separate channel wavelengths. When optical packets are provided at different bit-rates on a plurality of input paths, optical packets provided at low bit-rates may be compacted before switching to the destination. Alternatively or additionally, the bit-rates of the optical packets may be balanced before switching to the destination. Bandwidth contention among optical packets may be resolved by polarizing optical packets originating from separate input paths in different polarization directions, and merging optical packets having different polarization directions onto a single switched channel wavelength.

Abstract: An integrated digital loop carrier (IDLC) system includes digital line feeders and signal processors to interface with the feeders an to ultimately provide data to subscriber instruments. The system can be employed as a central office terminal (COT) or remote digital terminal (RDT) with analog, T1 or SONET feeders and any conventional link medium. Data are put in DS1 format and multiplexed onto token ring optical loops for delivery to banks of channel units wherein the optical signals are translated to electrical signals for delivery to the Cus and subscribers. A method and apparatus is provided for mapping and demapping signals between virtual tributaries (VT) and digital signal formats in the RDT of an integrated digital loop carrier.

Abstract: In a digital circuit multiplication equipment (DCME) equipped with tandem pass-through function, a speech coding device and a speech decoding device are resettable in a synchronous resetting mode. The DCME includes a transmission device and a unit to continuously assign and transmit data from a trunk channel to another DCME via a bearer circuit and an exchange during pass-through operation.

Abstract: A bound mode mechanism and technique efficiently accommodates high-bandwidth data traffic flow within an intermediate node of a computer network. The bound mode mechanism combines two half-slot line card connectors of a backplane in an aggregation router into a single full-slot line card arrangement to thereby increase the bandwidth provided to a high-speed, full-height line card of the router. The technique is also capable of accommodating generic half-slot (i.e., subslot) connectors, each of which is capable of supporting a variety of data formats. The bound mode mechanism further allows use of a high-speed trunk card without the penalty of supporting high trunk level bandwidth on all of the slot connectors of the router. The mechanism enables use of a simple backplane, while also maintaining a low pin count on a backplane logic circuit of the router.

Abstract: A SONET multiplexed system architecture that permits greater levels of integration. The architecture includes a time slot interchanger for routing information from at least one SONET input signal path associated with a respective first time slot to at least one SONET output signal path associated with a respective second time slot. Each input signal path includes a pointer interpreter, and each output signal path includes a FIFO buffer serially coupled to a pointer generator. The architecture further includes a synchronization buffer in each input signal path for transferring the input signal to the clock rate of the time slot interchanger. The architecture permits greater levels of integration when the time slot interchanger has more inputs than outputs, and/or the time slot interchanger provides the output signal to a pointer processor to transfer the output signal to the clock rate of the output signal path.

Abstract: Systems and methods for conveying multiple low-bit-rate data streams over a data transport medium which is configured to transport data in a single, high-bit-rate data stream. In one embodiment, a plurality of low-bit-rate signals are received and a corresponding data rate is determined. Each of the signals is formatted in frames comprising a payload and overhead data. The high-bit-rate signal is also formatted in frames comprising a payload and overhead data, but the frames (including payload and overhead) contain more bits than those of the low-bit-rate frames. The payloads of the low-bit-rate frames are mapped into the payloads of the high-bit-rate frames. The overhead and timing data of the low-bit-rate frames are mapped into the unused portion of the overhead of the high-bit-rate frames. After the high-bit-rate signal is transported, the payload, overhead and timing data of each of the low-bit-rate signals is extracted, and the corresponding signals are reproduced.

Abstract: Variable bit rate information is transmitted across a transmission link (20) at a constant bit rate by multiplexing individual variable bit rate elementary data streams (161 and 162) into a composite data stream (18) having a constant bit rate. A receiving device (22) receives the constant bit rate stream but delays processing thereof by an interval typically a fraction of the transmission interval. Following the delay interval, the receiving device processes the data at a rate that is independent of, but typically not greater than, the constant bit rate.

Abstract: A precoding-multiplexing circuit is formed by a precoding circuit for carrying out a precoding with respect to n sets of parallel input binary data signals having a bit rate equal to R/n, to obtain n sets of parallel precoded signals, and a time division multiplexer for time division multiplexing the parallel precoded signals obtained by the precoding circuit, in units of one bit, and outputting time division multiplexed output signal having a bit rate equal to R. In this configuration, the encoding is realized by processing electric signals before the time division multiplexing, so that it becomes possible for the preceding circuit to handle signals which are slower than the transmission rate, and therefore it becomes easier to realize the higher transmission rate.

Abstract: A system and method for the simultaneous transmission and rendition of multiple MPEG-encoded digital video signal streams in an interactive television application are disclosed. Simultaneous transmission and rendition of multiple MPEG-encoded digital video signal streams in an interactive television application generally comprises determining a value for a display position code corresponding to a display position of each slice of each of the MPEG-encoded video streams, modifying the value of the display position code of each slice of each of the MPEG-encoded video streams as necessary, and interleaving each slice of each of the MPEG-encoded video streams as modified into a single composite video stream. The modifying preferably maintains bit-alignment of the display position code within a byte.

Abstract: A data optimization engine disposed inline with a first communication channel and a second communication channel. The data optimization engine comprises a transmit interface circuit configured to receive a first data stream from the first communication channel and to obtain a first data file from the first data stream. The data optimization engine further includes an optimization processor coupled to the transmit interface circuit for receiving a second data file from the transmit interface circuit. The second data file represents the first data file after the first data file has been processed by the transmit interface circuit into a format suitable for optimization by the optimization processor. The optimization processor performs one of a compression and an encryption on the second data file, thereby obtaining all optimized data file. In one embodiment, the first data file is a Fiber Channel data frame.

Abstract: A transmitter (10) for transmitting a multiplex signal (20) containing a number of tables with information about the signal (11) to a receiver (12), capable of selecting some or all of these tables (26) from the signal (20) and storing them on a table storage medium (22). The stored tables (27) are transmitted for example when the receiver (12) requests them, or when the information therein is updated. By storing these tables in the transmitter (10), the problem that the receiver has to wait for them to occur in the multiplex signal (10) is overcome.

Abstract: A method for routing network switching information includes generating at one Time Slot Network (TS Net) data firame from at least one data frame of a first type. The TS Net data frame comprises switching event information. The TS Net data frame is transferred and stored among a number of network elements using a backplane network. Compare operations are performed among prespecified data frames of the TS Net data frame, and at least one interrupt signal is generated in response to detected changes resulting from the compare operations. Information routing is controlled in at least one network and the associated network elements in response to the interrupt signals.

Abstract: The present invention provides methods and apparatus for reconfiguring protocol data for a multiplexed data stream which is reduced to carry fewer services for cable-side transmission in a cable television plant or the like. More particularly, the present invention provides methods and apparatus for reconfiguring protocol data for a desired combination of multiplexed data stream subgroups contained within an incoming high data rate data stream, such as a high data rate Quadrature Phase Shift Keying (QPSK) modulated multiplexed data stream, when the incoming multiplexed data stream is reduced.

Abstract: The present invention makes it possible to efficiently transmit data for statistical multiplexing which is required for control using statistical multiplexing. By utilizing private packets, respective encoding devices transmit encoding difficulties serving as the data for statistical multiplexing to a multiplexer (4) via the same transmission channels as encoded video data and audio data are transmitted. The multiplexer (4) conducts multiplexing processing on data supplied from the respective encoding devices at a first rate R1 larger than a transmission rate on a transmission channel of a subsequent stage, and outputs a transport stream (TSd including the private packets to a statistical multiplexing computer.

Abstract: The invention relates particularly to the switching of an SDH low order VC-3 using a high order switching apparatus, such as an STS switch. A low order VC-3 is aligned with a TU-3 pointer to form a TU-3. The TU-3 is mapped into a high order VC-3 type data structure which, in turn, is aligned with an AU-3 pointer to form an AU-3 type data structure. The AU-3 type data structure is suitable for switching by the high order switch. After switching, the AU-3 type data structure is combined with similar AU-3 type data structures and converted into an AU-4 suitable for transmission across an SDH/SONET network. Advantageously, the arrangement is such that each AU-3 pointer has the same fixed value. Hence, conversion to an AU-4 is achieved by a fixed pointer replacement operation.

Abstract: In order to allow various user setups associated with a communication using a plurality of communication channels, the number of communication channels used in a communication with a single partner is varied depending on whether or not the automatic answering mode is set. The number of communication channels used in the communication with the single partner can be independently set in correspondence with transmission and reception. The number of communication channels used in the communication with another communication partner can be independently set in correspondence with whether an incoming call or a call origination request is detected.

Abstract: A method and apparatus for processing data packets of differing protocols across different channels within signals are described. In an embodiment, a method includes receiving at least one signal, wherein the at least one signal includes a number of channels such that each of the number of channels can include different protocols and different configurations for the different protocols. The method also includes processing data packets in each of the number of channels in a predefined order.

Abstract: According to the present invention a method and a device is provided for combining at least two data signals having a first data rate into a single data stream having a second data rate being higher than the first data rate for transmission on a shared medium or vice versa, said device comprises at least one port for receiving said at least two data signals and a port addressing unit for extracting data from the data signals received by said ports, wherein said port addressing unit is configured to place the extracted data at predetermined positions in said single data stream to be transmitted on said shared medium and at least one control data insertion unit is provided for placing control data in said single data stream. Thus, a method and device proposed implementing a multiplexing structure in which the data from M parallel low-speed channels are multiplexed onto a data bus operating with M times the data rate of the M low-speed channels. A multiple-stage process where, e.g.

Abstract: A PC-type computer has a system bus (e.g., a PCI bus) configured with a main CPU board, a statistical multiplexing (stat-mux) board, and a plurality of video/audio encoder boards, each configured to receive and compress a corresponding video/audio stream. The stat-mux board performs statistical multiplexing on the different compressed bitstreams to transmit multiple bitstreams over individual shared communication channels. Although each of the boards is configured to the system bus, each encoder board has a digital signal processor (DSP) with a synchronized serial interface (SSI) output port that is directly connected to an SSI input port on a DSP on the stat-mux board (which, in one embodiment, has four such DSPs each with six such SSI input ports). As such, (up to 24) compressed video/audio bitstreams generated on the various encoder boards can be transmitted directly to the stat-mux board without having to go through the system bus.

Abstract: Data transmission apparatus for multiplexing one or more channel data streams of equal, predetermined, data rate into a transmission data stream comprises: means for generating a control data stream of the same data rate as the channel data rate, in which first periodically repeating portions of the control data stream provide a synchronisation signal and second periodically repeating portions of the control data stream provide identification data specifying information about the channel data streams with reference to a predetermined ordering of the channel data streams; and means for multiplexing the control data stream with the one or more channel data streams in a cyclic pattern of equally-sized data portions so that a data portion from the control data stream is followed by data portions from each of the channel data streams according to the predetermined ordering of channel data streams.

Abstract: A method for establishing a digital communication link between an originating subscriber terminal and at least one called subscriber terminal, said method being better adapted to the transmission bandwidth used by a subscriber, has the following steps: First, a provisional link at a standard transmission rate from the originating subscriber terminal to the called subscriber is requested from a switching center. That provisional link is then established by the switching center. Next, a new, lower value for the transmission rate is selected by the originating subscriber terminal. That new value is then agreed upon with the switching center. Lastly, the latter switches the transmission rate of the provisional link over to the new, lower value, thus completing establishment of the communication link. The invention can advantageously be used in a telecommunications network, which for example operates according to the ISDN standard, to economize on transmission capacity and reduce call charges.

Abstract: An 1:n or m:n path protection mechanism is provided. Rather than defining an automatic protection protocol, use is made of the existing tandem connection monitoring function, tandem connection reverse defect indication, and tandem connection trail trace identifier. Upon detection of a failure on the working path segment, the occurrence of this failure is communicated to the far end node by inserting forced RDI into the tandem connection as long as the failure persists. In the case of more than one protected paths, the failed path is identified by means of the unique trail trace identifier received on the protection path. In the case of several protection paths, one network node is defined as slave node which has to follow the switch-over initiated by the master node and choose the same protection path as the master node. Preferably, a combination of two timers enables return from failure condition to normal operation.

Abstract: In a transmission method and apparatus, low-speed SDH signals are multiplexed into a high-speed SDH frame, the high-speed SDH frame including at least an information payload, a line overhead and a section overhead, the section overhead being divided into a first section overhead SOH and a second section overhead SOH, the first SOH carrying regenerator SOH bytes and the second SOH carrying multiplex SOH bytes. The multiplex SOH bytes in the second SOH of the high-speed SDH frame are detected without changing the line overhead and the payload when the high-speed SDH frame reaches a receive-side high-level line terminating equipment. The multiplex SOH bytes in the second SOH of the high-speed SDH frame are generated without changing the line overhead and the payload before the high-speed SDH frame is transmitted by a transmit-side high-level line terminating equipment.

Abstract: Multi-channel Ethernet port data, each including communication data and control data, are time-division multiplexed (TDM) into a SONET/SDH frame for transport. Ethernet port data for each of a plurality of channels is sequentially read in units of a byte that is one of communication data and control data, and a TDM frame containing one byte for each of the plurality of channels is sequentially generated. A frame of a digital synchronous network is generated by containing the plurality of TDM frames in a payload portion thereof and is transported through the SONET/SDH network.

Abstract: A multiplexing apparatus/method is characterized by inputting a plurality of data streams with which identification information of data is multiplexed, extracting the identification information multiplexed with the plurality of input data streams from the plurality of input data streams, detecting pieces of identification information, of the extracted identification information extracted, which are redundant among the respective data streams, replacing the detected identification information with new identification information, and multiplexing the plurality of data streams obtained by replacement.

Abstract: The present invention relates to a device for combining at least two data signals having an input data rate into a single data stream having an output data rate being higher than the input data rate for transmission on a shared medium or vice versa, particularly, to a single SDH/SONET framer capable of handling a large range of SDH/SONET frames from STM-i to STM-j with an aggregated total capacity corresponding to an STM-j frame where i and j are integers in the range from 1 to 64 or higher according to the STM-N definition of the SDH/SONET standards. More over, the present invention can also be extended to work with STS-1 as lowest range. STS-1 exists in SONET only not SDH and corresponds to a data rate of 51.5 Mb/s a third of the 156 Mb/s of STM-1.

Abstract: A time multiplexed multiple carrier transmitter includes a first data encoder that produces first transmit data and a second data encoder that produces second transmit data. In addition, the transmitter includes a digital multiplexer coupled to the first and the second data encoders. The digital multiplexer provides a transmit signal output. A transmit frequency upconverter coupled to a power amplifier and the transmit signal output provides a final upconversion (or direct upconversion) to a transmit frequency for each channel. The transmitter also includes a multiplexer control circuit coupled to the digital multiplexer through a multiplexer control input. The multiplexer control circuit produces a multiplexer control signal on the multiplex control input that selects between the first and second data encoders according to a transmit schedule. The transmit schedule determines when, at the frequency at which, the transmitter selects and transmits data from each data encoder.

Abstract: An apparatus and method for enabling the transport of a higher line rate time-multiplexed data signals (e.g., Ethernet at 10 Gb/s) at a lower line rate (e.g., SONET OC-192) and for regenerating the higher line rate time-multiplexed data signals at the receiving end. At a transmitter end, a data stream compression apparatus removes a predetermined portion of non-unique, invariant content of the higher line rate data stream thereby generating the lower line rate data stream which is transmitted over a communication link to the receiver end. At the receiver end, a data stream expansion apparatus adds back the missing predetermined portion of non-unique, invariant content to the lower line rate data stream thereby regenerating the higher line rate data stream. A data compression multiplexer apparatus is formed by combining a plurality of the data stream compression apparatuses with a data multiplexer.

Abstract: A high-speed communications system which permits high-speed communication services to be implemented with minimum modification to the existing communications facilities. A multiplexer/demultiplexer unit multiplexes outgoing signals to a network and demultiplexes incoming signals from the network separately for voice and data signals. A first voice processing unit, being linked to a voice service subscriber who only uses voice communication services, processes voice signals for bidirectional communications over a subscriber line. A second voice processing unit, being linked to a voice/data service subscriber who uses both voice and data communication services, processes voice signals for bidirectional communication. An office-side modem unit has modulator/demodulator functions to support high-speed bidirectional data communication for the voice/data service subscriber. An office-side splitter splits incoming signals from the voice/data service subscriber into separate voice and data signals.

Abstract: A multiplexing and transmission apparatus including a transmitter and a receiver is provided. The transmitter includes a control pulses generating circuit generating control pulses having different phases; channel-frame generating circuits each outputting low-speed frame signal in synchronization with the control pulse; and a multiplexing circuit multiplexing the low-speed frame signals into the high-speed serial signal. The receiver includes a demultiplexer demultiplexing high-speed serial signal into low-speed frame signals; channel-frame synchronization circuits each generating a frame pulse corresponding to the low-speed frame signal; a switching circuit switching each of the low-speed frame signals to an appropriate port of the channel; and a switch controller circuit controlling the switching circuit.

Abstract: A single framer engine operates on multiple DS1 lines. The framer engines includes a memory structure for pre-aligning and storing data received from a line interface unit. The memory structure is configurable for compatibility with standard transmission formats. A recognition or comparison unit processes the pre-aligned data to determine the proper pattern sequence.

Abstract: To perform a reliable and calibrated measurement of partial discharges, a first calibratable sensor and a second sensor are arranged in a metal enclosure. The first calibrated sensor picks up signal components in the HF (High Frequency) range, and the second non-calibrated sensor picks up signal components in the UHF (Ultra-High Frequency) range. An HF signal component picked up by the first sensor is transmitted to a partial discharge analyzer. The opening time of the gate device is determined by a UHF signal component picked up by the second sensor.

Abstract: Apparatus for switching full rate (e.g., 64 kilobit per second) signals and composite signals comprising a plurality of subrate signals (e.g., 32 kilobit per second subrate signal). The apparatus includes a unit for compressing selected ones of a plurality of full-rate signals into a smaller plurality of full-rate single and composite signals, and apparatus for decompressing composite signals into a plurality of full-rate signals. The main elements of the switching fabric of the switch continue to switch full-rate signals. Advantageously, during periods of heavy load, the switching network fabric of a switching system can carry more calls, and more traffic can be carried between switches equipped for subrate switching.

Abstract: A communication switching station includes a digital switch and a sub-rate interface circuit. The switch has signal terminals including inputs and outputs, and switching circuitry, adapted to operate at a first rate, operatively connected between the inputs and outputs. The sub-rate interface circuit includes a first signal terminal operatively connected to at least one of the signal terminals of the first signal terminal and the second signal terminal, the programmable circuitry being operative at a second rate that is lower than the first rate.

Abstract: At a transmission side, an encoder 4 codes data of each channel and inserts a special character attributing to each channel. A character multiplex circuit 5a byte multiplex each channel for outputting. At a reception side, a character synchronization circuit 9 synchronized with a character by detecting the special character. A character demultiplex circuit 10a demultiplexes a signal by a character byte and obtains data of each channel. A channel identification circuit 11 identifies each channel by detecting the special character attributing to the channel without bit rotating for synchronization. A decoder 14 executes decoding without bit rotating and outputs a signal from a channel demultiplex circuit.

Abstract: A digital carrier telephony system for delivering voice and data telephony services to subscribers in rural locations having low population densities. A Central Office processes telephony signals having subscriber channels. A Terminal (COT), which is connected to the CO and to one end of a digital carrier line, can transmit outgoing digital carrier line signals on the digital carrier line in response to multiplexing the subscriber channels of telephony signals received on a wired link from the CO. The COT also can transmit telephony signals to the CO in response to demultiplexing subscriber channels of incoming digital carrier line signals received on the digital carrier line. At subscriber locations, multiple remote drop units are typically connected to the digital carrier line. The remote drop unit can insert one of the subscriber channels into the multiplexed subscriber channels of one of the incoming digital carrier line signals.

Abstract: The invention provides a transceiver which is preferably used for high speed communications between a customer location and a central office over a subscriber line. The transceiver uses a pseudorandom noise generator both to provide a correlation for a complementary transceiver to use in achieving synchronization and as a way to transmit data in an extremely robust fashion. In addition, the transceiver uses frequency domain multiplexing so that downstream data and upstream data are transmitted by their respective transceivers in completely separate and distinct frequency bands. In order to achieve high data transfer rates, the transceivers can operate in an asymmetrical manner, whereby either (but, typically, the central office) transceiver can transmit data at a higher rate than the other transceiver.

Abstract: Multiplexing and demultiplexing are commonplace for an efficient bandwidth utilization in telecommunications. SRTS (Synchronous Residual Time Stamp) technique is widely used for timing recovery in processing of digital signal streams. The bit stuffing is also prevalent for various purposes, one being rate adjustment. The invention performs the SRTS technique entirely digitally to monitor the rate of slower speed signal streams in relation to the rate of a higher speed stream. The digital implementation permits the use of context switching for processing a plurality of digital signal streams. As the result, hardware requirement is greatly reduced.

Abstract: An interfacing device (INT) which replaces M outgoing sets of bits out of N outgoing sets of bits (OS1, OS2, . . . , OSN) by M incoming sets of bits (IS1, IS2, . . . , ISM), M being smaller than N, includes:a. an outgoing register (OR) wherein the N outgoing sets of bits (OS1, OS2, . . . , OSN) are temporarily stored; andb. a selection means (SEL) comprising a multiplexer bank (MUX) with N multiplexers (MUX1, MUX2, . . . , MUXN) each having one output and at most M inputs whereto at most M incoming sets of bits are applied, and a control unit (CTRL) for the multiplexer bank (MUX). The control unit (CTRL) can control the multiplexers (MUX1, MUX2, . . . , MUXN) so that an appropriate order is respected by the outgoing sets of bits (OS1, OS2, . . . , OSN).