Abstract: Apparatus for switching full-rate (e.g., 64 kilobit per second) signals and composite signals comprising a plurality of sub-rate signals (e.g., 32 kilobit per second sub-rate signal). The apparatus includes a unit for compressing selected ones of a plurality of full rate signals into a smaller plurality of full rate single and composite signals, and apparatus for expanding composite signals into full rate signals. Advantageously, during periods of heavy load, the switching network fabric of a switching system can carry more calls, and more traffic can be carried between switches equipped for sub-rate switching.

Abstract: A terminal for use in a multi-point video conference system that includes a plurality of terminals connected to each other via a network, the terminal includes a compressor for packetizing video data inputted from a video camera, and outputting packetized data to the network. A decompressor receives a plurality of packets transmitted from other terminals via the network in a time sharing manner, and decompresses the received packets in an order of reception. The decompressor outputs decompressed video information. A plurality of storage elements store the decompressed video information in a frame unit. The contents stored in the storage elements are displayed on a display. A switch changes over the contents of the storage elements to supply the display.

Abstract: A digital optical telecommunication method including the steps of: generating a digital modulated optical signal in an optical transmitting station, which signal corresponds to a first electric input signal carrying a piece of information; feeding the modulated optical signal to an optical-fiber line; receiving the modulated optical signal transmitted from the optical-fiber line at an optical receiving station, converting it to an electric form and thereat generating a second digital electric signal; wherein the modulated optical signal is coded in a sequence of elementary information units at a first frequency and wherein the step of generating a second digital electric signal comprises detecting in said converted signal, an electric signal having a second frequency higher than the first frequency and recognizing in said detected signal, the phase of an electric signal at the first frequency by comparing a received sequence of elementary information units with at least one reference sequence and verifying th

Abstract: A method for controlling the data bit rate of a differential pulse code modulation/discrete cosine transform (DPCM/DCT) video encoder, which is adapted to achieve a bit rate control in accordance with a video signal band compression scheme using a differential pulse code modulation (DPCM) and a discrete cosine transform (DCT), thereby obtaining a supreme picture quality while preventing a buffer overflow or underflow phenomenon from occurring in the encoder. The method includes the steps of determining an initial bit allocation amount for every group of pictures (GOP) of an input video, allocating bits for every picture of each GOP, allocating bits for every macroblock of each picture, determining a quantizer step parameter based on the bit allocation amount, and determining a quantizer step size proportional to the determined quantizer step parameter.

Abstract: A method and apparatus 200 for converting dual 4-wire digital data services (DDS-1 and DDS-2) for transmission over a single twisted pair telephone line 205. The present method includes use of a digital data service remote terminal 219 and a digital data service central office terminal 201. Each terminal converts more than one 4-wire digital data services into a 2B1Q signal for transmission over the single twisted pair telephone line 205. The present method provides an efficient and cost effective technique for increasing 4-wire digital data services to a customer premises without a corresponding increase in the number of telephone lines.

Abstract: A system that allows multiple bundles of plesiochronous digital hierarchy (PDH) payload data streams to be synchronously trasmitted from one point to another is described. The system multiplexes multiple stages of the PDH using a single clock signal. This removes the need to perform stuffing and de-stuffing of the data streams at the various stages of the multiplexing.

Abstract: Apparatus for asynchronously generating control signals (CONTROL) is disclosed including a plurality of sources (5) of asynchronous data signals and a plurality of data processing channels (10, 14), each processing one of the data signals in response to a control signal (CONTROL). Each of a plurality of parameter determining circuits (10, 16) produces a signal (COMPLEXITY) representing a parameter of one of the data signals. A data sampler (30) samples the signals (COMPLEXITY) from all of parameter determining circuits (10, 16) substantially simultaneously at predetermined sampling time intervals. A control signal generator (30) generates control signals (CONTROL) for the data processing channels (10, 14) having values based on the sampled parameter representative signals (COMPLEXITY) and the preceding sampling time interval.

Abstract: Two T1 signals are mapped onto a subscriber bus (26) in a subscriber loop equipment (10) for transport between a bank control unit (20) and channel units (22), for example. The data channels and the signaling and control channels of the first T1 signal are mapped onto a first data stream, and the data channels and the signaling and control channels of the second T1 signal are mapped onto a second data stream. The data streams are bit-interleaved for transport on the subscriber bus (26).

Abstract: A system and method for monitoring and collecting performance characteristics of a target system and providing the results by way of time-division multiplexing is provided. The performance monitor includes a mechanism for latching a plurality of performance attribute signals. An output circuit, coupled to the latching mechanism, is used to output the latched performance attribute signals in groups, wherein each of the groups is a subset of all of the performance attribute signals. The performance monitor further includes a time division circuit coupled to the output circuit, to allow the output circuit to output each of the groups of performance attribute signals at different times. Each group of performance attribute signals can therefore be transmitted via common output access points, although at different times as the groups are transmitted in succession.

Abstract: A pure ATM based multiplex is incapable, especially at low carrier rates, of satisfactorily carrying constant bit rate traffic or/human communication traffic. A multiplex format having a plurality of constant bit rate timeslots in which a timeslot is not in use for constant bit rate traffic can have that timeslot used for message based traffic to provide a composite constant bit rate/message based data stream.

Abstract: A system and method are provided for multiplexing/demultiplexing asynchros high-speed digital data and asynchronous low-speed digital data. A first digital signal processor (DSP) receives complete low-speed data messages and is programmed to assemble each complete message into data blocks in accordance with a block format. Each data block is identical in size and includes provisions for a header that identifies the data assembled therein. A second DSP has a plurality of I/O ports, each of which has a direct memory access (DMA) associated therewith. One of the I/O ports is coupled to the first DSP to receive each complete message assembled into data blocks. The other I/O ports are coupled to a second plurality of channels transmitting asynchronous high-speed digital data. The DMAs associated with the other I/O ports are configured to assemble the high-speed data into data blocks in accordance with the same block format used for the low-speed messages.

Abstract: A mixing circuit for synthesizing plural .DELTA..SIGMA. modulated data generated simultaneously with a bit rate F to single mixed data includes a slot determining section for dividing time length corresponding to 1-bit period of the .DELTA..SIGMA. modulated data into a number N which is of the same number as the plural .DELTA..SIGMA. modulated data, and a time division multiplex section for assigning in order the plural .DELTA..SIGMA. modulated data to the 1-bit period at a bit rate N*F on a time shared basis. The obtained mixed data can be converted to linear PCM data with a single decimation circuit. By increasing the bit rate of the mixed data by N times the bit rate F of the .DELTA..SIGMA. modulated data, a total gain can be maintained at a constant value irrespective of a change in the number of data to be synthesized.

Abstract: A multiplexer, preferably on an integrated circuit chip, receives a plurality of buses each having a plurality of lines responsive to binary indications and passes the binary indications in the lines of a particular one of the buses. The multiplexer includes a plurality of circuit blocks each responsive to the binary indications in the lines of an individual one of the buses. Each block has a plurality of recursive circuits each having first and second stages. The second stages of the recursive circuits in an individual one of the circuit blocks receive an individual one of a plurality of control indications at a first side of the block to activate the first stages in such recursive circuits. The first stage in each recursive circuit in each individual circuit block receives at a second side of the block the binary indications in an individual line in an individual one of the buses to obtain a signal from such first stage in accordance with such binary indication upon the activation of such first stage.

Abstract: A multiplexer includes an n-th stage as a final output stage (n=integer, 2.ltoreq.n); j stages (j=integer, 1.ltoreq.j.ltoreq.n-1), the n-th stage including a D flip-flop having a clock input terminal for receiving a first clock signal, a data input terminal for receiving serial data, and a data output terminal, the D flip-flop synchronizing the clock signal with the serial data; and a j-th stage including m.sup.n-j-1 (m=integer, 2.ltoreq.m) multiplexer blocks, each multiplexer block including D flip-flops and having data input terminals for receiving m parallel data inputs and a clock input terminal for receiving a second clock signal produced by frequency division of the first clock signal, and converting the parallel data into serial data in response to the second clock signal. The multiplexer further includes a variable delay circuit connected to the data input terminal of each multiplexer block in one of the second to the n-th stages for delaying the data input by a variable delay time.

Abstract: In known optical distribution systems, a signal intended for the subscribers is distributed from a transmitting point to all network terminations (point-to-multipoint transmission). The receivers, which are connected to a passive optical network, are adapted to a common bit rate. If a need for a higher data rate arises at a network termination, this need can only be satisfied in the prior art by converting all receivers. This is not possible without interrupting the service. Furthermore, the conversion entails great expense, since the receivers of these network terminations where the need for information is unchanged have to be converted as well. By a time-division-multiplexing method, a time-division multiplex signal is generated which has a frame whose duration is equal to one bit period (T) of a digital signal, and which is divided into k time slots (ZS). At least two time slots (ZS) are used for one digital signal, and one respective time slot (ZS) is used for each of the remaining digital signals.

Abstract: An interface unit having a digital hierarchy interface function for a communication device has parts disposed on a printed-wiring board in a Layout to maintain desired interface unit characteristics. The interface unit includes a plurality of parallel B/U converter blocks for converting bipolar signals in a plurality of channels into a plurality of unipolar signals, respectively, a plurality of parallel U/B converter blocks for converting unipolar signals in a plurality of channels into a plurality of bipolar signals, respectively, a connector disposed near the B/U converter blocks for connecting the B/U converter blocks to an external device, a shared processor LSI circuit connected to the B/U converter blocks and the U/B converter blocks and disposed near the U/B converter blocks, for interfacing the signals in the channels at a low speed, and a printed-wiring board supporting the B/U converter blocks, the U/B converter blocks, the connector, and the shared processor LSI circuit.

Abstract: A method and apparatus 200 for converting dual 4-wire digital data services (DDS-1 and DDS-2) for transmission over a single twisted pair telephone line 205. The present method includes use of a digital data service remote terminal 219 and a digital data service central office terminal 201. Each terminal converts more than one 4-wire digital data services into a 2B1Q signal for transmission over the single twisted pair telephone line 205. The present method provides an efficient and cost effective technique for increasing 4-wire digital data services to a customer premises without a corresponding increase in the number of telephone lines.