Adaptive Patents (Class 375/232)
  • Patent number: 8811465
    Abstract: In a reception device and a reception method for a multivalue VSB, QPSK, or mutlivalue QAM modulated signal, reliability information (R) is generated (22) on the basis of estimation results for the received signal transmission channel, and Viterbi decoding is performed on the basis of the reliability information (R). It may be so arranged that the smaller the absolute value of the difference between the maximum gain and the minimum gain within the transmission frequency band of the output of a transmission channel estimation means (17) is, the higher the reliability indicated by the output reliability information will be. Error correction capabilities can be improved in various transmission channel environments, and errors in transmitted data recovered at the receiving end can be reduced.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: August 19, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Jun Ido, Takashi Fujiwara
  • Patent number: 8811466
    Abstract: A cellular communication system comprises a Multiple-In Multiple-Out (MIMO) transmitter and receiver. The MIMO transmitter comprises a message generator for generating MIMO messages comprising selected training sequences and transceivers transmitting the messages on a plurality of antennas. The training sequences are selected by a midamble selector from a set of training sequences in response to an associated antenna on which the message is to be transmitted. The set of training sequences is associated with the cell of the MIMO transmitter and comprises disjoint subsets of training sequences for each of the plurality of antennas. The receiver comprises a transmit antenna detector which determines which antenna of the MIMO transmitter the message is transmitted from in response to the training sequence of the received message.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: August 19, 2014
    Assignee: Sony Corporation
    Inventors: Peter B. Darwood, Vishakan Ponnampalam, Alan Edward Jones
  • Publication number: 20140226705
    Abstract: An apparatus comprises a differential equalizer having: a) a first differential input, b) a second differential input, c) a first differential output, and d) a second differential output; a frequency detector coupled to the first and second differential inputs; an amplifier coupled to a first differential output and a second differential output of the differential equalizer; and a logical combiner having a first input coupled to an output of the frequency detector and an output coupled to a control input of the amplifier, wherein the logical combiner can mask at least one received de-emphasis parameter.
    Type: Application
    Filed: February 18, 2014
    Publication date: August 14, 2014
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Huawen Jin, Jawaid Ahmad, Yaqi Hu
  • Publication number: 20140226706
    Abstract: In various embodiments, a first and second complex multiplier may be configured to receive an input signal and provide a baseband I component signal and a baseband Q component signal, respectively. A first and second filter may be configured to filter the baseband I component signal and the baseband Q component signal, respectively. An equalizer may be configured to equalize the filtered baseband I component signal and the filtered baseband Q component signal. A carrier recovery portion may be configured to generate a reference signal based on the equalized filtered baseband I component signal and the equalized filtered baseband Q component signal. A first and second multilevel comparator may be configured to receive the equalized filtered baseband I component signal from the carrier recovery portion and provide an output I and receive the equalized filtered baseband Q component signal and provide an output Q signal for further modulation.
    Type: Application
    Filed: March 31, 2014
    Publication date: August 14, 2014
    Applicant: AVIAT U.S., INC.
    Inventors: Tjo San Jao, Richard Bourdeau
  • Patent number: 8804807
    Abstract: A method for removing distortions in a transmitted signal transmitted by a high power amplifier in a satellite communications system. The method characterizes the high power amplifier to define a series of Volterra coefficients and uses those coefficients in an equalizer in a receiver in the communications system to remove the distortions. The equalizer is a non-linear soft interference cancellation and minimum mean square error equalizer that employs three processing operations including parallel soft interference cancellation, minimum mean square error filtering and a priori log-likelihood ratio calculations.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: August 12, 2014
    Assignee: Northrup Grumman Systems Corporation
    Inventors: Daniel N. Liu, Michael P. Fitz
  • Patent number: 8804808
    Abstract: A dynamic equalization system and method for use with a receiver is provided. The receiver may include an antenna for receiving a signal having multipath signal components and a digitizer for obtaining and digitizing the received signal and multipath signal components. The digitized signal segment and multipath signal components may be discretized into signal segments of length n. Channel parameters of each of the discrete signal segments may be analyzed and locked to, and a time-domain representation of the analyzed channel parameters may be output. Each time-domain representation may be Fourier transformed into a frequency-domain representation, based upon which equalization parameters to equalize the multipath signal components for each of the analyzed channel parameters may be determined. The equalization parameters may be applied to corresponding signal segments of the digitized signal and multipath signal components so as to equalize the multipath signal components.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: August 12, 2014
    Assignee: The Aerospace Corporation
    Inventors: Robert B. Dybdal, Christopher J. Clark, Flavio Lorenzelli
  • Patent number: 8804799
    Abstract: A signal quality measuring apparatus includes a binary signal generating unit to generate a binary signal from an input signal; a level information extracting unit to extract level information from a relationship between the input signal and the binary signal using at least two window lengths; and a quality calculating unit to calculate a quality of the input signal based on the level information.
    Type: Grant
    Filed: March 18, 2010
    Date of Patent: August 12, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-soo Park, Kyung-geun Lee, In-oh Hwang, Hui Zhao, Jong-hyun Shin
  • Patent number: 8804805
    Abstract: Disclosed is a method of processing a stream of a digital broadcasting receiver. The method comprises: arranging at least one of new mobile data and known data in at least a portion of an existing mobile data region and in at least a portion of a normal data region, in a stream which includes the normal data region and the existing mobile data region; and composing a transmission stream where at least one of the new mobile data and the known data is arranged, and wherein the arranging combines a block of data arranged in the existing mobile data region and a block of the new mobile data in the stream, and performs serially concatenated convolution code (SCCC) coding on the combined blocks.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: August 12, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-hee Jeong, Hak-ju Lee, Se-ho Myung, Yong-Sik Kwon, Kum-ran Ji, June-hee Lee, Chan-sub Park, Ga-hyun Ryu, Jung-jin Kim, Kyo-shin Choo, Sung-il Park, Jong-hwa Kim
  • Patent number: 8804806
    Abstract: Disclosed is a symbol timing recovery circuit which includes an interpolator to generate, using a first filter, interpolation data of an input signal; a forward equalizer to eliminate, using a second filter, a forward interference wave from the input signal based on the interpolation data, and to output the resultant signal after the elimination, a first identification signal, and a first error signal; a backward equalizer to eliminate, using a third filter, a backward interference wave from the input signal based on the interpolation data, and to output the resultant signal after the elimination, a second identification signal, and a second error signal; and a timing recovery unit to generate a tap coefficient of the first filter, based on a tap coefficient of the second filter, a tap coefficient of the third filter, the first identification signal, the first error signal, the second identification signal, and the second error signal.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: August 12, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Tatsuaki Kitta
  • Patent number: 8804859
    Abstract: An apparatus of processing a time domain synchronous orthogonal frequency-division-multiplexing (TDS-OFDM) signal is provided. The apparatus includes a receiving block and a demodulating block. The receiving block receives the TDS-OFDM signal, and generates a down-converted signal according to the received TDS-OFDM signal. The demodulating block is coupled to the receiving block, and demodulates the down-converted signal to generate a transport stream. The demodulating block has a transmission parameter signaling (TPS) decoder implemented for performing a TPS decoding operation to generate a TPS decoding result and verifying a spectrum direction of the received TDS-OFDM signal according to the TPS decoding result.
    Type: Grant
    Filed: February 23, 2009
    Date of Patent: August 12, 2014
    Assignee: MediaTek, Inc.
    Inventor: Shun-An Yang
  • Publication number: 20140219327
    Abstract: Various embodiments described herein are directed to methods and systems for blind mode adaptive equalizer system to recover complex valued data symbols from the signal transmitted over time-varying dispersive diversity wireless channels. For example, various embodiments may utilize an architecture comprised of a bank of estimation units, a normalizing gain estimator, a DSP unit and a feedback shift register providing the equalizer feedback state vector. The estimation unit may be further comprised of a multiplicity of adaptive algorithms providing various filtered estimates of the data symbol to the DSP unit or providing the joint estimate of the transmitted data symbol.
    Type: Application
    Filed: February 7, 2013
    Publication date: August 7, 2014
    Inventor: Rajendra Kumar
  • Publication number: 20140219328
    Abstract: An equalization processing apparatus includes a correlation matrix generating unit. The correlation matrix generating unit calculates a correlation value between a plurality of paths of a received signal coming from the paths based on a correlation pattern selected from a plurality of correlation patterns indicating combinations of the numbers of correlation chips as arbitrary chips to be used for calculation of the correlation value among all the chips of the received signal and identification numbers of the correlation chips so as to generate a correlation matrix that is applied to equalization processing on the received signal.
    Type: Application
    Filed: April 7, 2014
    Publication date: August 7, 2014
    Applicant: FUJITSU LIMITED
    Inventor: Masatsugu Shimizu
  • Patent number: 8798121
    Abstract: A circuit includes a first wireless interface circuit that communicates packetized data to a first external device in accordance with a first wireless communication protocol. A second wireless interface circuit communicates packetized data to a second external device in accordance with a second wireless communication protocol. A plurality of signal lines communicate at least four lines of cooperation data between the first wireless interface circuit and the second wireless interface circuit, wherein the cooperation data relates to cooperate transceiving in a common frequency spectrum.
    Type: Grant
    Filed: May 10, 2007
    Date of Patent: August 5, 2014
    Assignee: Broadcom Corporation
    Inventors: Prasanna Desai, Mark Gonikberg, Brima B. Ibrahim, Edward H. Frank
  • Patent number: 8798127
    Abstract: Disclosed are apparatus and methods for adaptive receiver delay equalization. One embodiment relates to a method for adaptive receiver delay equalization. Filtered positive and negative polarity signals are generated by a first variable-delay filter and a second variable-delay filter, respectively. A delay difference is determined between the filtered positive and negative polarity signals, and a skew-indication signal is generated based on the delay difference. A delay control signal is generated based on the skew-indication signal, and the delay control signal is sent to at least one of the first and second variable-delay filters. Other embodiments and features are also disclosed.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: August 5, 2014
    Assignee: Altera Corporation
    Inventors: Weiqi Ding, Wei Li, Sergey Shumarayev
  • Patent number: 8798128
    Abstract: A method and a device which are for signal processing and are applied to a microwave communication system are disclosed. The method includes: performing equalization processing on each input signal by using an equalizer so as to obtain an equalized signal corresponding to the each input signal; performing phase estimation on phase noise in the equalized signal to obtain an estimated phase of the phase noise; performing phase rotation on the equalized signal to offset the estimated phase of the phase noise, so as to obtain a phase rotation signal; suppressing residual phase noise in the phase rotation signal by using a phase-locked loop so as to output an error signal and a received signal; and performing an iterative update on a filter coefficient of the equalizer by using the error signal.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: August 5, 2014
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Meng Cai
  • Publication number: 20140211839
    Abstract: A communication system having a receiver with a linear path and a nonlinear path. As the receiver receives a data signal, it adaptively equalizes the received signal, and amplitude-limits the equalized signal in the nonlinear path using a saturable amplifier limiter or the like. A slicer extracts data from the limited equalized received signal. In the linear path, a clock recovery circuit generates a clock signal from the equalized received signal. A delay circuit in the linear path at least partially compensates for propagation delay in the limiter. Having the clock recovery occur in other than the nonlinear path, a low jitter clock is generated. The limiter enhances the vertical opening of the data eye by increasing the rise and fall times of the limited signal, providing more noise margin for the slicer to operate with and a greater timing margin in which to sample the sliced data.
    Type: Application
    Filed: March 28, 2014
    Publication date: July 31, 2014
    Applicant: LSI Corporation
    Inventors: Mohammad S. Mobin, Pervez M. Aziz, Ye Liu
  • Publication number: 20140211837
    Abstract: A mobile communication device to equalize a Doppler shifted received signal according to one embodiment is configured to: extract one or more pilot signals from a segment of the received signal; perform Minimum Mean Square Error (MMSE) filtering on the extracted pilot signals, wherein the filter provides estimated pilot signal impulse responses; estimate the amplitudes of one or more path components of the estimated pilot signal impulse responses; estimate the phases of one or more path components of the estimated pilot signal impulse responses; and combine the estimated amplitudes and the estimated phases of the path components of the pilot signal impulse responses, wherein the combination provides an estimated channel impulse response.
    Type: Application
    Filed: May 15, 2012
    Publication date: July 31, 2014
    Inventors: Eugine Bakin, Grigory Evseev, Eugeny Pustovalov, Andrey Turlikov
  • Patent number: 8792544
    Abstract: An equalization device is arranged for equalizing a received signal, wherein the received signal may include a primary signal and at least one interference signal. The equalization device may include a transformation module, a serial-to-parallel converter, and an equalization module, wherein the transformation module may include a predictive decision feed-back equalizer, a first feed-back filter and an adder. The transformation module is arranged for generating a transformation signal according to the primary signal and the at least one interference signal of the received signal, wherein the transformation signal includes a transformed primary signal and at least one transformed interference signal. The serial-to-parallel converter is arranged for respectively converting the transformed primary signal and the transformed interference signal into a plurality of transformation signal sequences.
    Type: Grant
    Filed: August 1, 2012
    Date of Patent: July 29, 2014
    Assignee: Realtek Semiconductor Corp.
    Inventor: Yi-Lin Li
  • Patent number: 8792543
    Abstract: An impulse noise mitigation circuit (INMC) may set a cut-off frequency of each of two high pass filters to bound a frequency bandwidth of a desired signal, wherein a first of the two filters allows frequencies higher than the frequency bandwidth of the desired signal, and a second of the two filters allows frequencies lower than the frequency bandwidth of the desired signal. The INMC may compute and store a mean magnitude separately for a first signal response of the first filter and a second signal response of the second filter. The INMC may select the first filter for impulse noise mitigation when the mean magnitude of the second filter is greater than the mean magnitude of the first filter. The INMC may select the second filter for impulse noise mitigation when the mean magnitude of the first filter is greater than the second filter.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: July 29, 2014
    Assignee: MaxLinear, Inc.
    Inventors: Andy Lo, Sugbong Kang
  • Publication number: 20140204991
    Abstract: The present disclosure relates to a receiving node, and to a related method for determining when to apply a turbo equalization mode to compensate for Inter-Symbol Interference in a radio signal received over a radio channel from a transmitting node. The method comprises decoding the received radio signal into a decoded signal, determining a current error level in the decoded signal, predicting a turbo equalization gain based on instantaneous channel information of the radio channel and deciding whether to apply the turbo equalization mode depending on the predicted turbo equalization gain and the determined current error level in the decoded signal.
    Type: Application
    Filed: May 19, 2011
    Publication date: July 24, 2014
    Applicant: Telefonaktiebolaget L M Ericsson (publ)
    Inventors: Jinliang Huang, Tore Mikael André
  • Patent number: 8787436
    Abstract: A communication device is disclosed including: an analog-to-digital converter (ADC) for converting an analog input signal into a digital input signal; an equalizer module coupled with the ADC for processing the digital input signal to generate an equalized signal; a data slicer coupled with the equalizer module for generating an output signal based on the equalized signal; and a control unit coupled with the equalizer module and the data slicer; wherein the control unit or the equalizer module preserves at least one signal equalizing parameter of the equalizer module before the equalizer module enters power saving mode, and the equalizer module loads the at least one signal equalizing parameter to operate when the communication device receives a predetermined control signal.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: July 22, 2014
    Assignee: Realtek Semiconductor Corp.
    Inventors: Liang-Wei Huang, Fang-Ru Wang, Ting-Fa Yu, Chien-Sheng Lee
  • Patent number: 8787437
    Abstract: An adaptive equalizer and an adaptive equalizing method are provided. The adaptive equalizer includes an adaptive equalizing unit, for adaptively equalizing an inputted signal to output the equalized signal; a coefficient updating unit, for updating a coefficient of a filter of the adaptive equalizing unit; a switching unit, connected between the coefficient updating unit and the adaptive equalizing unit and a monitoring device, for controlling on or off of the switching unit in accordance with the fact that a down sampling phase of the inputted signal or a down sampling phase of the equalized signal is within a predetermined range. When the switching unit is on, the coefficient updating unit is capable of updating the coefficient of the adaptive equalizing unit, and when the switching unit is off, the coefficient updating unit is incapable of updating the coefficient of the adaptive equalizing unit.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: July 22, 2014
    Assignee: Fujitsu Limited
    Inventors: Ling Liu, Zhenning Tao, Takahito Tanimura
  • Patent number: 8787449
    Abstract: An adaptive loop filter utilizing separable filters within a quadtree-based adaptive loop filter (QALF). The filters for at least the P and B pictures are replaced with a separable filter to provide Separable QALF (SQALF). In a preferred embodiment the filter comprises a Wiener filter as a best fit approximation of the non-separable filter. In response to decoding with the SQALF approach, computational complexity in the decoder is reduced without lowering perceived visual quality. Estimation of the separable filter is obtained in the encoder by iteratively minimizing the sum of squares error with the separable filter. The SQALF filtering is described within a video decoder.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: July 22, 2014
    Assignee: Sony Corporation
    Inventors: Cheung Ayeung, Ali Tabatabai, Minh Do
  • Patent number: 8787861
    Abstract: In some implementations, an apparatus includes an echo canceller that generates an echo interference compensation signal that compensates for an echo interference signal in a communication signal, a crosstalk canceller that generates a crosstalk interference compensation signal that compensates for a crosstalk interference signal in the communication signal, and a combiner that generates a combined interference compensation signal based on the echo interference compensation signal and the crosstalk interference compensation signal.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: July 22, 2014
    Assignee: Marvell International Ltd.
    Inventors: Xiaopeng Chen, Runsheng He
  • Patent number: 8787438
    Abstract: A technique for a reconditioning equalizer filter for non-constant envelope signals is described. The input to a transmitter chain is modified by a reconditioning equalizer filter, prior to being applied to the transmitter. The reconditioning equalizer filter modifies and smoothens the amplitude of the signal. The modified and smoothened signal has its peaks reduced which results in lower Crest Factor. The input to the reconditioning equalizer filter could be a baseband, intermediate frequency (IF) or radio frequency (RF) signal. When the signal is an IF or RF signal, it needs to be down-converted to baseband before being applied to the reconditioning equalizer filter. The reconditioning equalizer filter could be performed in a digital or analog domain.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: July 22, 2014
    Assignee: Altera Corporation
    Inventor: Kiomars Anvari
  • Patent number: 8779847
    Abstract: System and methods are provided for signal processing. For example, an input signal is received at a finite impulse response filter circuit including a plurality of stages, where each stage of the plurality of stages is associated with a sample value of the input signal and a stage weight. An output signal is generated using the finite impulse response filter circuit, the output signal being equal to a weighted sum of the sample values of the input signal. An error signal is generated to indicate a difference between the output signal and a target. A constraint is applied to one or more of the stage weights. The stage weights are changed within the constraint to reduce a magnitude of the error signal.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: July 15, 2014
    Assignee: Marvell International Ltd.
    Inventors: Yu-Yao Chang, Jun Gao, Gregory Burd
  • Patent number: 8781043
    Abstract: Techniques for recovering a desired transmission in the presence of interfering transmissions are described. For successive equalization and cancellation (SEC), equalization is performed on a received signal to obtain an equalized signal for a first set of code channels. The first set may include all code channels for one sector, a subset of all code channels for one sector, multiple code channels for multiple sectors, etc. Data detection is then performed on the equalized signal to obtain a detected signal for the first set of code channels. A signal for the first set of code channels is reconstructed based on the detected signal. The reconstructed signal for the first set of code channels is then canceled from the received signal. Equalization, data detection, reconstruction, and cancellation are performed for at least one additional set of code channels in similar manner.
    Type: Grant
    Filed: November 15, 2006
    Date of Patent: July 15, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Byonghyo Shim, Inyup Kang, Farrokh Abrishamkar, Sharad Sambhwani
  • Patent number: 8781054
    Abstract: A semiconductor device includes a clock-and-data recovery circuit including a phase tracking loop that generates a phase difference signal indicating a phase difference between a reception clock generated from a transmission clock and an input signal and makes the reception clock track the input signal, a frequency tracking loop that performs control to make a frequency of the reception clock track a frequency of the input signal, the clock-and-data recovery circuit being configured to extract a data signal and a synchronization clock from the input signal and to control a phase and a frequency of the reception clock, a frequency error adjuster that increases or decreases a value indicated by a frequency adjustment signal according to a frequency difference signal generated based on the phase difference signal, and an oscillator that increases or decreases a frequency of the transmission clock based on the frequency adjustment signal.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: July 15, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Morishige Aoyama
  • Publication number: 20140192855
    Abstract: An adaptive equalizer capable of suppressing an increase in circuit scale and an increase in operation clock frequency. An adaptive equalizer (100) performs an adaptive equalization process on a time-region signal in a frequency region. A signal converter (200) has: a first wide-bit memory (201) capable of reading/writing a plurality of sample signals; a first register group (202) comprising a plurality of registers capable of accessing the first wide-bit memory (201); a butterfly computation unit group (204) comprising a plurality of butterfly computation units; and a first connection switching unit (203) for switching the state of connection between the plurality of registers and the plurality of butterfly computation units.
    Type: Application
    Filed: June 29, 2012
    Publication date: July 10, 2014
    Applicant: PANASONIC CORPORATION
    Inventors: Hidekuni Yomo, Akihiko Matsuoka, Atsushi Maruyama
  • Publication number: 20140192853
    Abstract: One or more aspects of the disclosure provide an efficient equalization scheme capable of mitigating multi-path interference on channels with large delay spread using short-length equalizers. That is, by dividing stored samples of a signal received on the multi-path channel by time into a plurality of clusters, a short-length equalizer can be utilized in an iterative fashion on each of the clusters, thus eliminating the need for a large length equalizer while still providing improved performance over that of a Rake receiver at large delay spreads. Other aspects, embodiments, and features are also claimed and described.
    Type: Application
    Filed: January 10, 2013
    Publication date: July 10, 2014
    Applicant: QUALCOMM Incorporated
    Inventors: Chun-Hao Hsu, Aditya Dua, Nathan Dingsai Yee, Abhinav Gupta
  • Publication number: 20140192856
    Abstract: An adaptive equalizer (100) has a signal converter (200) for performing a fast Fourier transform and/or an inverse fast Fourier transform. The signal converter (200) has: a first wide-bit memory (201) capable of reading/writing a plurality of sample signals; a first register group (202) comprising a plurality of registers capable of accessing the first wide-bit memory (201); a butterfly computation unit group (204) comprising a plurality of butterfly computation units; and a first connection switching unit (203) for switching the state of connection between the plurality of registers and the plurality of butterfly computation units.
    Type: Application
    Filed: June 29, 2012
    Publication date: July 10, 2014
    Applicant: PANASONIC CORPORATION
    Inventors: Hidekuni Yomo, Akihiko Matsuoka, Atsushi Maruyama
  • Publication number: 20140192854
    Abstract: A reception apparatus includes: a Fourier transform unit to output a converted signal; a propagation path estimation unit to calculate propagation-path-estimated-values based on pilot subcarriers; and a propagation path compensation unit, including a filter, to compensate propagation path distortion, the filter includes: first multipliers to multiply the propagation-path-estimated-values of taps other than a center tap by filtering coefficients; a first adder to add outputs of the first multipliers; a first subtractor to calculate an error between an output of the first adder and a propagation-path-estimated-value of the center tap; a filtering coefficient generation unit to generate the filtering coefficients based on the error; a second multiplier to multiply the propagation-path-estimated-value of the center tap by first coefficient; a third multiplier to multiply the output of the first adder by second coefficient; and a second adder to add an output of the second multiplier and an output of the third mul
    Type: Application
    Filed: October 16, 2013
    Publication date: July 10, 2014
    Applicant: FUJITSU LIMITED
    Inventor: Masataka UMEDA
  • Patent number: 8774261
    Abstract: A two stage interference cancellation (IC) process includes a linear IC stage that suppresses co-channel interference (CCI) and adjacent channel interference (ACI). The linear IC stage disambiguates otherwise super-trellis data for non-linear cancellation. Soft linear IC processing is driven by a-posteriori probability (Apop) information. A second stage performs expectation maximization/Baum Welch (EM-BW) processing that reduces residual ISI left over from the first stage and also generates the Apop which drives the soft linear IC in an iterative manner.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: July 8, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Farrokh Abrishamkar, Divaydeep Sikri, Ken Delgado
  • Patent number: 8774262
    Abstract: Methods, apparatuses, and systems are presented for performing adaptive equalization involving receiving a signal originating from a channel associated with inter-symbol interference, filtering the signal using a filter having a plurality of adjustable tap weights to produce a filtered signal, and adaptively updating each of the plurality of adjustable tap weights to a new value to reduce effects of inter-symbol interference, wherein each of the plurality of adjustable tap weights is adaptively updated to take into account a constraint relating to a measure of error in the filtered signal and a constraint relating to group delay associated with the filter. Each of the plurality of adjustable tap weights may be adaptively updated to drive group delay associated with the filter toward a target group delay.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: July 8, 2014
    Assignee: Vitesse Semiconductor Corporation
    Inventors: Sudeep Bhoja, John S. Wang, Hai Tao
  • Patent number: 8774322
    Abstract: The present disclosure provides a system, apparatus and method to reduce phase noise associated with a received data signal, while optimizing system performance. An optimal length of a digital filter, employed in a carrier phase recovery process, is determined such that phase noise is reduced in the received data signal. Reduction of the phase noise present in the received data signal leads to improved receiver performance. The optimal length of the digital filter may be continuously performed, resulting in optimal performance of the receiver.
    Type: Grant
    Filed: October 11, 2010
    Date of Patent: July 8, 2014
    Assignee: Infinera Corporation
    Inventor: Gilad Goldfarb
  • Patent number: 8774286
    Abstract: A receiving apparatus includes a buffer configured to store packets of a first packet sequence made up of packets extracted from one transport stream that are common to packets of another transport stream and packets of a second packet sequence made up of common packets, a read control section configured to read the packets of the first packet sequence and the second packet sequence stored in the buffer after the passing of a predetermined time after synchronization is established between the packets of the first packet sequence and the packets of the second packet sequence, thereby reconstructing one transport stream from the first packet sequence and the second packet sequence, and an output section configured to output the reconstructed transport stream.
    Type: Grant
    Filed: August 6, 2010
    Date of Patent: July 8, 2014
    Assignee: Sony Corporation
    Inventors: Takashi Yokokawa, Satoshi Okada
  • Publication number: 20140185661
    Abstract: The present invention provides GPA embodiments. In some embodiments, a GPA stage with a negative capacitance unit is provided.
    Type: Application
    Filed: December 27, 2012
    Publication date: July 3, 2014
    Inventors: Kevin Chang, Stefano Giaconi
  • Publication number: 20140185662
    Abstract: Logic may comprise a single phase tracking implementation for all bandwidths of operation and the logic may adaptively change pre-defined and stored track parameters if the receiving packet is 1 MHz bandwidth. Logic may detect a packet and long training fields before performing a 1 MHz classification. Logic may auto-detect 1 MHz bandwidth transmissions by a property of the long training field sequences. Logic may auto-detect 1 MHz bandwidth transmissions by detecting a Binary Phase Shift Keying (BPSK) modulated first signal field symbol rather than the Quadrature Binary Phase Shift Keying (QBPSK) associated with the 2 MHz or greater bandwidth transmissions. Logic may perform an algorithm to determine an estimated phase correction value for a given orthogonal frequency division multiplexing symbol and several embodiments integrate this value with an intercept multiplier that may be 0.2 for 1 MHz transmissions and, e.g., 0.5 for 2 MHz or greater bandwidth communication.
    Type: Application
    Filed: December 29, 2012
    Publication date: July 3, 2014
    Inventors: Shahrnaz Azizi, Eldad Perahia, Thomas J. Kenney
  • Patent number: 8767870
    Abstract: Embodiments of the present invention provide a variable inter symbol interference generator that generates a data signal having a variable amount of inter symbol interference by passing a data signal through (1) a programmable filter having an adjustable frequency response, and through (2) a fixed filter having a fixed frequency response such as a PCB trace, a length of cable, a discrete filter, or the like. By adjusting the parameters and therefore the insertion gain or loss of the programmable filter, and combining this with one or more fixed filters, a large range of continuously variable and finely tunable inter symbol interference amounts can be easily generated.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: July 1, 2014
    Assignee: Tektronix, Inc.
    Inventors: James R. Waschura, Senthil Kumar Thandapani, Timothy E. Sauerwein
  • Patent number: 8767881
    Abstract: A signal processing apparatus is disclosed which includes: a detection section configured such that based on a result of the error correction of a signal generated by a single carrier system, the detection section detects the presence or absence of spectrum inversion in the signal; and a selection section configured such that if the detection section detects the spectrum inversion, the selection section selects the spectrally inverted signal as the signal subject to the error correction, and that if the detection section does not detect the spectrum inversion, then the selection selects the spectrally uninverted signal as the signal subject to the error correction.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: July 1, 2014
    Assignee: Sony Corporation
    Inventors: Takashi Yokokawa, Ryoji Ikegaya, Yuji Shinohara
  • Patent number: 8767811
    Abstract: An apparatus having a transmitter is disclosed. The transmitter generally has a filter coupled to a communication channel. The transmitter may be configured to adjust the filter using information based on an estimate of one or more characteristics of the communication channel.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: July 1, 2014
    Assignee: LSI Corporation
    Inventor: Lizhi Zhong
  • Patent number: 8767812
    Abstract: Various systems and methods are described for performing fractionally spaced time domain equalization (TEQ). One embodiment is a method implemented in a communication system for training a fractionally spaced time domain equalizer (TEQ). The method comprises performing an initialization phase, averaging a received signal in the system to reduce effects of noise in a channel, determining a channel estimate, and aligning an ideal reference signal with the received signal. The method further comprises updating a target response filter according to a non-integer multiple of a base sampling rate, determining an adaptation error based on useful information both inside and outside a Nyquist band of the TEQ, and updating the TEQ according to the adaptation error.
    Type: Grant
    Filed: April 7, 2011
    Date of Patent: July 1, 2014
    Assignee: Ikanos Communications, Inc.
    Inventors: Lin Lin Li, Amitkumar Mahadevan
  • Patent number: 8767813
    Abstract: A circuit comprises an analog to digital converter (ADC) that samples a received signal based on a sampling clock. A feed forward filter communicates with the ADC and does not remove first precursor intersymbol interference from the received signal. An adaptive timing loop circuit that adjusts a timing phase of the sampling clock of said ADC to remove the first precursor intersymbol interference from the received signal. The adaptive timing loop circuit adjusts the timing phase based on at least one of an estimate signal and a loop gain control constant.
    Type: Grant
    Filed: January 23, 2007
    Date of Patent: July 1, 2014
    Assignee: Marvell International Ltd.
    Inventor: Runsheng He
  • Publication number: 20140177620
    Abstract: A demodulator can include an ingress exciser configured to remove ingress noise from a burst mode digital input signal that is above a predetermined threshold and resides within a narrowband. An adaptive equalizer can be configured to adaptively equalize an estimate of the signal provided from the ingress exciser and to provide an adaptively equalized signal. An ingress predictor can be configured to subtract an estimate of remaining predicted ingress noise from the adaptively equalized signal to provide a resultant signal that is substantially free of the ingress noise.
    Type: Application
    Filed: December 20, 2012
    Publication date: June 26, 2014
    Applicant: CISCO TECHNOLOGY, INC.
    Inventors: LEO MONTREUIL, RICK MELLER
  • Publication number: 20140177696
    Abstract: A receiver circuit includes a first differential amplification unit including a variable load section, and configured to receive first and second input signals, and to generate first and second output signals, which are amplified based on an impedance value of the variable load section and a voltage difference between the first and second input signals, a second differential amplification unit configured to receive the first and second output signals and to generate a third output signal based on a voltage difference between the first and second output signals, and a signal generating unit configured to generate an equalization signal for controlling the variable load section based on the third output signal.
    Type: Application
    Filed: March 15, 2013
    Publication date: June 26, 2014
    Applicant: SK hynix Inc.
    Inventor: Tae-Jin HWANG
  • Patent number: 8761328
    Abstract: An update algorithm for equalizer coefficients in a communications system using phase correction symbols. Instead of using a traditional all symbols slicer update algorithm, the equalizer is updated during phase correction symbols for optimal performance in low signal-to-noise ratio conditions. In lower signal-to-noise ratio conditions, the equalizer uses a phase correction circuit to compensate for distortion caused by a communication channel when a demodulated data stream contains an unknown phase offsets resulting from a fast dynamic distortion. More specifically, the phase correction circuit uses a phase correction signal to correct for the unknown phase offsets in a demodulated data stream in lower signal-to-noise ratio conditions. The equalizer then corrects for distortion caused by the communication channel based upon the phase corrected demodulated data stream.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: June 24, 2014
    Assignee: Broadcom Corporation
    Inventors: Tommy Yu, Amy Gayle Hundhausen
  • Patent number: 8761238
    Abstract: A method and an apparatus for correcting a frequency offset are provided. The method includes: receiving n channels of first signals; performing frequency offset correction processing on the n channels of first signals to obtain n channels of first corrected signals; acquiring n center tap coefficients of a space time equalizer, n first output phases of a phase-locked loop phase detector, and a second output phase of a phase-locked loop phase detector; acquiring n first estimated frequency offset values according to the n center tap coefficients and the n first output phases; acquiring a second estimated frequency offset value according to the second output phase; and receiving n channels of second signals, and performing frequency offset correction on the n channels of second signals according to the n first estimated frequency offset values and the second estimated frequency offset value.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: June 24, 2014
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Rui Lv
  • Publication number: 20140169435
    Abstract: A duty cycle correcting device is provided which includes a pulse width adjusting unit which adjusts a pulse width of an input signal according to a pulse width control code; a comparison unit which compares an output signal of the pulse width control unit with a plurality of reference voltages; and a control unit which selects one of a plurality of pulse width control codes based on comparison data from the comparison unit and provides the selected pulse width control code to the pulse width adjusting unit.
    Type: Application
    Filed: February 15, 2013
    Publication date: June 19, 2014
    Applicant: Industry-Academic Cooperation Foundation, Yonsei University
    Inventor: Industry-Academic Cooperation Foundation, Yonsei University
  • Publication number: 20140169437
    Abstract: A method for modulating data for transmission within a communication system. The method includes establishing a time-frequency shifting matrix of dimension N×N, wherein N is greater than one. The method further includes combining the time-frequency shifting matrix with a data frame to provide an intermediate data frame. A transformed data matrix is provided by permuting elements of the intermediate data frame. A modulated signal is generated in accordance with elements of the transformed data matrix.
    Type: Application
    Filed: June 25, 2013
    Publication date: June 19, 2014
    Applicant: COHERE TECHNOLOGIES, INC.
    Inventors: Ronny Hadani, Salim Shlomo Rakib
  • Publication number: 20140169442
    Abstract: A clock data recovery method includes: integrating an input data signal over a number of cycles of a sample clock to generate an integrated signal; performing a digital process on the integrated signal to output a first digital signal; interpolating the first digital signal in accordance with phase information to generate interpolation data; outputting phase difference data indicating a difference in phase of the interpolation data from the sample clock; performing a filtering process on the phase difference data to generate the phase information; performing an equalization process on the interpolation data in accordance with output data; and performing a binary decision on results of the equalization process to generate the output data.
    Type: Application
    Filed: September 20, 2013
    Publication date: June 19, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Takushi HASHIDA, Hirotaka Tamura