Abstract: Technologies for signaling compression inside a partially unrolled decision feedback equalizer (DFE) are described. The signaling compression associated with partially unrolled DFE results in multiplexers selecting a 1-bit output value from one of two 1-bit input values, which are decoding the actual multi-bit candidate levels and transforming the selected 1-bit output value to a multi-bit sliced value by adding to it a pointer value of a pulse-amplitude modulation (PAM) level. The signaling compression reduces the power and area of an N-tap DFE, where N is a positive integer.

Abstract: Systems, methods, and apparatuses for providing optimization of network resources. The system is operable to monitor the electromagnetic environment, analyze the electromagnetic environment, and extract environmental awareness of the electromagnetic environment. The system extracts the environmental awareness of the electromagnetic environment by including customer goals. The system is operable to use the environmental awareness with the customer goals and/or user defined policies and rules to extract actionable information to help the customer optimize the network resources.

Abstract: Provided are an interference cancellation repeater capable of selecting one of a plurality of adaptive filters based on a synchronization signal and canceling interference included in a received signal using the selected adaptive filter and a method of operation thereof.

Abstract: An Automatic Gain Control (AGC) SERDES circuit may be used to provide improved gain control for SERDES operation. This AGC SERDES circuit uses an initial gain convergence to determine and store an initial gain level. Once the initial gain convergence is complete, the AGC SERDES circuit uses a signal peak tracking to reduce or prevent saturation events. By setting the gain target based on tracked changes in the equalizer coefficients, the AGC SERDES circuit adapts the gain target to reduce or prevent saturation events and provide the improved communication throughput. A SERDES receiver circuit also provides improved performance using an improved convergence flow within its subcomponent blocks. The improved convergence flow also provides the ability to track environmental changes, voltage changes, and changes to input parameters, and can be performed while data is running on the link to provide continuously improved communication channel performance.

Abstract: Methods, systems, and devices for techniques for time-variable decision feedback equalization are described. A memory device may be coupled with a host device using one or more conductive lines. A receiver may receive a signal transmitted from another device over a conductive line. The receiver may include a decision circuit used to determine voltages of the received signal based on the received signal and a feedback signal and output an output signal. The receiver may include a variable time-delay circuit configured to output delayed signals that are delayed versions of the output signal and a gain circuit that is configured to scale the delayed signals to generate the feedback signal. The variable time-delay circuit may include delay elements having variable delay parameters. The receiver may be coupled with a memory array that stores the information conveyed by the output signal.

Abstract: Systems, methods, and apparatuses for providing optimization of network resources. The system is operable to monitor the electromagnetic environment, analyze the electromagnetic environment, and extract environmental awareness of the electromagnetic environment. The system extracts the environmental awareness of the electromagnetic environment by including customer goals. The system is operable to use the environmental awareness with the customer goals and/or user defined policies and rules to extract actionable information to help the customer optimize the network resources.

Abstract: Devices and methods for operating a low-power memory device includes a first data input (DQ) circuitry including an input buffer configured to generate a loopback data signal based at least in part on a data signal received at the first DQ circuitry when the low-power memory device operates in a feedback mode. A second DQ circuitry includes an output buffer configured to receive the loopback data signal from the first DQ circuitry and to output the loopback data signal via a data pin.

Abstract: The disclosure provides a signaling link that overcomes or at least reduces the limitations of RC-dominated signaling wires, improving both the bandwidth and the power consumption of signaling circuits. Both an AC and a DC signaling link are disclosed. In one example, a signaling link is provided that includes: (1) a transmitter including a passive equalizer, (2) an over-terminated receiver, and (3) a lossy channel having a first end connected to the passive equalizer and a second end connected to the receiver, wherein the lossy channel has a channel characteristic impedance that is lower than a terminating impedance of the passive equalizer and a termination impedance of the receiver.

Abstract: A test and measurement device includes an input configured to receive an analog signal from a Device Under Test (DUT), an Analog to Digital Converter (ADC) coupled to the input and structured to convert the analog signal to a digital signal, a receiver implemented in a first Field Programmable Gate Array (FPGA) and structured to accept the digital signal and perform signal analysis on the digital signal, a transmitter implemented in a second FPGA and structured to generate a digital output signal, and a Digital to Analog Converter (DAC) coupled to the transmitter and structured to convert the digital output signal from the transmitter to an analog signal, and structured to send the analog signal to the DUT. The receiver and the transmitter are coupled together by a high speed data link over which data about the current testing environment may be shared.

Abstract: Embodiments included herein are directed towards sampling circuits and methods of using the same. Embodiments may include a data sense amplifier circuit and a reference sense amplifier circuit directly connected with the data sense amplifier circuit. Embodiments may further include a latch circuit configured to receive a first input from the data sense amplifier circuit and a second input from the reference sense amplifier circuit. The latch circuit may be further configured to generate a least significant bit output based upon, at least in part, the first input and the second input.

Abstract: A decision feedback equalizer including: a first input latch configured to generate a first output signal from first data received by the first input latch, wherein the first input latch includes: a first sub-circuit configured to receive the first data and a reference voltage, compare the first data and the reference voltage, and generate first internal signals having different transition timings according to a result of the comparison between the first data and the reference voltage; and a second sub-circuit configured to receive, as first feedback, a second output signal, which corresponds to second data received by the first latch earlier than the first data, and generate the first output signal, which compensates for a difference between the transition timings of the first internal signals, based on the first feedback.

Abstract: A pulse width modulation (PWM) system includes a PWM circuit and a controller. The PWM circuit includes a counter, a period register, and a duty cycle register. The controller is coupled to the PWM circuit. The controller is configured to calculate a period value and a duty cycle value. The controller is also configured to load the duty cycle value into the duty cycle register responsive to a count value of the counter being equal to a value of the duty cycle register and the duty cycle value being less than the period value.

Abstract: An error detection and correction device includes a decision-feedback equalizer (DFE), a decision circuit, an error detection circuit, and an error correction circuit. The DFE equalizes a data signal to generate a first equalized signal. The decision circuit performs hard decision upon the first equalized signal to generate a symbol decision signal. The error detection circuit performs forward error detection at symbol positions of consecutive symbols included in the symbol decision signal to detect a head position of suspicious error that affects at least one symbol in the symbol decision signal. The error correction circuit performs error correction upon the symbol decision signal in response to the head position of the suspicious error that is detected by the error detection circuit.

Abstract: The present disclosure discloses a decision feedback equalizer and a method for acquiring and correcting data. The decision equalizer comprises: a first decision sampling circuit; and a second decision sampling circuit; wherein an input end of the first decision sampling circuit is configured to receive sampling data and a first sampling result outputted by the second decision sampling circuit in a previous sampling period; and an input end of the second decision sampling circuit is configured to receive sampling data and a second sampling result outputted by the first decision sampling circuit in a previous sampling period.

Abstract: Disclosed are a clock and data recovery circuit, method and apparatus. The circuit comprises a receiving module for receiving an analog signal; a first equalization module connected to the receiving module, the first equalization module comprising a first totalizer and a second totalizer; a first sampling module connected to an output end of the first totalizer, the first sampling module comprising a first edge sampler and a second edge sampler that are connected to the output end of the first totalizer, respectively; a second sampling module connected to an output end of the second totalizer; a data processing module connected to both the first sampling module and the second sampling module; a clock recovery module connected to the data processing module; and an output module connected to the clock recovery module. In the present application, by means of the manner, a phase can be adjusted using a bias voltage, thereby accurately recovering clock information.

Abstract: An image coding method includes selecting two or more transform components from among a plurality of transform components that include a translation component and non-translation components, the two or more transform components serving as reference information that represents a reference destination of a current block; coding selection information that identifies the two or more transform components that have been selected from among the plurality of transform components; and coding the reference information of the current block by using reference information of a coded block different from the current block.

Abstract: Various embodiments described herein provide for data communications using decision feedback equalization (DFE) for electro-magnetic interference (EMI) cancellation in a received signal, such as a signal received over a data communication medium and at a receiver of a communication system. In particular, some embodiments use a DFE and a feed-forward equalizer (FFE) to equalize a signal received by a first physical layer device from a second physical layer device over a data communication medium, and to operate as a narrowband notch filter to cancel EMI from the received signal.

Abstract: Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. A first PAM-4 DFE architecture has low latency from the output of the samplers to the application of the first DFE tap feedback to the input signal. This is accomplished by not decoding the sampler outputs in order to generate the feedback signal for the first DFE tap. Rather, weighted versions of the raw sampler outputs are applied directly to the input signal without further analog or digital processing. Additional PAM-4 DFE architectures use the current symbol in addition to previous symbol(s) to determine the DFE feedback signal. Another architecture transmits PAM-4 signaling using non-uniform pre-emphasis. The non-uniform pre-emphasis allows a speculative DFE receiver to resolve the transmitted PAM-4 signals with fewer comparators/samplers.

Abstract: An optimized pulse shaping clock data recovery system is provided that includes a slicer configured to receive a signal and provide an initial set of tentative decisions to a decision feedforward equalizer, where the decision feedforward equalizer provides a fully equalized output signal. The slicer may be incorporated as part of decision feedback equalizer to provide better quality tentative decisions. The clock data recovery system also receives the first output signal that is partially equalized in such a way as to optimally shape it for a clock to sample it at an ideal location by providing an adjustment signal to the analog to digital controller.

Abstract: Embodiments of equalizers are disclosed. In an embodiment, an equalizer includes a first signal path segment that includes a first plurality of serially connected transistors and current sources, a second signal path segment that includes a second plurality of serially connected transistors and current sources, and at least one termination resistor connected to the first and second signal path segments. The first plurality of serially connected transistors and current sources includes a first current source and a second current source connectable to a reference voltage and a first transistor and a second transistor connected between input terminals of the equalizer and the first and second current sources, where the first signal path segment further includes at least one resistor connected between the first and second current sources.

Abstract: A receiver utilizes loop-unrolled decision feedback equalization (DFE). For each sample, two comparators, each configured with different thresholds, sample an input signal. The output of one of these comparators is selected and used as the output of the receiver and may be optionally input to additional DFE circuitry. The output of the other (non-selected) comparator is used to adjust an input offset voltage of that same comparator. Adjustments to the offset voltages of the comparators may be based on a statistical analysis of the respective outputs of the two comparators when not selected. Adjustments to the offset voltages of the comparators may be based on comparisons between the respective outputs of the two comparators when not selected to the outputs of a reference comparator that has been calibrated for minimal or zero offset.

Abstract: This disclosure provides channel estimation methods and apparatuses. One method includes: determining Ps initial sample channel matrices that indicate channel states, where the Ps initial sample channel matrices include P1 first sample channel matrices and Ps-P1 second sample channel matrices, the P1 first sample channel matrices are determined based on a previous sample channel matrix or a given reference signal, and Ps is an integer greater than 1; and determining a channel matrix based on the Ps initial sample channel matrices, and obtaining a channel estimation result. Because the P1 initial sample channel matrices in the Ps initial sample channel matrices are determined based on the previous sample channel matrix or the given reference signal, an initial channel estimation result may be provided as an iterative initial sample channel matrix.

Abstract: Methods in an optical receiver, for decoding a received M-level pulse-amplitude-modulated, PAM-M, optical signal. An example method comprises, for a first interval, decoding (510) the received PAM-M optical signal using a standard PAM-M decoder with M-1 thresholds, using first sampling times, to obtain a first set of decoded bits, and decoding (520) the received PAM-M optical signal using a duobinary decoder with 2M-2 thresholds, at second sampling times offset from the first sampling times, to obtain second set of decoded bits. The method further comprises calculating (530) first and second error metrics corresponding to the first and second sets of decoded bits, respectively, and selecting (540) the standard PAM-M decoder or the duobinary decoder for subsequent decoding of the received PAM-M optical signal, based on the first and second error metrics.

Abstract: An apparatus and method for providing a decision feedback equalizer are disclosed herein. In some embodiments, a method and apparatus for reduction of inter-symbol interference (ISI) caused by communication channel impairments is disclosed. In some embodiments, a decision feedback equalizer includes a plurality of delay latches connected in series, a slicer circuit configured to receive an input signal from a communication channel and delayed feedback signals from the plurality of delay latches and determine a logical state of the received input signal, wherein the slicer circuit further comprises a dynamic threshold voltage calibration circuit configured to regulate a current flow between output nodes of the slicer circuit and ground based on the received delayed feedback signal and impulse response coefficients of the communication channel.

Abstract: A receiver receives communications over a communication channel, which may distort an incoming communication signal. In order to counter this distortion, the frequency response of the receiver is manipulated by adjusting several parameters. Each parameter controls at least a portion of the frequency response of the receiver. The optimal values for the parameters are determined by modifying an initial set of values for the parameters through one or more stochastic hill climbing operations until a performance metric associated with the receiver reaches a local optimum. The modified values are displaced through one or more mutation operations. The stochastic hill climbing operations may subsequently be performed on the mutated values to generate the final values for the parameters.

Abstract: A receiver includes an analog-to-digital converter (ADC) to generate a digital output, including a set of bits corresponding to a received signal. The receiver further includes a calculator circuit coupled to the ADC, the calculator circuit to calculate a set of tap coefficient gradient values corresponding to the digital output, generate a first feedback signal corresponding to the set of tap coefficient gradient values, and generate a second feedback signal corresponding to the set of tap coefficient gradient values. The receiver further includes a clock data recovery (CDR) circuit, coupled to the calculator circuit, the CDR circuit to detect a first parameter of the received signal based on the first feedback signal.

Abstract: An input stage of a comparator includes a first transistor, wherein a gate of the first transistor is coupled to a first input of the input stage, a second transistor, wherein a gate of the second transistor is coupled to a second input of the input stage, a third transistor coupled in series with the first transistor, and a fourth transistor coupled in series with the second transistor. The input stage also includes a fifth transistor, wherein a gate of the fifth transistor is configured to receive a first decision feedback signal, and a drain of the fifth transistor is coupled to a gate of the third transistor. The input stage further includes a sixth transistor, wherein a gate of the sixth transistor is configured to receive a second decision feedback signal, and a drain of the sixth transistor is coupled to a gate of the fourth transistor.

Abstract: Methods and systems are described for generating two comparator outputs by comparing a received signal to a first threshold and a second threshold according to a sampling clock, the first and second thresholds determined by an estimated amount of inter-symbol interference on a multi-wire bus, selecting one of the two comparator outputs as a data decision, the selection based on at least one prior data decision, and selecting one of the two comparator outputs as a phase-error decision, the phase error decision selected in response to identification of a predetermined data decision pattern.

Abstract: Various embodiments provide for identifying and training a floating tap for decision feedback equalization. For some embodiments, the identification and training of the floating tap described herein can be part of a circuit for receiver block of a system, such as a memory system.

Abstract: A latch circuit and an equalizer including the same are provided. The equalizer includes: an even data path configured to receive a reception data signal and including a first summing circuit and a first latch circuit; and an odd data path configured to receive the reception data signal and including a second summing circuit and a second latch circuit. An even data signal output from the first latch circuit is configured to be input to the second summing circuit, and an odd data signal output from the second latch circuit is configured to be input to the first summing circuit. Each of the first latch circuit and the second latch circuit includes a latch and a multiplexer.

Abstract: A communication system provides reliable wideband communications with reduced power consumption in a user equipment (UE) receiver. A UE may include receiver circuitry to receive a radio frequency (RF) signal from a wireless network and output an analog baseband signal. The RF signal includes M copies of a duplicated signal in a frequency domain. The analog baseband signal includes the M copies of the duplicated signal uniformly offset from one another in the frequency domain by a bandwidth F and including a gap between adjacent copies. The UE further includes an anti-aliasing analog filter an analog to digital converter (ADC). The ADC samples an output of the anti-aliasing analog filter at a sampling frequency selected to obtain a digital baseband signal comprising a combined digital copy of the M copies of the duplicated signal folded over each other.

Abstract: This application provides a narrowband interference isolation method and a communication apparatus. An example method includes: determining a parameter of a narrowband interference signal; determining a coefficient of a first filter based on the parameter of the narrowband interference signal, wherein the first filter is located at a receive end of a master communication device, and the coefficient of the first filter is for filtering out the narrowband interference signal; and sending the parameter of the narrowband interference signal or the coefficient of the first filter to M slave communication devices using an Ethernet operation, administration, and maintenance (OAM) frame, wherein the master communication device is connected to the M slave communication devices, M?1, and M is an integer.

Abstract: Methods and apparatuses are disclosed for wireless device (WD)-autonomous physical downlink shared channel (PDSCH) receiver (RX) antenna adaptation. In one embodiment, a method implemented in a WD includes one or more of: estimating an expected number of multiple-input multiple-output (MIMO) layers based at least in part on channel state information (CSI) and/or a sounding reference signal (SRS) configuration; determining a set of antennas of a plurality of antennas to use based at least in part on the estimated expected number of MIMO layers; and/or receiving a MIMO signal using the determined set of antennas. In one embodiment, a method implemented in a network node include receiving a channel state information (CSI) report from the WD; and/or scheduling and/or transmitting a downlink (DL) channel to the WD using a number of multiple-input multiple-output (MIMO) layers, the number of MIMO layers used based at least in part on the received CSI report.

Abstract: An apparatus includes a sensor module configured for receiving sensed information indicative of a sensed signal. The sensed signal includes a source signal component and a source noise component. The apparatus also includes a reference module configured for reference information indicative of a reference signal. The reference signal also includes a reference noise component. The apparatus also includes a filter module configured as a fixed lag Kalman smoother. The filter module is configured for adaptively filtering the reference signal to generate an estimate of the source noise component. The apparatus also includes a processing module configured for calculating an output signal based on the sensed signal and the estimate of the source noise component. The apparatus also includes an interface module configured for transmitting an indication of the output signal. The filter module is further configured for, based on the output signal, tuning the Kalman smoother.

Abstract: A method for detecting transmitted data in a multiple-input multiple-output (MIMO) receiver, the method comprising: iteratively calculating symbol estimates by: obtaining input symbol estimates and input symbol variances; calculating error values for the input symbol estimates; refining the input symbol estimates to obtain refined symbol estimates, based on the error values, wherein the refined symbol estimates are used as input symbol estimates for the subsequent iteration of the above calculation, and wherein the refined symbol estimates are used as final symbol estimates when the difference between refined symbol estimates from one iteration to the next is below a threshold change.

Abstract: An error sampler circuit includes a differential input voltage input, a differential reference voltage input, a master latch circuit, and a slave latch circuit. The master latch circuit includes a slicer circuit. The slicer circuit includes a first input, a second input, and a differential output. The first input is coupled to the differential input voltage input. The second input is coupled to the differential reference voltage input. The slave latch includes a differential input coupled to the differential output of the slicer circuit.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may determine an actual power delay profile (PDP) associated with a channel between the UE and a base station, wherein the actual PDP indicates an averaged power level of the channel over a period of time. The UE may determine whether a channel estimation mode switching event is satisfied. The UE may switch, based at least in part on the channel estimation mode switching event being satisfied, between a first channel estimation mode based at least in part on the actual PDP and a second channel estimation mode based at least in part on a template PDP. Numerous other aspects are described.

Abstract: A switching network for effecting point-to-point communication between nodes has a time-varying switching configuration, which causes successive activation and deactivation of multiple channels of the switching network, a first of the channels connecting, when activated, a transmitter node and a first receiver node, and a second of the channels connecting, when activated, the transmitter node and a second receiver node.

Abstract: Disclosed embodiments include a decision feedback equalizer (DFE) comprising an N-bit parallel input adapted to be coupled to a communication channel and configured to receive consecutive communication symbols, a first DFE path including a first path input configured to receive communication symbols, and a first adder having a first adder input coupled to the first path input. There is a first DFE filter having outputs responsive to the first DFE filter inputs, the outputs coupled to the second adder input. The DFE includes a first path having a first slicer and a first multiplexer, a first path multiplexer output, and a second DFE path including a second path input configured to receive a second communication symbol, a second adder, a second DFE filter, a second slicer, and a second multiplexer.

Abstract: An electronic-system for implementing decision-feedback equalization (DFE) includes a first stage including a first-amplifier. The first amplifier including an in-built adder circuit. The first amplifier being configured to charge one or more output nodes of the first amplifier to a first voltage using a summed signal based on input data and a feedback signal in response to a first-clock variation, wherein the feedback signal is a partially-regenerated analog output from a regenerating amplifier. A second stage is includes a second amplifier configured as the regenerating amplifier and connected to the one or more output nodes of the first amplifier, the second amplifier configured to amplify charged output nodes of the second stage to a second voltage in response to a second-clock variation and apply a regenerative gain to the amplified second-voltage during the second-clock variation to generate the partially-regenerated analog output.

Abstract: Provided are a summing circuit and an equalizer including the summing circuit. The summing circuit includes: a reference signal generator generating a first reference signal and a second reference signal, based on a coefficient code; a first non-overlap clock buffer generating a first switching signal and a second switching signal by using the first reference signal; and a first current source receiving the first switching signal and the second switching signal generated by the first non-overlap clock buffer, generating a first output current by using a bias voltage, and outputting the first output current to an output line, wherein the first switching signal includes a switching signal and a complementary switching signal that is a complementary signal to the switching signal, and wherein a logic low period of the second switching signal is included in a logic high period of the complementary switching signal of the first switching signal.

Abstract: A memory device may include a first data line driver circuit that generates a first reference voltage set based on a first code and a second code associated with a first data line, and determines bit values of the first input data received through the first data line, based on the first reference voltage set. A second data line driver circuit may similarly generate a second reference voltage set. The reference voltages may have levels based on a decision feedback equalization (DFE) technique to reduce bit errors otherwise caused by inter symbol interference.

Abstract: An information handling system includes a first component including a transmitter for a high-speed serial data interface, and a second component including a receiver for the high-speed serial data interface. The receiver includes an equalization stage and a decision feedback equalization (DFE) stage. The equalization stage has an input to configure the equalization stage in one of a first low equalization state and a first high equalization state. The DFE stage has a plurality of tap inputs. The first component provides a plurality of training runs on the high-speed serial data interface.

Abstract: Embodiments provide a data sampling circuit and a data sampling device. The sampling circuit includes: a first sampling module configured to respond to a signal from a data signal terminal and a signal from a reference signal terminal and to act on a first node and a second node; a second sampling module configured to respond to a signal from the first node and a signal from the second node and to act on a third node and a fourth node; a latch module configured to input a high level signal to a first output terminal and input a low level signal to a second output terminal or input the low level signal to the first output terminal and input the high level signal to the second output terminal according to a signal from the third node and a signal from the fourth node; and a decision feedback equalization module.

Abstract: Disclosed herein are a signal receiving apparatus capable of improving signal compensation performance and a signal processing method thereof. The signal receiving apparatus includes a terminal configured to receive a signal from an external device; and an equalizer configured to reduce inter-symbol interference of the signal received through the terminal. A swing level of an output signal output from the equalizer is maintained in a preset range.

Abstract: An electronic device includes a dock dividing circuit configured to generate sampling clocks, alignment clocks and output clocks by dividing a frequency of a write clock; and a data alignment circuit configured to, in a first operation mode, receive input data having any one level among a first level to a fourth level and generate alignment data by aligning the input data in synchronization with the sampling clocks, the alignment clocks and the output clocks, and to, in a second operation mode, receive the input data having any one level of the first level and the fourth level and generate the alignment data by aligning the input data in synchronization with the sampling clocks, the alignment clocks and the output clocks.

Abstract: Example systems, read channel circuits, data storage devices, and methods to provide signal correction based on soft information in a read channel are described. The read channel circuit includes a soft output detector, such as a soft output Viterbi algorithm (SOVA) detector, and a signal correction circuit. The soft output detector passes detected data bits and corresponding soft information to the signal correction circuit. The signal correction circuit uses the soft information to determine a signal correction value, which is combined with input signal to return a corrected signal to the soft output detector for a next iteration. In some configurations, the signal correction value may compensate for DC offset, AC coupling poles, and/or signal asymmetries to reduce baseline wander in the read channel.

Abstract: Methods and systems are described for receiving a plurality of signals corresponding to symbols of a codeword on a plurality of wires of a multi-wire bus, and responsively generating a plurality of sub-channel outputs using a plurality of multi-input comparators (MICs) connected to the plurality of wires of the multi-wire bus, generating a plurality of wire-specific skew control signals, each wire-specific skew control signal of the plurality of wire-specific skew control signals generated by combining (i) one or more sub-channel specific skew measurement signals associated with corresponding sub-channel outputs undergoing a transition and (ii) a corresponding wire-specific transition delta, and providing the plurality of wire-specific skew control signals to respective wire-skew control elements to adjust wire-specific skew.

Abstract: An apparatus includes an equalization circuit, an error prediction circuit, a sequence estimation circuit, and a selection circuit. The equalization circuit is configured to generate a first data sequence and a first equalized signal from an input signal received through a channel. The error prediction circuit is configured to predict an error based on the first equalized signal when the error is predicted. When the error is predicted, the sequence estimation circuit is configured to generate a second data sequence from the first data sequence and the predicted error. The selection circuit is configured to output the second data sequence when the predicted error is determined to be an actual error and to otherwise output the first data sequence.

Abstract: Selection of equalization coefficients to configure a communications link between a receiver in a host system and a transmitter in an optical or electrical communication module is performed by a management entity with access to management registers in the receiver and transmitter. Continuous modification of the selected equalization coefficients is enabled on the communications link after the communications link is established to handle varying operating conditions such as temperature and humidity.