Abstract: A regenerating apparatus includes an identification circuit, an error correcting circuit, an abnormality detecting circuit which generates an alarm when a predetermined abnormal operation is detected, a threshold value adjusting circuit which adjusts the threshold value to make a first error correction number equal to a second error correction number when the alarm is not generated, and a threshold value initializing circuit which sets the threshold value to an initial threshold value when the alarm is generated.

Abstract: A receiver with baseline wander compensation is applicable to a digital communication system. The receiver includes an Analog-to-Digital Converter (ADC), a slicer, a threshold value detector, a gain controller, a baseline wander compensator, a delay circuit, an analog gain stage, and a digital gain stage. The baseline wander compensator is used to perform an operation and a filtering process on a voltage obtained prior to processing by the slicer and a voltage after the processing so as to obtain a baseline wander voltage value for compensation and control. The threshold value detector and the gain controller dynamically produce control signals of analog gain and digital gain. The analog gain stage compensates degrading of communication signals passing through transmission channels in an analog gain manner. The delay circuit is used to compensate the delay of the conversion performed by the ADC. The digital gain stage compensates insufficiency of the analog gain.

Abstract: A serial data receiving apparatus includes a transistor, a resistor, and a diode, converts input data of an RS232 standard to data of a TTL/CMOS standard.

Abstract: A receiving apparatus which suppresses threshold-voltage changes. A peak voltage detection block detects the peak voltage of a signal. A bottom voltage detection block detects the bottom voltage of the signal. A stop control block generates a stop signal for stopping the operations to detect the peak voltage and the bottom voltage. A threshold value specification block specifies a threshold voltage derived from the peak voltage and the bottom voltage. When receiving the stop signal, the peak voltage detection block stops the operation to detect the peak voltage and retains the peak voltage detected before the reception of the stop signal while the same signal is being received. When receiving the stop signal, the bottom voltage detection block stops the operation to detect the bottom voltage and retains the bottom voltage detected before the reception of the stop signal while the same signal is being received.

Abstract: In an over-sampled maximum-likelihood sequence estimation (MLSE) receiver system, the optimal sample spacing is determined for a variety of conditions. In an illustrative implementation, the system includes an optical filter for tightly filtering an incoming optical data signal with an on-off-keying (OOK) non-return-to-zero (NRZ) format, followed by an optical-to-electrical converter, an electrical filter, a sampler, and a MLSE receiver. The sampler samples the filtered electrical data signal twice each bit period with unequal sample spacings. For wide optical filtering bandwidths, the optimal sample spacing occurs at less than 50% of a bit period. For narrow bandwidths, the optimal sample instances occur closer to the maximum eye opening.

Abstract: A receiver for high bitrate binary signals contains a soft decision circuit with three parallel deciders coupled to a 2:1 multiplexer. The three deciders have different threshold values and generate four potential states. The 2:1 multiplexer translates the four different states into a restored data signal and a reliability signal indicating the decision reliability.

Abstract: In an optical communication-use receiving circuit of the present invention, the pulse width of the received pulse which is a binary signal corresponding to the signal optical pulse is specified by using an integration circuit and a trigger generating circuit. If the pulse width of the received pulse is not shorter than a predetermined value, a signal having a fixed pulse width is outputted as an output signal from a one-shot pulse generating circuit, so that a pulse having a constant pulse width corresponding to the specified communication speed is outputted. Accordingly, if the pulse width deriving from the signal optical pulse is larger than a certain value, the communication is deemed as a low-speed communication, and a pulse having a constant pulse width corresponding to the communication speed is outputted. As a result, it is possible to realize a small-size receiving circuit and a small-size electronic device which require no external switching-over terminal.

Abstract: A method, algorithm, architecture, circuits, and/or systems for using a delay-locked loop (DLL) for phase adjustment in a direct conversion radio receiver are disclosed. In one embodiment, a receiver circuit can include: (i) a voltage-controlled oscillator (VCO) for providing a reference clock; (ii) a delay element that can receive the reference clock and provide a delay adjustment signal; (iii) a first channel for receiving a radio signal and providing a recovered radio signal from the radio signal and the delay adjustment signal, where the first channel includes a first mixer and a first filter; and (iv) a second channel for receiving the radio signal and a phase adjustment signal derived from the delay adjustment signal and for providing a delay control signal to the delay element from the radio signal and the phase adjustment signal, where the second channel includes a second mixer and a second filter.

Abstract: A digital signal receiver for a high-bitrate digital signal has a serial signal input (20, 20?) and a number of N parallel digital signal outputs (26) with N>1. The receiver contains at least N+1 digital sampling channels (31-35), a Q-monitor (37, 38) for comparing the output signal of at least two of said sampling channels (31-35), and a switch fabric (36) for controllably connecting N of said sampling channels (31-35) to said output leads (36) and at least two of said sampling channels (31-35) to said Q-monitor (37, 38). This allows to use N of the sampling channels to provide the N output signals while at the same time, the at least one remaining sampling channel can be used by the Q-monitor to scan an eye diagram.

Abstract: An integrated circuit includes an internal resistance (RINT) and a compensation circuit coupled to adjust a slice level specified by a slice signal to a compensated slice level according to a difference between the internal resistance (RINT) and a known resistance (REXT). A reference voltage is coupled to the internal resistance to generate an internal current and is coupled to the known resistance to generate a known current. The compensated slice level is determined according to the internal current and the known current. The compensated slice level may be generated using an analog to digital converter coupled to a digital to analog converter that scale original slice signal based on the internal and known currents.

Abstract: In a communication device, the LO leakage and opposite side band signals are measured at an output signal. Input processing signals to a modulator are adjusted in response to the measured values to minimize the LO leakage and maximize side band suppression.

Abstract: A method of and device for automatic gain control (AGC) incorporates digitally controlled variable gain amplifiers (VGAs). An AGC circuit comprises multiple AGC stages, where each of the stages comprises: respective I and Q VGAs; a detector for detecting respective I and Q output signals received from the respective I and Q VGAs; an analogue to digital converter for converting the detected I and Q output signals; and a digital engine for adjusting the respective I and Q VGAs for differences between the detected I and Q output signals and a reference signal. Using staggered AGCs incorporating respective I and Q VGAs splits the total dynamic range between n stages, allowing for reduced gain requirements in the VGAs. Using digital control for setting the VGA gains reduces analogue variations and I/Q gain imbalances. Using multiple update rates or magnitudes in the VGA control improves dynamic settling time.

Abstract: This digital transmission system is provided with a transmitting apparatus that transmits digital data signals and a receiving apparatus that receives the digital data signals transmitted over a transmission path, compares the signals with a predetermined threshold value, and performs decision reproduction. The receiving apparatus is formed by: decision circuits that receive the input of reception signals, discriminate between the respective reception signals using a plurality of threshold values, and output decision results; and a selection circuit that, based on the decision results output from the decision circuit, selects one decision result from one threshold value from among the decision results from each of the plurality of threshold values, and outputs the selected decision result. As a result, the receiving apparatus is able to individually select which decision result to use from which threshold value.

Abstract: The invention relates to a method for correcting an IQ-imbalance (In-phase and Quadrature) of an IQ-based direct conversion receiver (200). In the method a group of radio frequency pilot signals are received in the direct conversion receiver (200). They are conveyed to an in-phase branch and a quadrature-phase branch of the receiver (200) and mixed, in the analogue domain, to form a baseband in-phase (I) and quadrature-phase (Q) signal components. The signal componets are conveyed to a digital demodulator (210) which detects the IQ-phase imbalance of the direct conversion receiver (200) by analysing at least one of the baseband in-phase (I) and the quadrature-phase (Q) signal components. In the method, the detected IQ-imbalance is corrected, in the analogue domain of the direct conversion receiver (200), to achieve a 90 degrees phase difference between a future baseband in-phase (I) signal component and a future baseband quadrature-phase (Q) signal component.

Abstract: An embodiment of the proposed invention is primarily applied to compensate the BLW in communication systems using THPs in their transmitters, especially suitable for the 10GBase-T Ethernet application. The present apparatus includes an additional decision device (slicer) used to generate DC offset information (error signal) and an extra modulus unit after our BLW compensator to reconvert compensated symbols to correct 16-PAM signals. In addition, the estimated error signals in our method are generated from the difference between the input of the BLW compensator and the output of the decision device. These error signals are then weighted to alleviate the impact of erroneous DC offset information on the performance of the BLW compensator. Therefore, a more direct and accurate DC offset information can be derived to improve the inaccurate BLW estimation in previous works.

Abstract: A radio frequency (RF) integrated circuit (IC) includes a local oscillation module, analog radio receiver, analog radio transmitter, digital receiver module, digital transmitter module, and digital optimization module. The local oscillation module is operably coupled to produce at least one local oscillation. The analog radio receiver is operably coupled to directly convert inbound RF signals into inbound low intermediate frequency signals based on the local oscillation. The digital receiver module is operably coupled to process the inbound low IF signals in accordance with one of a plurality of radio transceiving standards to produce inbound data. The digital transmitter is operably coupled to produce an outbound low intermediate frequency signal by processing outbound data in accordance with the one of the plurality of radio transceiving standards. The analog radio transmitter is operably coupled to directly convert the outbound low IF signals into outbound RF signals based on the local oscillation.

Abstract: A system and method for detecting digital symbols carried in a received optical signal. The system comprises a functional element operative to receive a stream of samples of an electrical signal derived from the received optical signal and to evaluate a non-linear function of each received sample, thereby to produce a stream of processed samples. The system also comprises a detector operative to render decisions about individual symbols present in the received optical signal on the basis of the stream of processed samples. In an embodiment, the non-linear function computes substantially the square root of each received sample.

Abstract: An active-set PAR reduction method has low computation cost and delay. Peak canceling, by adding up the original signal and the peak canceling signal, is done only after the final peak canceling signal that can reduce all peaks of the resultant signal below the desired peak level is generated with an iterative method or a maximum iteration is reached. The PAR reduction method cancels the high computation cost for accumulating the peak-canceling effort into each sample every iteration. In the i-th iteration, the method attempts to resolve an intermediate peak canceling signal that can reduce the i peaks of the resultant signal to the desired peak level. The method only calculates the samples of the intermediate peak canceling signal and performs balance testing in some locations where the peak level of the original signal is larger than a selected threshold.

Abstract: An apparatus for processing a Bluetooth signal advantageously mixes down a received RF signal to an IF signal wherein one band-edge of the spectrum of the IF signal may be approximately 0 Hz. In one embodiment, the IF signal may be digitized, decimated and filtered before being processed into a baseband signal. The baseband signal may be processed by a cordic (COordinate Rotation DIgital Computer) processor to transform the baseband signal from rectangular to polar coordinates. A phase signal from the cordic processor may be used to determine transmitted Bluetooth data symbols. The apparatus may advantageously use less area than traditional Bluetooth receivers.

Abstract: A frame synchronization method is disclosed. The method comprises correlating a stream with a pattern to generate a correlated result c(t). A first peak and a second peak are selected from the correlated result c(t), wherein the first peak is the peak with highest amplitude, and the second peak is the peak occurring later than the first peak with the second highest amplitude. The peak ratio of the two peaks is computed, and the position of the frame boundary is determined according to the ratio.

Abstract: A baseline wandering correction device for correcting baseline wandering of signals at a first output terminal and a second output terminal of a receiver includes: a control circuit for outputting a control signal according to voltages of the first and the second output terminals and a second threshold value; a voltage generation unit coupled to the control circuit for outputting a control voltage according to the control signal, the voltages of the first and the second output terminals, and a first threshold value; and a compensation current source coupled to the voltage generation unit for outputting a compensation current to the receiver according to the control voltage to correct the baseline wandering.

Abstract: A data communication system comprises a transmitter and a receiver. A plurality of current mode drivers at the transmitter are used to transmit clock and data signals to the receiver. A plurality of current mode sinks at the receiver are used to receive the transmitted clock and data signal. The present invention provides an improved current mode interface receiver with a process insensitive common mode current extraction circuit. The proposed common mode current extraction circuit will generate a current reference based on the received clock signal, so as to accurately interpret the received clock and data signals.

Abstract: A method for recognizing a valid change of state in a communication signal including capacitively coupled signals received by an input contact includes maintaining the input contact in a first state and an impedance of the first contact input in a first impedance level, validating that the communication signal sent from to the input contact is a valid change of state, and changing the input contact to a second state and the impedance of the first input contact input to a second impedance level when the voltage signal is validated. An input contact circuit is also disclosed.

Abstract: A method for detecting transmission power reduction in a physical channel including at least a non-enhanced data channel portion, a non-enhanced control channel portion, an enhanced control channel portion and an enhanced data channel portion is provided. The method includes estimating a ratio of a transmission power associated with the enhanced data channel to transmission power associated with the non-enhanced control channel portion, comparing the estimated ratio with a threshold, the threshold being determined based on a format indicator associated with the enhanced data channel portion, and detecting a transmission power reduction in the enhanced data channel portion based on the comparing step.

Abstract: A system and method of wireless communication determines received signal timing deviation which is used to generate a timing advance for adjusting wireless transmit receive unit (WTRU) transmissions. An adaptive threshold for measuring the timing deviation is set based on the energy level of received WTRU signals. WTRU signal samples which exceed the threshold are evaluated to determine timing deviation.

Abstract: A demodulating semiconductor integrated circuit device used in a wireless communication system of an FM-modulation scheme, wherein a circuit for canceling a frequency offset is made of a digital circuit, so as to make a high-accuracy decision as to received data and prevent error frequency offset cancel due to a pseudo pattern contained in the received data. Consequently, a high-accuracy received data decision is carried out.

Abstract: The following invention relates to geolocation technology. In particular, the proposed method can be used to determine the optimum threshold value that minimizes the estimation error. The proposed method also allows the threshold value to be varied adaptively according to the signal-to-noise ratios (SNRs) under consideration. This is to ensure that the optimum threshold value is being selected under all channel conditions i.e., both line-of-sight (LOS) and non-LOS (NLOS) scenarios. Additionally, the proposed method is generic and system independent in which it can be applied to both coherent (e.g., match filter (MF)) and non-coherent receivers (e.g., energy detector (ED)).

Abstract: A normalization factor for a current frame of a signal may be determined. The normalization factor may depend on an amplitude of the current frame of the signal. The normalization factor may also depend on values of states after one or more operations were performed on a previous frame of a normalized signal. The current frame of the signal may be normalized based on the normalization factor that is determined. The states' normalization factor may be adjusted based on the normalization factor that is determined.

Abstract: A data receiving apparatus capable of reducing bit errors caused by noise includes a threshold value calculation unit, a judgment timing output unit, a data judgment unit, and a majority-rule judgment unit. The threshold value calculation unit calculates a plurality of different threshold values to judge whether the status of a received signal is ‘1’ or ‘0’. The judgment timing output unit outputs a plurality of judgment timings in a one-bit section of the received signal. The data judgment unit compares the received signal with each of the threshold values at the judgment timings and judges whether the status of the received signal is ‘1’ or ‘0’. The majority-rule judgment unit decides, by majority rule, on the ‘1’ and ‘0’ statuses obtained by the data judgment unit in the one-bit section and outputs the majority of the ‘1’ and ‘0’ statuses as the signal status of the received signal.

Abstract: A variable power supply voltage generator generates a variable power supply voltage Vvar and supplies it to other circuits. A transmitting circuit 130 (or 140), operative at the variable power supply voltage Vvar, generates multi-value analog signals Smulti and transmits them to other circuits. A receiving circuit 140 (or 130), operative at the variable power supply voltage Vvar, receives the multi-value analog signals Smulti and subjects them to A/D conversion to generate multi-value digital signals. The threshold voltage generator generates threshold voltages used for A/D conversion from the variable power supply voltage Vvar or from a signal having a voltage value proportional to that of the variable power supply voltage Vvar and supplies them to the receiving circuit. An analog clock generator 120 generates an analog clock signal having a cyclical analog waveform.

Abstract: Provided is a burst mode optical receiver considering a characteristic of an extinction ratio of a received optical signal is provided. By using a peak detector considering a characteristic of an extinction ratio, top and bottom peak voltages of actual burst packets can be precisely detected while not being affected by a DC offset corresponding to an extinction ratio even though burst packets having a DC offset corresponding to the extinction ratio are received. Accordingly, waveform distortion of a signal output from the burst mode optical receiver can be minimized.

Abstract: A plurality of detectors are included which have different detection frequencies. The detectors detect the signal level of an IF signal at the respective detection frequencies. The IF signal is produced by frequency conversion of an incoming signal in a mixing section. A comparator identifies the modulation scheme of the incoming signal from a comparison of the signal levels detected by the detectors. Accordingly, a detecting circuit is realized which is contained in a common multi-scheme receiver receiving a plurality of transmission signals with different modulation schemes and which identifies various modulation schemes for incoming signals.

Abstract: A mobile device capable of scaling input data and a method thereof. The mobile device comprises a data segmentation module, a quality measure module, and a scaling module. The data segmentation module divides the input data into a plurality of subdata. The quality measure module, coupled to the data segmentation module, calculates signal quality of each subdata. The scaling module, coupled to the quality measure module, scales each subdata according to corresponding signal quality.

Abstract: The discrimination phase margin monitor circuit (10) of the present invention comprises a first discrimination circuit (11 and 12) discriminating an input data signal using a clock signal extracted from the input data signal, a second discrimination circuit (13 and 14) discriminating the input data signal using a clock signal with a frequency different from that of the clock and an operation circuit (15 and 16) calculating the exclusive OR of the output signal of the first discrimination circuit and that of the second discrimination circuit and obtaining a phase margin monitor output signal by averaging the exclusive ORs.

Abstract: A digital baseband (DBB) radio frequency (RF) receiver used for receiving and processing a wireless communication signal. The DBB RF receiver includes a demodulator, an analog to digital converter (ADC) and a digital cross-talk compensation module. The demodulator outputs analog real and imaginary signal components on real and imaginary signal paths, respectively, in response to receiving the communication signal. The ADC receives the analog real and imaginary signal components and outputs respective digital real and imaginary signal components. The digital cross-talk compensation module receives the digital real and imaginary signal components, estimates the cross-talk interference caused by each of the signal components, and outputs digital real and imaginary cross-talk compensated signal components.

Abstract: A data slicer includes a comparator coupled with an input signal and a reference signal for generating a sliced signal, a waveform generator for generating a calibration signal, a pulse extension device coupled to the comparator and the waveform generator for modifying the duty cycle of the sliced signal or the calibration signal to output, a charge pump coupled between the pulse extension device and a first node for charging and discharging the first node according to the signal output from the pulse extension device, a determining circuit for adjusting the data slicer according to the level change at the first node, and a feedback device coupled between the first node and the comparator for generating the reference signal.

Abstract: A signal processing circuit including a demodulator having an input for receiving a received signal which includes falling and rising signal edges, and an output for outputting a demodulated received signal which, with signal edges of the received signal, includes transitions from a first level to a second level or vice versa, wherein times of the transitions depend on steepnesses of the signal edges. Additionally, the circuit includes a signal generator having an input for receiving the demodulated received signal and coupled to the output of the demodulator, and an output for outputting a corrected demodulated received signal which includes transitions, the times of which relative to the times of the transitions of the demodulated received signal are set based on a reference signal to reduce influences of the steepnesses of the falling and rising signal edges in the corrected demodulated received signal relative to the demodulated received signal.

Abstract: A data slice control device comprises a monotone increase detection circuit for detecting a monotone increase point of a data signal, a monotone decrease detection circuit for detecting a monotone decrease point of the data signal, a counter for calculating a monotone increase interval value from the monotone increase point to a next monotone increase point, a data holding circuit for calculating a monotone increase monotone decrease interval value from the monotone increase point to the monotone decrease point, a CRI period determination circuit for determining whether the data signal is within a CRI period or not on the basis of the monotone increase interval value and the monotone increase monotone decrease interval value, and a slice level calculation circuit for calculating a slice level from a maximum value and a minimum value of amplitude values of the data signal only when the data signal is within the CRI period.

Abstract: Dynamic adjustment of searcher thresholds used to detect propagation paths of a communications signal transmitted from a transmitter to the base band receiver. Interference signal code power (ISCP) measurements of the communications signal are obtained from a database communicatively coupled with the base band receiver, wherein contents of the database are associated with a physical layer. A scaler is calculated based on the ISCP measurements only. The searcher thresholds, which are stored in the database, are adjusted using the scaler. The adjusted searcher thresholds are then stored in the database.

Abstract: Modified branch metrics for processing bit-soft decisions to account for phase noise impact on cluster variance (CV). The present invention is able to partition a modulation scheme's constellation into two or more regions, so that the bit-soft decision branch metrics may be adjusted based on the CV of the various constellation points. A confidence level may be attached to the various constellation points based on their particular CVs. There are a number of methods to ascertain the CV of the constellation's points, including finding characteristics of various components in a communication system (transmitter, communication channel and receiver), and any method may be used within various embodiments. The modification of the branch metrics/confidence level may be performed in a communication receiver; the communication receiver may be implemented in a communication system employing the vector orthogonal frequency division multiplexing (VOFDM) portion of the broadband wireless internet forum (BWIF).

Abstract: An example wireless communication device is provided with a binarizing circuit which precisely carries out binarization even if a level of an input signal is kept substantially consistent for a long period. The binarizing circuit includes: a comparator which outputs a data slicer output by comparing a generated signal generated from a demodulated signal with 0 level; a feedback circuit which detects a direct current level of the generated signal, thereby outputting an inversion signal of the direct current level; and an adder circuit which outputs the generated signal by adding the inversion signal to the demodulated signal. Since an offset canceller of the feedback circuit outputs 0 to an integration circuit when the generated signal falls within a predetermined range, the generated signal does not follow the demodulated signal even if the demodulated signal is kept at a substantially consistent level, thereby reducing errors.

Abstract: This invention discloses a receiver and a signal compensation method therefor. An adaptive equalizer and a baseline wander compensator are provided on the front end of the receiver to improve the quality of output signals. The signal compensation method enables the adaptive equalizer to use a long T as its observation unit when the transmission cable is idle, and enables the baseline wander compensator for operation and controls both the adaptive equalizer and the baseline wander compensator to use a short T as its observation unit when the transmission cable is transmitting data signals. The disclosed adaptive equalizer can achieve its optimal processing effects, and the efficiency of the baseline wander compensator can be increased.

Abstract: An apparatus and a method for compensating signal attenuation based on an equalizer. The apparatus Includes an auto gain controller, an analog-to-digital converter and an auto-gain-control mapping circuit. The auto gain controller is used for receiving an incoming analog signal and amplifying the received analog signal. The analog-to-digital convertor is used for converting the output of the auto gain controller into a digital signal. The output of the auto-gain-control mapping circuit is used to control the gain of the auto gain controller. The equalizer is connected to the output of the analog-to-digital converter to eliminate signal attenuation in the digital output of the analog-to-digital converter. The output of the auto-gain-control mapping circuit controls the gain of the auto gain controller based on the primary weight of the equalizer.

Abstract: A wireless receiver includes a local oscillator, a mixer, a band pass filter, a DC offset determination module, a DC offset correction module, a subtraction module, and a down converter. The local oscillator produces a local oscillation that a mixer uses to down convert the RF information signal to produce a Very Low Intermediate Frequency (VLIF) information signal at a VLIF and having a DC offset. The band pass filter band pass filters the VLIF information signal. The DC offset determination module produces a DC offset indication for the VLIF information signal. The DC offset correction module generates a DC offset correction based upon the DC offset indication. The subtraction module subtracts the DC offset correction from the VLIF information signal to substantially remove a DC offset of the post-filtered VLIF information signal. The down converter down converts the VLIF information signal to a baseband information signal.

Abstract: A reception error rate controller in which the settling time can be shortened at the time of feedback control by controlling the quality of a received signal when the error rate is low. The reception error rate controller identifies the received signal by comparing it with a reference value, detects the error rate of the identified signal, controls the reference value based on the error rate and further controls the quality of the received signal based on the error rate.

Abstract: A base band circuit of a receiver and a low cut-off frequency control means can quickly converge transition state due to gain fluctuation with setting a low cut-off frequency of a high-pass filter as low as possible. The base band circuit of a receiver has a variable amplifier variably amplifying a base band signal depending upon a gain control signal, a high-pass filter provided in a path of the base band signal, and a controller detecting variation magnitude of the gain control signal and controlling variation of a low cut-off frequency of the high-pass filter means depending upon the detected variation magnitude.

Abstract: The receiver is provided which comprises a mixer, a low pass filter coupled to the mixer and a plurality of gain controllers serially coupled to an output of the low pass filter (LPF). A plurality of analog-to-digital converters (ADCs) is coupled so that an input of a first of the ADCs is coupled to the output of the LPF. An input of each of a remaining portion of the ADCs is individually coupled to a corresponding output of each of the serially coupled gain blocks. An output path traced from the output of the LPF to an output of each of the analog-to-digital converters may be referred to as a processing path. Each processing path may comprise a gain controller and an ADC, except for the first processing path, which may have an ADC coupled directly to the output of the LPF.

Abstract: In a receiver operable in response to a data signal, an eye aperture size is detected along a time axis by an eye aperture detection circuit and is controlled by a control circuit so that it becomes a maximum. The eye aperture detection circuit determines different decision time points of the same level arranged along a time axis and judges whether or not an error is caused to occur at each of the decision time points, so as to detect the eye aperture size and to produce detection results. The control circuit processes the detection results in accordance with a predetermined algorithm to successively vary the eye aperture size and to keep the data signal at an optimum amplitude.

Abstract: A communication receiver amplifies a pulse-amplitude-modulated (PAM) signal representing an integer-valued sequence of first data elements (D1) with an adjustable first gain (G1) and digitizes the amplified signal to produce a sequence of second data elements (D2) representing successive magnitudes of the PAM signal. A first automatic gain control (AGC) circuit determines the rate at which magnitudes of the second data sequence elements fall within a first range and adjusts G1 to maintain that rate within a second range. Digital signal processing circuits within the receiver process the second data to produce a sequence of third data elements (D3), each having a real number value substantially equal to a product of a second gain G2 and a corresponding one of the first data elements D1. A slicer rounds the real number represented by each third data sequence element to produce a corresponding integer-valued element of a fourth data sequence (D4).

Abstract: The present invention relates in general to a method, apparatus, and article of manufacture for providing high-speed digital communications through a communications channel. In one aspect, the present invention employs an automatic slicer level adaption to enhance the performance of a high speed communications system.