Abstract: To demodulate a frequency-modulated signal having an offset, two time constants are provided in a filter unit. The filter unit has two analog or digital low-pass filters or high-pass filters. A first switch is used to change over between the two time constants. If a plurality of bits having the same state succeed one another in a setting mode, the first switch is used to change over to a slower time constant so as not to corrupt the threshold voltage that is to be ascertained. In a normal mode, the stored threshold voltage is, then, used to distinguish between the states coded in an input signal. In such a context, the slower time constant is valid in the normal mode.

Abstract: An increase in the code error rate in a received signal is detected in a light receiver. An loss of signal detector circuit for a light receiver 20 comprises a main discrimination circuit 8a for comparing the intensity of an electric signal obtained by converting a light signal by photoelectric conversion using a photoelectric conversion element 1 with a predetermined discrimination threshold; a reference discrimination circuit (8b, 8c, . . . ) for comparing the intensity of the electric signal with regard to a reference threshold which differs from the discrimination threshold; and an operation circuit 9 for detecting loss of the signal based on the results of the comparisons performed by the main discrimination circuit 8a and the reference discrimination circuit (8b, 8c, . . . ).

Abstract: A method is provided for determining a slice level in the quantizer of a receiver, by determining the proportions of received signal values which lie below and above specified values. These proportions, which correspond to points on a cumulative probability function, can be used with assumptions about the received signal distribution, to determine a desired slice level.

Abstract: A semiconductor circuit includes a decision feedback equalizer (DFE) for waveform-equalizing an input signal and generating a waveform-equalized input signal. The DFE compares the waveform-equalized signal with a predetermined reference voltage to generate a decision signal having first and second decision values and an error signal which lies between the waveform-equalized signal and the decision signal. A dispersion value calculator is connected to the DFE, calculates first and second dispersion values of the first and second decision values of the decision signal using the error signal, and produces a compensation signal using the first and second dispersion values. An asymmetry compensator is connected to the DFE and the dispersion value calculator. The asymmetry compensator receives the input signal and corrects an asymmetry in the input signal in accordance with the compensation signal and supplies the corrected input signal to the DFE.

Abstract: The present invention includes a system that determines a threshold to distinguish between binary signals. The system includes a bit wise threshold determination device coupled to receive an input signal and that delays the input signal, averages the input signal and the delayed input signal, and outputs the average to an output node. The average represents a threshold value. This system can be used in any system that must determine a threshold between binary values.

Abstract: A transmitter circuit for transmitting a sine wave modulated with digital data, where the sine wave includes a clock signal, and a receiver circuit for demodulating the transmitted sine wave, where the receiver circuit extracts the clock signal and the digital data from the sine wave. The transmitter circuit includes digital logic components that allow the transmitted sine wave to include at least one bit per cycle of the sine wave, and the receive circuit includes digital logic components that allow the clock signal and the digital data to be extracted from the sine wave. In various embodiments, the transmitted sine wave includes one bit per cycle, one bit per half cycle, multiple bits per cycle and multiple bits per half cycle.

Abstract: A method is disclosed for recovering a digital signal from an analog signal. A received analog signal value is compared with a centre threshold, and with at least one of a pair of outer thresholds, to form comparator output signals. Digital samples of the comparator output signals are formed using a recovered clock signal. The values of the outer thresholds are adapted such that a constant proportion of the digital samples represent received signal values lying between the outer thresholds, and the phase of the recovered clock signal is adapted such that the separation of the outer thresholds is maximised. Other receiver parameters can be adapted in the same way.

Abstract: A tracking system and method in an optical communications system utilizing an optical communications beam. In one embodiment, the disclosed optical communications system includes a communications receiver circuit and a tracking circuit. The optical communications system generates a communications signal. The tracking system includes a tracking detector having a plurality of regions coupled to a corresponding plurality of tracking channel circuits. Each of the tracking channel circuits includes an optical detector coupled to receive the optical communications beam. The peak-to-peak amplitude modulation in the optical communications beam is measured by substantially reducing or removing a direct current (DC) offset present in the optical communications beam. In one embodiment, after the DC offset is substantially reduced or removed, the signal is then amplified, mixed with the communications signal and then filtered.

Abstract: Techniques to adjust the setpoint of a power control loop in a wireless communication system. The setpoint may be adjusted based on frame status indicative of erased/good decoded frames, one or more (typically soft) metrics indicative of the confidence in the decoded results, power surplus/deficit indicative of the difference between the received signal quality and the setpoint, setpoint surplus/deficit indicative of the difference between the setpoint and a threshold Eb/Nt needed for the desired level of performance, or a combination thereof. The metrics may include re-encoded symbol error rate, re-encoded power metric, modified Yamamoto metric, minimum or average LLR among decoded bits, number of decoding iterations, and possibly others. The setpoint may be adjusted in different manners and/or by different amounts depending on the above-noted factors. The techniques may be employed for forward and/or reverse links in CDMA systems.

Abstract: A method of processing a pulse response with an adaptive threshold and corresponding receiver. According to the method, an adaptive threshold is calculated that is a function of a maximum reached by the pulse response, noise, and a coefficient adjustable between 0 and 1. The processing only comes into operation for signals that exceed this threshold. Such a method may find application notably to digital radio-communications with spread spectrum.

Abstract: The present embodiments provide apparatuses and methods for use in receiving radio frequency signals. In some embodiments, a method receives an input signal comprising data and jamming signals, amplifies the input signal according to a first adjustable bias level and producing a first internal signal. The first internal signal is mixed with an intermediate frequency signal to produce a second internal signal. The method detects a level of a signal that is proportional to a level of the input signal prior to baseband limiting filtering and as such is proportional to a level of the data and jamming signals. A bias control signal is generated that is dependent on the detected level of the detected signal, and the first bias level is adjusted according to the bias control signal. The bias control signal can increase as the level of the detected signal increases and can compensate for the jamming signals.

Abstract: Techniques that may aid in the recovery of clock and data signals include receiving a stream of incoming data signals and determining an offset based, at least in part, on the state of a transition bit sampled from the stream of incoming data signals. The slice level of an input sampling circuit is adjusted based on the offset. Re-timed data signals corresponding to the incoming data signals may be generated.

Abstract: An allocation section 101 in a base station apparatus of the present invention sets the transmission rate of a transmit signal for a communication terminal apparatus based on a DRC signal transmitted from that communication terminal apparatus. A power margin information detector 117 detects power margin information from a demodulated signal generated by a demodulator 115, and, using that power margin information, a power setting section 118 makes a setting so as to give the minimum transmission power value at which received signal characteristics in each communication terminal apparatus meet the desired quality. Using the set transmission power value, the base station apparatus transmits a transmit signal of the set transmission rate to a communication terminal apparatus.

Abstract: A receiver in a radio system, the receiver comprising means (500) for receiving a signal, an analogue-to-digital converter (504) for providing signal samples from the received signal. The receiver comprises means (508) for selecting a set of signal samples, means (508) for forming a statistical function value on the basis of the selected signal sample values, means (508) for forming a threshold value on the basis of the statistical function value and a preset threshold parameter, means (508) for dividing the samples between a set within the statistical distribution and a set outside the distribution by using the threshold value as a limit, and means (508) for repeating said statistical function value formation by using the set in accordance with the distribution, said threshold value formation and said division of samples into said sets if the termination condition for repetition is not fulfilled.

Abstract: The present invention is directed at providing methods in a circuit for smoothing transitions relating to a signal processing function. A reference signal is produced that relates to a DAC output code. The reference signal is used as a starting point, and is compared to the input signal. A feedback signal is produced that is used to adjust the reference. The invention can be used to implement signal processing functions such as peak detection, noise filtering, peak suppression, and the like, in which the transitions in the signal are smoothed. The invention can implement these functions with a minimal complexity and a minimal die area.

Abstract: A direct conversion or VLIF receiver corrects DC offset by, prior to receiving a burst of data, the receiver determines a coarse DC offset with the antenna of the receiver switched off. The receiver then adjusts an analog portion of the receiver (e.g., the output of the mixers) based on the coarse DC offset. The receiver then determines a gain setting of the receiver (e.g., for the low noise amplifier and/or programmable gain amplifiers) with the antenna on. The receiver then sets the gain of at least one gain stage of the receiver based on the gain setting. The receiver then determines a fine DC offset with the antenna off. The receiver then, while receiving a burst of data, subtracts the fine DC offset from the digital baseband or low IF signal prior to data recovery.

Abstract: An FM demodulator compensates for DC offset by detecting the positive peak value of the frequency demodulated signal (D1, C2, R1) and the negative peak value of the frequency demodulated signal (D2, C3, R2). The mean of the positive and negative peak values is determined (C1, R3, R4) to produce an estimation of a DC offset value. This estimated DC offset value is then used to compensate for DC offset in the frequency demodulated signal. This circuit has the advantage of enabling the DC offset to be calculated without requiring complex digital signalling processing, and without requiring the input signal to have a zero mean. A signal strength signal RSSI may be used to disconnect the DC offset compensation circuitry during periods when the input signal strength is weak.

Abstract: A threshold detector for detecting synchronization signals at correlator output during packet acquisition. An RF receiver converts RF signals into baseband signals. A matched filter correlator correlates samples of the baseband signals with predetermined synchronization signals, such as long sync symbols, and provides corresponding correlation samples. A long-term integrator integrates a first predetermined number of the correlation samples to provide a long term moving average and a short term integrator integrates a second predetermined number of the correlation samples to provide a short term moving average signal. The short term moving average signal is based on channel delay spread and the long term moving average tracks channel noise. A multiplier multiplies the long term moving average signal by a scale factor to generate a dynamic threshold. A detector detects a crossover between the short term moving average and the dynamic threshold to estimate timing of received synchronization signals.

Abstract: While a discrimination level is scanned by a discrimination section, an average-value detecting section detects the average value of the discrimination output. This yields a distribution function of an input signal. Further, a differentiation section performs a differential process to acquire a probability density function. Average values or dispersion values of, for example, the mark level and space level of the input signal are computed from the distribution function and the probability density function. Accordingly, a Q value as a quality parameter can be obtained.

Abstract: A spread-spectrum communication apparatus includes an analog modulator and demodulator for modulating and demodulating information in its transmitter and receiver respectively. The apparatus also includes a spreader and de-spreader for modulating and demodulating a spread-spectrum signal respectively in its transmitter and receiver. This structure widens a dynamic range of the RSSI with an inexpensive and simple circuit. This structure also allows the apparatus to operate in a stable manner against an intense input signal, to detect an “out of sync” in a highly reliable manner and move immediately to a “sync-tracking mode”.

Abstract: A method and apparatus for monitoring and adjusting an analog signal of an operating circuit. The apparatus includes a control circuit, an analog-to-digital converter, and a comparator. The control circuit has an analog generator for generating the analog signal and an adjusting circuit for adjusting the strength of the analog signal. The analog-to-digital converter receives the analog signal and converts the analog signal to a digital signal. The comparator then compares the value of the digital signal to a predetermined value and generates a comparator signal. The adjusting circuit then receives the comparator signal and adjusts the strength of the analog signal based upon the value of the comparator signal. The method includes generating the analog signal, converting the analog signal to a digital signal, comparing the value of the digital signal to a predetermined value and adjusting the strength of the analog signal.

Abstract: A slice circuit includes a DC component adjusting circuit, an integrator, a low pass filter, and a comparator. The DC component adjusting circuit adjusts only a DC component in an input signal sent from an input terminal to produce a DC component having a uniform voltage level. The integrator amplifies only a high frequency component of or above a predetermined frequency in the input signal received from the DC component adjusting circuit. The low pass filter detects an average voltage of the input signal received from the DC component adjusting circuit. The comparator compares a voltage of the output signal sent from the integrator with a voltage of an output signal sent from the low pass filter, and provides a digital signal having a logical level corresponding to results of the comparison to an output terminal.

Abstract: A slice circuit includes a DC component adjusting circuit, an integrator, a low pass filter and a comparator. The DC component adjusting circuit adjusts only a DC component in an input signal sent from an input terminal to produce a DC component formed of a uniform voltage level. The integrator amplifies only a high frequency component of or above a predetermined frequency in the input signal received from the DC component adjusting circuit. The low pass filter detects an average voltage of the input signal received from the DC component adjusting circuit. The comparator compares a voltage of the output signal sent from integrator with a voltage of an output signal sent from the low pass filter, and provides a digital signal having a logical level corresponding to results of the comparison to an output terminal.

Abstract: The present disclosure discloses a method and apparatus for slicing data, or “squaring up” a signal such as the output of a wireless receiver demodulator for proper interface with conventional digital logic circuits. The method involves the receiving of an input signal, the generation of a reference level, the comparison of the input signal to the reference level, and the measurement and storage of the reference level. The reference level is generated by applying the input signal to a filter, which has been previously set to an initial condition. The reference level is measured at a predetermined point in a receive data frame, and is maintained at the desired level throughout the remainder of the frame. After a frame has been received, the reference level is stored if the frame data output from the data slicer contained no errors.

Abstract: A multipath noise reducer detects and removes the individual noise spikes occurring in an interval of multipath noise, thereby reducing the multipath noise with relatively little distortion of the output signal. The threshold signal used to detect multipath noise is varied depending on reception conditions. The gate pulses indicating the presence of multipath noise spikes are preferably expanded by variable amounts, depending on both reception conditions and the signal level. Multipath noise spikes are preferably replaced by a smoothed signal. These provisions further reduce perceived distortion of the audio output signal.

Abstract: A digital FM demodulator converts a digital FM input signal to a demodulated signal, detects the amplitude of the digital FM input signal, generates a corresponding amplitude signal, and adjusts the amplitude of the demodulated signal according to the amplitude signal, thereby compensating for variations in the amplitude of the digital FM input signal and removing amplitude distortion from the demodulated signal. This reduces the performance requirements of, for example, a low-pass analog filter preceding the digital FM demodulator in an FM radio broadcast receiver, permitting the analog filter to be implemented in a semiconductor integrated circuit.

Abstract: A decision feedback equalizer includes a lookup table device. The lookup table device may include a shift register and memory, or may include multiple shift registers and memories. Near-end crosstalk may be reduced using a lookup table device. Echo in a bi-directional port circuit may also be reduced using a lookup table device.

Abstract: Data of the packet header is digitalized by a slicer circuit of a floating slice level mode, which follows DC voltage fluctuation, and packet data other than the packet header is digitalized by a slicer circuit of a fixed slice level mode, which does not follow DC voltage fluctuation. A default slice level of the fixed slice level mode is created by using demodulated data in a packet header section so as to accurately carry out switching of slicing methods. Obtained is a data slicer capable of accurately carrying out digitalization with respect to a signal, which is demodulated after being received.

Abstract: An FSK receiving apparatus has, as means for performing offset correction upon a demodulated base band signal, a second low pass filter 9 for integrating the demodulated base band signal; a window comparator for detecting a DC offset component in an output voltage from the second low pass filter 9; an up/down counter 11 for incrementing or decrementing a count value on the basis of the output of the window comparator 10; a clock generating portion 13 for generating a timing signal for counting operation in the up/down counter 11; a reference voltage generating portion 12 for generating a reference voltage for a comparator 7 on the basis of the output of the up/down counter 11; and a charging circuit 22 for supplying a reference voltage in the last frame to the second low pass filter 9 so as to charge the second low pass filter 9 with the last-frame reference voltage and set an initial value of the second low pass filter 9.

Abstract: A signal level detector to detect the level of 1-bit digital signal is provided. It includes a level detector (12) supplied with a sequence of 1-bit digital signals decoded by an audio decoder (5) and which counts the number of 0 (zeros) or 1 (ones) included in the row of a predetermined number n of 1-bit digital signals to detect the level of the 1-bit digital signal, and an indication unit (13) to indicate the signal level detected by the level detector (12).

Abstract: A receiver of baseband signals from a communications line characterized by baseline wander, including a pre-decoding section, which receives and samples the signals and subtracts each sample from a preceding sample so as to generate corrected data, and an equalization section, which receives the corrected data and generates equalized output data representative of data input to the line and generally free of the baseline wander. The receiver preferably includes an A/D converter, which digitizes the signals either before or after pre-decoding.

Abstract: An automatic gain control circuit for an optical receiver couples the low level signal produced by an optical detector to a signal amplifier, preferably a double-ended differential amplifier with the optical detector output fed into the high input and the low input coupled to ground, the gain of which is controlled by a negative feedback circuit. The feedback circuit comprises a signal level detection circuit coupled to the amplifier output, such as high-speed Schottky diodes acting in conjunction with an operational amplifier. The Schottky diodes are coupled to ground through AC coupling capacitors, and oriented in opposite directions, so when the amplified signal exceeds a conduction threshold of the Schottky diodes the capacitors are respectively charged and drained, establishing a voltage difference between the input terminals of the operational amplifier.

Abstract: A demodulating circuit 1 contains an electric field level detector 2 for detecting an electric field strength from a received modulation signal, comparators 3a to 3n for outputting electric field strength information PS, a detector 5 for outputting a detection signal corresponding to a modulation signal, both a low-pass filter 6 and a digital filter 12 for removing a noise component from the detection signal, and a data comparator 7 for comparing the detection signal with a reference voltage to output a digital signal. This demodulating circuit 1 further includes a control circuit 4 for controlling a cutoff frequency used in a digital filter 12, an output voltage amplitude of the detector 5, and the reference voltage of the data comparator 7 in accordance with both the electric field strength information PS and control condition information PC saved in an EEPROM 11 and supplied from a CPU 10, and also a judging circuit 9 for judging the digital signal at preselected timing to produce a demodulation signal.

Abstract: This digital transmission system is provided with a transmitting apparatus that transmits digital data signals and a receiving apparatus that receives the digital data signals transmitted over a transmission path, compares the signals with a predetermined threshold value, and performs decision reproduction.

Abstract: A system and method are provided for feed-forward/feedback non-causal channel equalization in a communications system. The method comprises: receiving a non-return to zero (NRZ) data stream input; using three thresholds, estimating a first bit in the data stream; using two thresholds, determining a third bit value received subsequent to the first bit; comparing the first bit estimate to the third bit value; comparing the first bit estimate to a second bit value received prior to the first bit; and, in response to the comparisons, determining the value of the first bit. In some aspects of the method, the third bit value is determined in response to a prior third bit value determination. Determining a third bit value includes: distinguishing NRZ data stream inputs between fourth and fifth thresholds as a “0” if the prior third bit value was a “1”, and as a “1” if the prior third bit value was a “0”.

Abstract: A differential slicer circuit includes a plurality of differential comparators and threshold voltages. Each differential comparator includes two matched amplifiers cross-coupled as a subtractor for a differential threshold signal dependent on the threshold voltages. The differential comparator outputs a differential output voltage dependent on the difference between an input differential signal and the differential threshold voltage.

Abstract: An object of the invention is to prevent an erroneous operation of the internal circuits due to glitches and to dispense with a circuit as a countermeasure against glitches. There are provided a low-value threshold detector, a high-value threshold detector, and a set/reset latch circuit. The low-value threshold detector receives two differential data input DATA+ and DATA− signals and detects whether both input signals are lower than a first threshold voltage. The high-value threshold detector receives the input DATA+ and DATA− signals and detects whether one of the input signals is higher than a second threshold voltage. And the set/reset latch circuit is used for outputting an SE0 signal. the set/reset latch circuit is set when the levels of both input DATA+ and DATA− signals are lower than or equal to the first threshold voltage, and is reset when one of the levels of the input DATA+ and DATA− signals is higher than or equal to the second threshold voltage.

Abstract: A multi-carrier receiver system and method for receiving a transmission frequency multi-carrier signal include a feedforward cancellation loop. A frequency conversion circuit generates an intermediate frequency (IF) multi-carrier signal based on the transmission frequency multi-carrier signal. The feedforward cancellation loop generates an amplitude corrected multi-carrier signal based on the IF multi-carrier signal such that the amplitude corrected multi-carrier signal has a reduced dynamic range with respect to the IF multi-carrier signal. A primary A/D converter having a significantly lower dynamic range requirements can therefore generate a digital multi-carrier signal based on the amplitude corrected multi-carrier signal. The feedforward cancellation loop therefore enables the primary A/D converter to process multi-carrier signals without the need for large dynamic range requirements.

Abstract: To improve a capacity of coherent detection of the spread spectrum (SS) signal, when interference and noise can not be neglected. Amplitude phase estimation unit outputs transmission line estimation value including fluctuations in the transmission lines, using known pilot signals of which transmission sequences are known. The pilot signal is extracted from the despread signal through despreading filter. Reliability measurement unit pursues a reliability value of transmission line estimation value. Interpolation unit generates vectors for compensating the phase, by deciding a method of interpolation on the basis of the reliability. Coherent detection unit compensates the amplitude and phase of information symbol to execute the coherent detection.

Abstract: An adaptive slicer threshold generation system includes a first moving average filter to determine a first average value of a first binary signal. A second moving average filter is included to determine a second average value of a second binary signal. A combiner combines the first average value of the first binary signal and the second average value of the second binary signal to generate a combined output.

Abstract: A communications receiver includes an analog input for receiving an analog signal having a time-varying DC voltage drift. A variable gain amplifier is coupled to the analog input and is adapted to amplify the analog signal based on a gain set by a gain control input to the amplifier. An analog-to-digital (A/D) converter is coupled to an output of the amplifier and is adapted to convert the amplified analog signal to a series of digital values. A drift estimator is coupled to the A/D converter, which generates an estimate of the time-varying DC voltage drift based on the series of digital values. A gain adjuster is coupled between the drift estimator and the amplifier, which adjusts the gain control input based on the drift estimate.

Abstract: A method for refining a DC-Offset estimate and removing of the DC-Offset includes the step of determining if any AM is present (602). If AM is determined to be present, it is next determined if the I and Q path DC-Offset estimates are closely matched, if they are, then only a single search using the average of the I and Q path estimates is used (608). If it determined however, that the two path estimates are not closely matched, than two searches are performed, one for each path (610). After this, the blocking signals are searched for up to a predetermined number and the DC-Offset vector is generated (612). Once the DC-Offset vector is generated, the DC-Offset is removed from the received signal (614). After which it is determined if the AM level is high (616), and if so, a transient correction routine is performed (618).

Abstract: A receiver for high bitrate binary signals contains a soft decision circuit with three parallel deciders coupled to a 2:1 multiplexer. The three deciders have different threshold values and generate four potential states. The 2:1 multiplexer translates the four different states into a restored data signal and a reliability signal indicating the decision reliability.

Abstract: A method and apparatus for providing a self-sustaining precise voltage and current feedback biasing loop. The present invention provides a circuit for initially biasing the bandgap and master bias current generator at startup. The feedback biasing loop has loop dynamics that are chosen such that the gain of the positive feedback loop is less than one so that the loop will not oscillate under normal operation after power-up.

Abstract: A data pulse receiver includes a data regenerator and a peak detector, both having set-reset flip-flops (RS-FFs) to generate hysteresis which is varied based on its tail current provided to the RS-FF. The regenerator regenerates data from a differential signal derived from an incoming data signal. The peak detector monitors the peak level of the differential signal derived and its output adjust automatically the tail currents of the data regenerator and the peak detector. The receiver also includes impedance matching networks connected to the data regenerator and the peak detector. The input impedances for both networks are essentially the same. The tail currents for the two RS-FFs of the regenerator and the peak detector are essentially equal and it ensures precise cancellation of non-linear effects.

Abstract: The device and the method enable determining a respectively current level of a digital signal. The digital signal is compared with a threshold value that is located between the state representing the low level of the digital signal and the state representing the high level of the digital signal. The threshold value that is used is matched to the prevailing conditions, that is, the threshold value is defined taking account of the waveform of the digital signal.

Abstract: The present invention relates in general to a method, apparatus, and article of manufacture for providing high-speed digital communications through a communications channel. In one aspect, the present invention employs an automatic slicer level adaption to enhance the performance of a high speed communications system.

Abstract: The present invention relates to a method and an apparatus for compensating a signal that has experienced fading distortion in a communication channel. The signal that can be a TDMA (Time Division Multiple Access) signal includes slots that carry data symbols. Non-uniformly spaced pilot symbols are also embedded in the slot structure. The receiver separates the incoming symbols stream in two parts namely a pilot symbols stream and data symbols stream. Since the transmitted pilot symbols are known, an estimate of the channel distortion on the pilot symbols locations can be computed. This estimate is then interpolated to provide an estimate of the fading distortion at the data symbols locations, thus allowing to compensate accurately for the fading distortion in the channel.

Abstract: An apparatus and method of the present invention allows the digitally decoding of asynchronous communication signals and includes a sampling and storing circuit for sampling a digitally converted asynchronous communication signal and storing sampled signal values corresponding to negative edge signal values, positive edge signal values, and central signal values. A derivative calculating circuit is connected to the sampling of storing circuit for receiving at least negative edge signal values and positive edge signal values and calculating derivatives. A comparator circuit receives the calculated derivatives and compares the derivatives with the threshold based on the calculated negative derivative and produces negative output and positive output values used for determining a decoded output signal.

Abstract: A receiving circuit is described for a CAN (Controlled Area Network) system with digital data transfer via a bus with parallel, redundant pulse signal transfer via two fines. The receiving circuit includes a comparator circuit assembly for differential evaluation of the two pulse signals received via the two lines, with an offset voltage being superimposed on the pulse signal received via one of the two lines prior to said differential evaluation. The comparator circuit assembly superimposes both a positive offset voltage and a negative offset voltage. A bistable multivibrator circuit is connected between the output side of the comparator circuit assembly and the output of the receiving circuit.