Abstract: A semiconductor integrated circuit has a reception circuit configured to receive a strobe signal of which a logic is intermittently switched in synchronization with a data signal, an output circuit configured to extract a low frequency component including at least a DC component of the strobe signal received by the reception circuit and to output a first signal, and a comparison circuit configured to compare a signal level of the first signal with a threshold level. The reception circuit is configured to change a boost amount of a high frequency component different from the low frequency component of the strobe signal based on a comparison result obtained by the comparison circuit.

Abstract: An apparatus for providing a processed audio signal representation on the basis of input audio signal representation configured to apply an un-windowing, in order to provide the processed audio signal representation on the basis of the input audio signal representation. The apparatus is configured to adapt the un-windowing in dependence on one or more signal characteristics and/or in dependence on one or more processing parameters used for a provision of the input audio signal representation.

Abstract: A power electronics converter includes a converter commutation cell having a power circuit and a gate driver circuit. The power circuit includes at least one power semiconductor switching element and at least one capacitor. Each power semiconductor switching element is included in a power semiconductor prepackage. The gate driver circuit is configured to provide switching signals to a gate terminal of each power semiconductor switching element, and a peak rated power output of the power electronics converter is greater than 25 kW and a value of a converter parameter ? is less than or equal to 150 fFs/W, where the converter parameter ? is a total rated capacitance of the at least one capacitor of the power circuit divided by a product of the peak rated power output of the power electronics converter and a maximum switching frequency of the switching signals.

Abstract: With advanced compute capabilities and growing convergence of wireless standards, it is desirable to run multiple wireless standards, e.g., 4G, 5G NR, and Wi-Fi, on a single signal processing system. Automatic gain control (AGC) is a process of converging on a gain level for optimum signal reception considering the dynamic range of all the components in the receive chain, including analog and digital parts. For certain wireless standard such as Wi-Fi, AGC is required to complete within a short interval. Both RF and baseband gains have to be adjusted within this short time. Discloses in the present disclosure are embodiments of a high-speed and low pin-count interface between an RF circuit and a baseband circuit for AGC communication. The high-speed interface provides a light-weight serial protocol over one or more low-voltage differential signaling (LVDS) channels to meet a low-latency requirement for gain updates.

Abstract: Techniques are disclosed relating to detecting supply voltage events and performing corrective actions. In some embodiments, an apparatus includes sensor circuitry and control circuitry. In some embodiments, the sensor circuitry is configured to monitor supply voltage from a power supply and detect a load release event that includes an increase in the supply voltage that meets one or more pre-determined threshold parameters. In some embodiments, the control circuitry is configured to increase clock cycle time for operations performed by circuitry powered by the supply voltage during a time interval, wherein the time interval corresponds to ringing of the supply voltage that reduces the supply voltage and results from the load release event. In some embodiments, the disclosed techniques may reduce transients in supply voltage (which may avoid equipment damage and computing errors) and may allow for reduced voltage margins (which may reduce overall power consumption).

Abstract: A shift register unit, a gate driving circuit and a display device are provided. The shift register unit includes a bias control circuit. The bias control circuit is electrically connected to a pull-down node, a control clock signal terminal, and a bias voltage terminal, respectively, and is configured to control connection between the pull-down node and the bias voltage terminal under the control of a control clock signal provided by the control clock signal terminal; and the bias voltage terminal is configured to input a bias voltage signal.

Abstract: Disclosed is a method for low voltage broadband power line carrier communication; when transmitting a physical layer protocol frame, short preambles are first transmitted to undergo automatic gain control, channel estimation, coarse-grained frequency offset compensation, and symbol synchronization; and then long preambles are transmitted to undergo automatic gain control, channel estimation, fine-grained frequency offset compensation, and symbol synchronization. Compared with the scheme of only transmitting long preambles, the present disclosure combines transmissions of short preambles and long preambles, which thus may quickly and accurately implement frequency offset compensation, automatic gain control, symbol synchronization, and channel estimation without sacrifice of precision, thereby achieving quick convergence, reducing resource overheads and time overheads, and enhancing system performance.

Abstract: A system of multiple concurrent receivers is described to process multiple narrow bandwidth wireless signals with arbitrary bandwidth and center frequency separation. These multiple receivers may provide a downconverted signal at the baseband frequency to process signal bandwidth using the lowest power consumption while using fully modular signal processing blocks operating at the low frequency. The concurrent receivers may operate from a single high frequency amplifier and may be derived from a low impedance point to reduce loading and improve scalability. The center frequency and bandwidth of each of the channels as well as phases of each of the channels may be independently reconfigured to achieve scalability, and on-chip test and calibration capability.

Abstract: During operation of an analog filter having one or more filter stages is configured to operate in a first configuration. Configuring the analog filter to operate in the first filter configuration includes configuring one or both of i) a filter response of the analog filter and ii) a filter bandwidth of the analog filter. A first set of one or more direct current (DC) offset correction codes corresponding to the first filter configuration are retrieved from a memory. The one or more DC offset correction codes in the first set are converted to one or more first analog DC offset correction signals. While operating the analog filter configured in the first configuration, the one or more first analog DC offset correction signals are applied to the one or more filter stages of the analog filter.

Abstract: Provided is a method for transmitting a physical random access channel (PRACH) preamble in a wireless communication system. More specifically, the method performed by the UE includes generating a PRACH preamble sequence having a zero correlation zone (ZCZ) having a specific length based on a specific number-th root Zadoff-Chu sequence and a cyclic shift; and transmitting to a base station the PRACH preamble including the generated PRACH preamble sequence.

Abstract: An example receiver includes: a pad splitter circuit coupled to a pad, the pad splitter circuit configured to generate a first logic signal and a second logic signal; a wide-range receiver coupled to the pad splitter circuit to receive the first and second logic signals, the wide-range receiver comprising a combination of a first Schmitt trigger receiver and a second Schmitt trigger receiver; a control circuit coupled to the pad splitter circuit and the wide-range receiver; and a bias generator circuit coupled to the pad splitter circuit and the wide-range receiver.

Abstract: An electronic device is disclosed and includes a sensor module; an audio output module; and a processor configured to apply a preset DC offset to a sound signal provided to the audio output module based on a change in the internal pressure inside the electronic device, detected through the sensor module.

Abstract: An apparatus for testing, inspecting or screening an electronic device for electrical characteristics, modified or unmodified hardware, or firmware modifications including Malware, Trojans, improper versioning, and the like, includes a transmitting antenna positioned at a distance from the electronic device and a electromagnetic energy receiver or sensor for examining a resulting unintentional derived electromagnetic energy from the electronic device. The receiver collects unintentional RF energy components emitted by the device and includes a processor and executable instructions that perform analysis in a response to the acquired electromagnetic energy input. The characteristics of the collected RF energy may be compared with RF energy characteristics of an exemplary device. The analysis determines one of a modified, unmodified or score of certainty of discerned condition of the device.

Abstract: A receiver frontend having a high-frequency AC-coupled path in parallel to a low-frequency feed-forward path for baseline correction. The low-frequency path blocks the DC common-mode voltage of the input differential signal pair, but passes low-frequency differential signal components (e.g., long strings of a single value, or disparities in the number of 1's and 0's over a long period of time.) The low-frequency path can include a passive network for level shifting and extending the range of acceptable common-mode input voltages. The low-frequency path can also include a differential (e.g., transconductance) amplifier to isolate the common-mode input voltage from the output of the baseline wander correction circuit.

Abstract: A system of multiple concurrent receivers is described to process multiple narrow bandwidth wireless signals with arbitrary bandwidth and center frequency separation. These multiple receivers may provide a downconverted signal at the baseband frequency to process signal bandwidth using the lowest power consumption while using fully modular signal processing blocks operating at the low frequency. The concurrent receivers may operate from a single high frequency amplifier and may be derived from a low impedance point to reduce loading and improve scalability. The center frequency and bandwidth of each of the channels as well as phases of each of the channels may be independently reconfigured to achieve scalability, and on-chip test and calibration capability.

Abstract: A method of calibrating a transceiver circuit including transmission circuitry for processing an input signal to produce an output signal including the input signal modulated onto a carrier signal, and reception circuitry arranged to take a modulated signal including a signal modulated onto a carrier signal and to output the signal demodulated from the carrier signal. The method includes: selectively coupling the transmission circuitry to the reception circuitry; introducing a reference signal into the transmission circuitry, the reference signal causing a plurality of components of different frequencies to be present in a calibration signal in the reception circuitry; measuring the power, and typically the received signal strength indication (RSSI) of the calibration signal including the plurality of components; and adjusting operation of the transmission and reception circuitry to increase the amplitude of a first set of the components relative to the amplitude of a second set of the components.

Abstract: A mobile communication system. The system has a housing comprising an interior region and an exterior region and a processing device provided within an interior region of the housing. The system has an rf transmit module coupled to the processing device, and configured on a transmit path. The system has a transmit filter provided within the rf transmit module. In an example, the transmit filter comprises a diplexer filter comprising a single crystal acoustic resonator device.

Abstract: An integrated electron spin resonance (ESR) circuit chip includes a chip substrate, a transmitter circuit, and a receiver circuit. The transmitter circuit and receiver circuit are disposed on the chip substrate. The transmitter circuit includes an oscillator circuit configured to generate an oscillating output signal and a power amplifier (PA) circuit configured to generate an amplified oscillating output signal based on the oscillating output signal. The receiver circuit receives an ESR signal from an ESR probe. The receiver circuit includes a receiver amplifier circuit configured to generate an amplified ESR signal based on the received ESR signal, a mixer circuit configured to receive the amplified ESR signal and to down-convert the amplified ESR signal to a baseband signal, and a baseband amplifier circuit configured to generate an amplified baseband signal based on the baseband signal.

Abstract: A random access method and random access system for a terminal in a high-speed mobile environment are provided. Wherein, the method comprises: selecting a random access preamble format according to a preset cell coverage radius target value; judging whether using a restricted set of cyclic shift quantities pre-configured satisfies a requirement of the cell coverage radius target value under the selected random access preamble format; if not satisfying, selecting a cyclic shift quantity which satisfies the requirement of the cell coverage radius target value from a unrestricted set of the cyclic shift quantities pre-configured; and generating a random access signal according to the cyclic shift quantity and a pre-configured mother code, and performing access using the random access signal. Through the above-mentioned technical scheme, the embodiment of the present document provides a more perfect random access method and random access system for a terminal in a high-speed mobile environment.

Abstract: Systems and methods for providing offset calibration for low power and high performance receivers are described herein. In one embodiment, a method for offset calibration comprises inputting a first voltage to a first input of a sample latch, and inputting a second voltage and an offset-cancellation voltage to a second input of the sample latch. The method also comprises adjusting the offset-cancellation voltage, observing an output of the sample latch as the offset-cancellation voltage is adjusted, and recording a value of the offset-cancellation voltage at which a metastable state is observed at the output of the sample latch. The method may be performed for each one of a plurality of different voltage levels for the first voltage to determine an offset-cancellation voltage for each one of the voltage levels.

Abstract: A unified balun low noise amplifier (LNA) and I/Q mixer is provided as a single-chip design, and includes a passive/active gain-boosted balun-LNA-I/Q-mixer (blixer), a filter section and a buffer amplifier. The filter section includes an IF-noise-shaping transistorized current-mode lowpass filter sharing a common power supply with the blixer, which allows the blixer and lowpass filter to draw a single bias current. The filter section also includes a complex-pole load providing image rejection and channel selection.

Abstract: In an embodiment, a system for measuring high frequency response of a DUT having improved power leveling includes a signal source, a modulator, an upconverter, and a leveling loop having dynamic gain adjustment. The signal source generates a test signal and the modulator modulates the amplitude of the generated test signal to target a requested power. The converter multiplies a frequency of the test signal. The leveling loop is configured to detect an intermediate frequency (IF) signal generated in response to the upconverted test signal. Modulation of the amplitude of the generated test signal by the modulator is adjustable based on the IF signal detected by the leveling loop.

Abstract: A demodulator for a Bluetooth receiver includes an oversampling module configured to oversample input symbols a first plurality of times to generate a first plurality of oversampled input symbols. A correlating module is configured to correlate a second plurality of adjacent samples of the first plurality of oversampled input symbols with corresponding symbols in a predetermined enhanced data rate (EDR) sync word. Based on the correlation, the correlating module is configured to selectively generate a sync signal indicating that EDR sync has occurred. The second plurality of adjacent samples comprises more samples than one and less than all of the first plurality of oversampled input symbols.

Abstract: The present invention concerns a method and associated apparatus for reducing the time required to scan an incoming satellite transmission power spectrum for available signals and to determine the characteristics of those signals. The frequency range of interest is scanned in narrow slices to determine approximate input power within each slice. Center frequencies and symbol rates of individual transponders are then estimated based upon these input power approximations.

Abstract: A digital circuit includes at least one input node, a biasing circuit, and a digital baseband circuit. The input node receives a digital signal including samples at a plurality of sample instances, the samples including a positive sample and a negative sample and represented by first plurality of bits. The biasing circuit generates a biased digital signal by adding a bias value to the digital signal so as to change the positive sample and the negative sample to first sample and second sample respectively and represented by second plurality of bits. The digital baseband circuit is configured to receive and process the biased digital signal such that reduced current consumption is realized based on a number of bit toggles in the second plurality of bits being less than a number of bit toggles in the first plurality of bits.

Abstract: A novel and useful reconfigurable superheterodyne receiver that employs a 3rd order complex IQ charge-sharing band-pass filter (BPF) for image rejection and 1st order feedback based RF BPF for channel selection filtering. The operating RF input frequency of the receiver is 500 MHz to 1.2 GHz with a varying high IF range of 33 to 80 MHz. The gain stages are inverter based gm stages and the total gain of the receiver is 35 dB and in-band IIP3 at mid gain is +10 dBm. The NF of the receiver is 6.7 dB which is acceptable for the receiver without an LNA. The architecture is highly reconfigurable and follows the technology scaling.

Abstract: A method of calibrating data slicer-latches in a receiver to remove offset errors in the slicer-latches. A known voltage is applied to all but one of the inputs of the slicer-latch. The remaining input receives an offset cancelation voltage from a DAC is stepped upward from a minimum voltage until the slicer-latch output transitions by incrementing a codeword to the DAC and the codeword that resulted the transition is saved. Then the offset cancelation voltage is swept downward in steps from a maximum voltage until the slicer-latch output transitions and the codeword that caused the transition is averaged with the stored codeword. The average of the codewords is applied to the DAC to generate the offset cancelation voltage used during normal operation of the receiver.

Abstract: Techniques are presented herein for distinguishing between the DC component of a real signal and DC energy of a received signal due to the radio receiver circuitry. Samples are obtained of a received signal derived from output of a receiver of a communication device. A mean of the samples is computed over a sample window comprising a predetermined number of samples. First and second thresholds are provided, the first threshold being greater than the second threshold. An absolute value of the mean is compared with respect to the first threshold and the second threshold as samples are obtained in the sample window. A selection is made between the first threshold and the second threshold for purposes of comparison with the absolute value of the mean to determine whether energy at DC is a true/real DC component of the received signal or is due to circuitry of the receiver.

Abstract: A method and apparatus is disclosed to restrict the delivery of video, audio, and/or data to unauthorized end users in a satellite communications system. The satellite communications system includes one or more satellite receiving antennas, commonly referred to as a satellite dish, to receive downlink communications signals from one or more satellites. The transmission received by the one or more satellite receiving antennas is converted by an outdoor unit (ODU) for transmission to one or more indoor units (IDUs). The ODU receives control information from one or more satellites from the downlink communications signals, commonly referred to as in-band, and/or from out-of-band communications signals. The ODU may use the control information to restrict access to one or more communications channels embedded within the downlink communications signals to the unauthorized end users.

Abstract: A digital receiver includes a radio frequency analog front end, a digital processing unit, a plurality of cascaded amplifier stages configured to receive output of the radio frequency analog front end, a first analog to digital converter configured to convert an analog signal output from the plurality of cascaded amplifier stages into a digital signal output to the digital processing unit, a first received signal strength indicator unit configured to receive outputs of each of the plurality of cascaded amplifier stages and output signal to the digital processing unit, a second received signal strength indicator unit configured to receive output of at least one amplifier stage in the plurality of cascaded amplifier stages, and a received signal strength indicator detection unit configured to activate and to deactivate digital units according to a comparison of output from the second received signal strength indicator unit to a predetermined threshold.

Abstract: The present invention provides a method and an apparatus for eliminating direct current offset.

Abstract: An apparatus for processing signals, in particular physiological measuring signals, is provided with a number of channels with main signal inputs for receiving input signals. Each of the input signals has a specific signal component and a signal component common to all input signals. Each channel is provided with an impedance transforming input amplifier. The apparatus supplies a respective input signal to the first input of each input amplifier and an analog reference signal, which is equal for all channels, to the second input. The apparatus includes a digital signal processor and one or more analog-digital converters for supplying the signals provided by the input amplifiers to the digital signal processor. The signal processor converts signals received from the one or more analog-digital converters at least into one or more output signals.

Abstract: An apparatus for repeating signals includes a receive antenna for capturing a receive signal, processing circuitry for processing the receive signal to form a repeated signal, and a transmit antenna for transmitting the repeated signal. The processing circuitry includes gain circuitry for gain in the repeated signal and decorrelation circuitry configured for modifying the repeated signal with respect to the receive signal to thereby decorrelate the repeated signal from the receive signal. The processing circuitry further comprises circuitry configured for calculating a gain margin for the apparatus utilizing the decorrelated receive and repeated signals.

Abstract: A method of operation of a wireless communication system includes: receiving a received signal; generating concurrently a first modulation data and a second modulation data from the received signal; calculating an error energy for the first modulation data and the second modulation data; and removing a residual Direct Current (DC) offset from the received signal based on determining a minimum of the error energy for the first modulation data or the second modulation data.

Abstract: A receiver technique includes generating a DC offset compensation signal based on a frequency offset-compensated received signal and a frequency offset indication signal. The technique includes generating a DC offset-compensated received signal based on the DC offset compensation signal and a received signal. The frequency offset-compensated received signal may be generated using a first Coordinate Rotation DIgital Computer (CORDIC) responsive to the DC offset-compensated received symbol and the frequency offset indication signal. The DC offset compensation signal may be generated using a second CORDIC responsive to the frequency offset indication signal and a real-valued signal.

Abstract: A mechanism for blind estimation of parameters for correcting I/Q impairments. Complex samples of a complex baseband signal are received from a receiver. A cross-correlation is computed between an I component and a Q component of the complex samples. A mean square value is computed for the I component of the complex samples; and a mean square value is computed for the Q component of the complex samples. A cross-channel gain estimate is: computed based on the cross-correlation value and one or both of the mean square values; and used to apply a cross-channel gain correction to the complex samples. An estimate of an I/Q gain imbalance is computed based on the mean square values. The gain imbalance estimate is useable to correct an I/Q gain imbalance present in the complex samples. The parameters may be supplied to the receiver, enabling the receiver to apply online corrections.

Abstract: A bias current utilized in a unit of a radio frequency (RF) receiver device of a network interface is controlled. A modulation scheme utilized in a packet being received by the network interface is determined. It is determined, based on the determined modulation scheme, whether a level of the bias current should be changed. When it is determined that the level of the bias current should be changed, a control signal to change the level of the bias current is generated.

Abstract: A direct-conversion type wireless receiver includes a pair of mixers for frequency-converting a radio signal received from an antenna into a base band signal by local signals having different phases; a first amplification circuit for amplifying the base band signal up to a demodulation level; a second amplification circuit provided between the mixer and the first amplification circuit; and a variable current circuit including a multi-stage current mirror to add a current 2n times as high as a reference current. The wireless receiver further includes a control unit configured to correct a DC offset of the mixer by allowing a current to flow into the second amplification circuit from the variable current circuit, based on an output of the first amplification circuit, and a capacitor connected between a gate and a source of a PchMOSFET which allows the reference current to flow therethrough.

Abstract: A mechanism is provided for dynamically adjusting DC offset at the time of deviation from DC balance ½ (DC level) in a data pattern including long-period consecutive bits generating DC offset in a section of data. A receiver circuit unit of an LSI having a serializer/deserializer arrangement for performing high-speed serial transmission includes an offset adjusting circuit. The offset adjusting circuit calculates DC balance in an arbitrary section of data by averaging received serial data. Based on comparison between a DC level and the DC balance obtained by averaging the received data, offset is shifted toward the H side when the DC balance exists on the H side from the DC level, and shifted toward the L side when the DC balance exists on the L side.

Abstract: Some embodiments of the invention relate to a DC offset correction circuit comprising a feedback loop having a DAC controlled by a reconfigurable ADC, which determines (e.g., tracks) the mean value of a modulated input signal. The circuit operates according to two phase process. In a first “pre-modulation” tracking phase, an input signal is tracked by the ADC, which is configured to output the input signal's mean value as a digital code equivalent to the input mean value. The output of the ADC is provided to a DAC, which provides an analog representation of the mean value to an adder that subtracts the mean value from the modulated input signal to generate a bipolar adjusted input signal. In a second “modulation” phase, the estimated mean value is held constant, so that the bipolar adjusted input signal may be provided to an activated modulation circuit for improved system performance.

Abstract: Provided is a pulse receiver capable of receiving a burst signal and decoding the burst signal with a bit error rate reduced to a target value or less by controlling a determination threshold such that decoding success rate is equal to or less than a predetermined value. A decode unit 140 decodes a pulse train 20 to information 30, counts the number of decoding successes for a predetermined time period and outputs the counted number (decoding success rate DR) to a control unit 150. The control unit 150 uses as a basis the decoding success rate DR communicated from the decode unit 140 to control the set value of reference voltage Vth used in the comparator 130.

Abstract: A Bluetooth receiver comprises a RF front end configured to receive a Bluetooth signal including a preamble and 34-bit pseudo-number (PN); a DC estimator communicatively coupled to the RF front end; and a frame synchronizer communicatively coupled to the DC estimator. The DC estimator is configured to perform DC offset estimation by determining an average value of samples of the preamble and the frame synchronizer is configured to use the 34-bit PN for frame synchronization.

Abstract: The voltage regulator device has a wide band amplifier having an input reference voltage, Vref and an input feedback voltage, Vfbk. The device has a source follower coupled to the wide band amplifier, the source follower coupled to an output of the wide band amplifier. The device has a VDD source, a regulator output, and a current source coupled to the source follower and the VDD source. The device has a low frequency path comprising a first transistor. The first transistor has a first gate, a first source, and a first drain. The first source is coupled to the VDD source. The first gate is coupled to a slow node, and the first drain is coupled to the regulator output. The low frequency path comprises a RC network, which has a capacitor, a resistor, and the slow node configured between the resistor and the capacitor. The device has a high frequency path comprising a second transistor. The second transistor has a second gate, a second source, and a second drain. The second source is coupled to the VDD source.

Abstract: The present invention relates to a digital front end receiver using a DC offset compensation scheme. The digital front end receiver includes a DC offset compensation filter configured to remove DC offset components from signals received from a digital mixer and a Cascaded Integrator-Comb (CIC) decimation filter configured to reduce a sampling rate of the signals received from the DC offset compensation block.

Abstract: A method for estimating an unwanted component that a receiver introduces into a signal at a known frequency, the method comprising applying a frequency offset to a signal, which comprises a wanted component at the known frequency, to form an offset signal having a frequency spectrum in which the wanted component is not positioned at the known frequency, processing the offset signal in the receiver and estimating a component positioned at the known frequency in the frequency spectrum of the processed signal.

Abstract: A device and method for solving problems of the prior art in which channel information as well as a DC offset is removed when removing the DC offset using a feedback signal of a baseband amplifier is provided. The device includes a DC offset correcting unit for removing the DC offset using an HPF function and controlling a feedback path according to a control signal to stop the HPF function and a signal generator for generating the control signal for controlling the HPF function, wherein the control signal is a signal for controlling formation and cutting-off of the feedback path.

Abstract: Embodiments of user equipment and methods for determining IQ imbalance parameters are described. In some embodiments, a method for determining in-phase (I) and Quadrature (Q) imbalance (IQ imbalance) parameters based on a known signal in a dual-carrier receiver using at least one controllable frequency offset includes receiving a known signal modulated onto a first radio frequency (RF) carrier frequency and a second RF carrier frequency different than the first RF carrier frequency. The known signal is downconverted to a baseband signal for the carriers by conversion from the respective RF carrier frequencies to an intermediate frequency (IF) using a common RF local oscillator (LO) and by further conversion from IF to baseband using carrier specific IF LOs, where a controllable frequency offset is used. Any controllable frequency offset is removed from the baseband signal for the first and second carriers to produce representations of the received signals.

Abstract: A receiver termination circuit includes an internal AC coupling capacitor and an adjustable resistor forming an adjustable high-pass filter (HPF) at a receiver side of a transmission medium, and a digital-to-analog converter (DAC) coupled to the adjustable HPF, the DAC configured to provide a signal having a low-pass filter response to the adjustable HPF to provide a DC restore function.

Abstract: A method of generating inphase and quadrature signals from a polar receiver providing a phase derivative signal and an envelope magnitude signal comprising receiving an estimated phase derivative signal; generating an estimated phase signal; mapping the estimated phase signal to an angular value; converting the estimated phase signal to an inphase signal and a quadrature signal based on the angular value; and, providing the inphase signal and quadrature signal to a demodulation circuit.

Abstract: A method for DC offset cancellation includes defining, in a range of possible gain values for operating a direct conversion receiver, multiple sub-ranges of the possible gain values. Multiple DC offset correction values for the respective sub-ranges are stored in a memory. Upon detecting at the receiver that a gain of the receiver has changed from a first sub-range to a second sub-range, DC offset cancellation is initiated based on a DC offset correction value stored for the second sub-range and on a condition relating to past operation in the second sub-range.