Abstract: A method for adjusting a DC offset slice point in an RF receiver is provided and may comprise estimating DC offset using a combination of fast tracking of an input signal and slow tracking of an input signal. If both are used, the fast tracking may be executed prior to executing the slow tracking. The fast tracking may acquire synchronizing signals transmitted before a payload. Additionally, noise tolerance may be increased in the fast tracking and the slow tracking by using tracking envelopes. The fast tracking may average acquisition envelopes and tracking envelopes using a fast tracking weighting factor to a sum of the acquisition envelopes and a slow tracking weighting factor to a sum of the tracking envelopes. Additionally, the slow tracking may average the tracking envelopes.

Abstract: A method and system for dynamic call type detection for circuit and packet-switched networks. A network endpoint, such as a gateway, will receive an incoming signal and make an examination of the signal to detect characteristics of the signal. Upon detection of a characteristic of the signal, the gateway will generate a data packet, identifying the characteristic, and send the packet to a receiving network endpoint. The initial gateway will continue to examine the incoming signal and continue to send packets identifying characteristics of the signal as more characteristics are detected. The receiving gateway may then begin reproducing the signal in part by generating a signal that has the characteristics as indicated by the data packets. Once the initial gateway no longer receives the incoming signal, and determines that an event has occurred, the gateway will send a packet to the receiving gateway to inform it of the event.

Abstract: Systems and methods for DC offset correction in analog and digital direct conversion RF receivers. A time derivate and subsequent integration of in-phase and quadrature phase signal path components is performed to effectively remove DC offset from the resultant down converted baseband signal.

Abstract: In a data processing apparatus and a data processing system including the same, the data processing apparatus includes a clock signal generation unit configured to receive a data signal comprising a preamble signal, information about DC balance codes for DC balance, an embedded clock signal between the DC balance codes, and information about serialized valid data, to generate a synchronous clock signal that is synchronized with the serialized valid data based on the data signal, and to generate at least one sample clock signal based on the synchronous clock signal; and a data processor configured to deserialize the serialized valid data based on the at least one sample clock signal, to decode deserialized data based on the DC balance codes, and to output decoded data.

Abstract: A dynamic DC offset removal apparatus and a dynamic DC offset removal method capable of accurately estimating a change position of a dynamic DC offset and a DC offset value before the change and a DC offset value after the change, thereby carrying out equalization processing on a reception signal whose dynamic DC offsets are removed, and improving a bit error rate characteristic.

Abstract: Systems and methodologies that enable implementing a complete period of frequency domain pseudo random/pseudo noise (PN) sequences, wherein the PN sequences satisfy predetermined requirements or relations. Such requirements or relations include: (1) supplying substantially low time domain Peak-to-Average Ratio (PAR); (2) supplying perfect periodic autocorrelation (zero out-of-phase correlation); (3) supplying substantially perfect cross correlation for any pair of sequences; and (4) supplying sequence correlation in the frequency domain by performing additive operations only or addition and subtraction-only. Taken together, such features in a family of sequences facilitate efficient signal transmission (e.g., substantially low power usage).

Abstract: A system for and method of detecting interference in a communication system. In an embodiment, a receiver acquires a communication signal, the communication signal comprising a carrier signal and an in-band interference signal. A signal processor conditions the communication signal and extracts the in-band interference signal without interrupting the carrier signal to form an error signal. The error signal is representative of the in-band interference signal. The signal processor is further configured to process the error signal to obtain one or more spectral properties of the error signal in a manner suitable for display.

Abstract: A method and arrangement for estimating a DC offset for a signal received in a radio receiver. The received signal includes a digitally modulated signal component, a DC offset component, and a noise component. When the signal is of a known type, such as a Gaussian Minimum Shift Keying (GMSK)-modulated signal with constant amplitude in a GSM/EDGE cellular radio system, the method exploits the known characteristics of the statistical distribution for the known type of signal to obtain a better estimate of the DC offset. The statistical distribution of the received digitally modulated signal component is first analyzed. That statistical distribution is then compared to the known statistical distribution for the known type of signal to identify differences. The differences are then used to estimate the DC offset. Additional iterations may be performed to further improve the DC estimate.

Abstract: A method may compensate for direct current (DC) offset in a radio frequency reception device. The method may include partitioning an analog portion of the reception device into a plurality of zones, for each zone, calibrating initial DC offset compensation to be applied within an operating range of a respective zone, the operating range of the other zones being limited to a threshold operating range, and determining DC offset compensation to be applied to the reception device throughout the operating range based on the basic DC offset compensations.

Abstract: A frequency demodulator comprises a frequency discriminator configured to generate a frequency modulation signal from frequency modulated signal, circuitry for generating a phase modulation signal from the frequency modulation signal, and a click reduction signal processing (CRSP) circuit operable to remove noise enhancements from the phase modulation signal caused by clicks. By first converting the frequency modulation signal to a phase modulation signal, noise enhancements caused by clicks are more readily distinguished from other noise in the phase modulation signal. After the noise enhancements have been removed by the CRSP, the frequency modulation is recovered substantially free of clicks. Removal of the clicks results in an improved output signal-to-noise ratio, thereby advantageously extending the onset of the threshold effect.

Abstract: The present invention relates to receiver equipment with AC-coupled receiver circuits and AC coupling filters. A switch connected between a first stage and a second stage among the receiver circuits is adapted to switch from a high coupling corner frequency, for rapid settling of a signal during preparation of data reception, to a low corner frequency, for low signal distortion during data reception. The receiver circuits are adapted to use known properties in the signal to perform the switch at a time when the short term DC-components of the signal are as low as possible.

Abstract: A receiver arrangement includes a single ended multiband feedback amplifier, at least one single ended input, differential output mixer arrangement including a main mixer and a trim mixer, and a mixer feedback loop circuit configured to receive differential output signals generated by the mixer arrangement. The mixer feedback loop circuit generates a feedback signal based on the received differential output signals and provides the feedback signal to the mixer arrangement to minimize DC-offset and second order intermodulation products. The single ended multiband feedback amplifier may include an input stage and a programmable resonance tank circuit connected to the input stage for suppressing downconverted noise from harmonics of the LO-frequency, and a configurable feedback net that shapes the frequency response of a feedback loop including the feedback net based on a band operation of the single ended multiband feedback amplifier.

Abstract: Disclosed is a wireless communication system, more particularly, a receiver and a chipset for DSRC.

Abstract: A communication system for transmitting and receiving a sequence of bits, and the methodology for transferring that sequence of bits are provided. The communication system includes a transmitting circuit and a receiving circuit. Within the transmitting circuit is a scrambler that comprises a shift register, an enable circuit, and an output circuit. The shift register temporarily stores n bits within the sequence of bits, and the enable circuit enables the shift register to store bits that arise only within the payload section of a frame. The output circuit includes a feedback, and several taps within the n stages to scramble logic values within the sequence of n bits output from the shift registers thus effectively preventing in most instances the sequence of bits from exceeding n number of the same logic value. Within the receiving circuit is a descrambler also having a shift register, an enable circuit, and an output circuit. The descrambler recompiles the scrambled data back to its original form.

Abstract: Certain aspects of a method and system for independent in-phase (I) and quadrature (Q) loop amplitude control for quadrature generators may include determining an amplitude voltage associated with an in-phase (I) component and a quadrature (Q) component of a generated signal. A DC reference voltage associated with the I component and the Q component may be determined. The determined amplitude voltage may be compared with the determined reference voltage to generate a control signal. The amplitude mismatch between the I component and the Q component may be compensated by controlling a biasing current of one or more programmable buffers associated with one or both of the I component and the Q component, based on the generated control signal.

Abstract: The invention relates generally to the field of wireless communications and more particularly to a method of and device for detecting the presence of a received data packet in a digital receiver. The present invention proposes a simplified method of correlation by removing dependency on the amplitude fluctuations while at the same time maintaining phase relevancy. The key advancement involves mapping the complex quadrature amplitude modulation (QAM) preamble to a quantized phase shift keying (PSK) constellation before application to a matched complex correlator. The proposed process essentially “amplitude normalizes” the input signal without the use or complexity associated with a divider. This simplified normalization scheme makes the packet detection algorithm robust against amplitude variations in the input signal, while still allowing for good correlation output.

Abstract: A receiver has a first input port and a second input port both coupled to a differential amplifier through first and second input capacitors. A bias circuit coupled to the core side of the first input capacitor and to the core side of the second input capacitor is configured to provide a selected voltage to at least one of the first input and the second input of the differential amplifier. In one embodiment, a common mode bias circuit provides a common mode voltage to both inputs of a differential amplifier. In a particular embodiment, a run length detector monitors the output of the differential amplifier and provides a run length feedback signal or an average bit density feedback signal to the set the selected voltage between periods of data reception.

Abstract: A wireless receiver includes a hardware (HW) block, a converter block and a digital signal processor (DSP). The HW block receives a wireless signal having a first DC Offset Component (DCOC), removes a portion of the first DCOC to produce a residual DCOC centered at DC, and generates parameters that estimate the residual DCOC. The converter block is coupled to the HW block and receives the residual DCOC centered at DC and converts it to a residual DCOC centered at IF. The DSP is coupled to the HW block and the converter block and receives the residual DCOC centered at IF from the converter block and the parameters from the HW block, and uses the parameters to eliminate the residual DCOC, and generate a baseband signal that is substantially free of the first DCOC and the residual DCOC.

Abstract: An antenna device that is placed adjacent to an antenna 5 for receiving a high frequency signal and includes an impedance matching circuit 6 and an amplifying circuit 21 to which a DC control voltage is supplied from a demodulating device 3 through a feeder cable 4 for transmitting the high frequency signal to the demodulating device 3, wherein the DC control voltage is set to a value for adjusting a frequency characteristic of the impedance matching circuit 6 within an allowable range corresponding to a received frequency. A small and inexpensive antenna device having a simple circuit configuration and good reception sensitivity is implemented.

Abstract: A wireless receiver includes a hardware (HW) block, a converter block and a digital signal processor (DSP). The HW block receives a wireless signal having a first DC Offset Component (DCOC), removes a portion of the first DCOC to produce a residual DCOC centered at DC, and generates parameters that estimate the residual DCOC. The converter block is coupled to the HW block and receives the residual DCOC centered at DC and converts it to a residual DCOC centered at IF. The DSP is coupled to the HW block and the converter block and receives the residual DCOC centered at IF from the converter block and the parameters from the HW block, and uses the parameters to eliminate the residual DCOC, and generate a baseband signal that is substantially free of the first DCOC and the residual DCOC.

Abstract: Baseband BB input units input baseband received signals. An initial weight data setting unit sets weighting coefficients to be utilized in the interval of a training signal as initial weighting coefficients. A gap compensating unit compensates control weighting coefficients with a gap error signal and outputs the updated weighting coefficients acquired as a result of the compensation. A weight switching unit selects the initial weighting coefficients in the interval of the training signal and selects the updated weighting coefficients in the interval of the data signal. Then the weight switching unit outputs the selected initial weighting coefficients and updated weighting coefficients as the weighting coefficients. A synthesizing unit weights the baseband received signals with the weighting coefficients and then sums them up.

Abstract: A high performance radio frequency receiver includes an isolated transconductance amplifier with large binary and stepped gain control range, controlled impedance, and enhanced blocker immunity, for amplifying and converting a radio frequency signal to multiple electrically isolated currents; a pulse generator for generating in-phase and quadrature pulses; a crossover correction circuit and pulse shaper for controlling a crossover threshold of the pulses and interaction between in-phase and quadrature mixers; and a double balanced mixer for combining the RF signal with the pulses to generate an intermediate frequency or baseband zero intermediate frequency current-mode signal. The intermediate frequency signal and second order harmonics may be filtered with a high frequency low pass filter and a current injected complex direct-coupled filter. IIP2 calibration of the in-phase and quadrature channels may be optimized using the isolated transconductance amplifier.

Abstract: A transceiver includes a switching unit configurable for isolating an input of a receiver from an output of a transmitter during a local calibration mode. A known signal present at the output at a first power level during the calibration mode will also be present at the input at a second power level lower than the first power level and will be converted by the quadrature demodulator. A compensation factor is estimated for compensating the receiver section for imbalances in the in-phase and quadrature phase signals resulting from conversion of the known signal. Remote calibration is implemented using a method for remotely compensating for I-Q imbalance wherein a data packet having a known signal is transmitted to a receiver for conversion by a quadrature demodulator and compensation factors are estimated for compensating for imbalances in the in-phase and quadrature phase signals resulting from conversion of the known signal.

Abstract: A system and method are provided for compensating for an I/Q mismatch of either a direct conversion transmitter or a direct conversion receiver based on known short training symbols of a Short Training Sequence (STS) of packets transmitted according to the IEEE 802.11a or 802.11g standard. To compensate for an I/Q mismatch of a direct conversion transmitter, a packet including the STS is transmitted. Due to the I/Q mismatch of the direct conversion transmitter, the transmitter distorts the packet to provide a distorted packet including a distorted STS. Based on one or more short training symbols of the distorted STS and a known ideal short training symbol, a distortion matrix is determined. Subsequent packets transmitted by the direct conversion transmitter are pre-distorted based on the distortion matrix. Compensation of the I/Q mismatch of a direct conversion receiver may be performed in a similar fashion.

Abstract: A DC offset correction circuit includes a DC offset detector generating a detection voltage based on a result of a comparison of a first reference voltage and a voltage difference between signals input to the DC offset detector, a comparator comparing a second reference voltage and the detection voltage and a third reference voltage and the detection voltage and outputting first and second comparison signals, respectively, as a result of the comparisons, and an up/down counter performing an up or a down count operation in response to one of the first or second comparison signals and, as a result of the up or down count operation, outputting a signal that causes at least one control signal for canceling a DC offset in a signal input to a receiver to be generated.

Abstract: A method and apparatus are disclosed for detecting a synchronization mark in a received signal. The received signal is processed to compensate for a DC bias in the received signal, such as subtracting an average of a block of received samples from each sample in the block. A distance metric, such as a sum of square differences, is computed between the DC compensated received signal and an ideal version of the received signal expected when reading the synchronization mark. The synchronization mark is detected if the distance metric satisfies predefined criteria. The ideal version of the received signal can optionally be processed to compensate for a DC bias in the synchronization mark. A search for the synchronization mark search can be limited to time cycles that match a known phase.

Abstract: A method of simultaneously determining a DC offset and a channel impulse response from a received signal in a mobile communication system. The received signal Y comprising a set of training sequence bits that have been modulated prior to transmission. The modulated signals experience a certain phase shift and are rotated by a certain angle. The received signal may also comprise a DC offset component ADC that needs to be removed. By manipulation of the received signal samples with the knowledge of the original training sequence TRS and method of modulation used, it is possible to simultaneously estimate the communication channel's impulse response H and the DC offset ADC by finding the Least Square solution to a linear equation, such that the energy of the noise term introduced into the communication channel may be kept to a minimum.

Abstract: A translating bi-directional packet repeater includes a first antenna and a second antenna for receiving a wireless signal, amplifying it, and retransmitting it on a different channel. The channel associated with each of the antennas is separated in frequency sufficiently to ensure good isolation between the wireless signals that are received and then retransmitted. The wireless signal is down converted to an intermediate frequency (IF) that is passed through a band pass filter, and the filtered signal is then up converted and retransmitted on the different channel. A controller responds to a wireless signal on one of the antennas in selecting a path through the bi-directional amplifier and the antennas used to receive and retransmit the signal. The isolation between the received wireless signal and the retransmitted wireless signal is sufficient to avoid interference, and the retransmission takes place almost instantaneously to minimize the delay incurred.

Abstract: A method of determining a DC offset in a communications signal received via a communications channel, the communications signal comprising a sequence of training symbols. The method comprises providing a channel estimate of the communications channel based on said sequence of training symbols; determining, based on the channel estimate, an estimate of a noise contribution introduced by the communications channel; and determining an estimate of the DC offset from the determined estimate of the noise contribution.

Abstract: Apparatus, methods, and systems are disclosed, including, for example, a data receiver to receive a calibration voltage and a reference voltage to calibrate the data receiver. The output of the data receiver is provided to a first ripple counter that counts the outputs from the data receiver and provides an output count. The ripple counter may count either ones or zeros. A second ripple counter counts the number of a clock signals over the same period of time. The output count is either multiplied by two or the count of clock signals is divided by two. A ripple comparator may then compare the outputs and adjust the reference voltage based upon the comparison results.

Abstract: A speed estimation method is provided, detecting relative speed of a transmitter and a receiver transmitting symbols by OFDM sub-carriers through a channel. First, a first correlation table is established, indicating conceptual relationships between the relative speed and the channel characteristic based on Doppler shift theory. Thereafter, channel characteristic caused by movement is estimated. The first correlation table is checked to determine the relative speed according to the estimated channel characteristic. The channel characteristic is a correlation value generated by auto-correlating received symbols with a delay factor. The first correlation table is established with a first delay factor, associating correlation values to a first plurality of presumed shift frequencies in view of the first delay factor. The first presumed shift frequencies scale from zero to a first maximum value, and the relative speed is proportional to the shift frequencies.

Abstract: An apparatus, method, and system for providing dc offset reduction in a communications channel include a feedback loop to generate dc offset correction signals, which in turn are combined with an input analog signal and a processed digital signal thereby reducing dc offset. Each feedback loop may include an adaptive filter. At least one feedback loop may be responsive to an error signal that represents the difference between the delayed input of a first detector, and its output. Further, the dc offset correction signal, partially delayed, may be added to the error signal, thereby improving the response time of the dc offset correction loop.

Abstract: An integrated circuit and method of generating a bias signal for a data signal receiver is disclosed. One embodiment provides a replica circuit configured to generate a feedback signal, wherein the replica circuit is a replica of at least a part of a data signal receiver, and wherein the feedback signal depends on a reference signal of the data signal receiver. A compensation circuit is configured to compensate an influence of the reference signal on the feedback signal. An amplifier circuit is configured to generate a bias signal based on the feedback signal, the bias signal being provided to the data signal receiver.

Abstract: A receiving apparatus includes an amplification section that amplifies a received signal and a frequency conversion section that converts a frequency of the received signal, from a radio frequency to a baseband, the baseband having a lower frequency than the radio frequency. A gain control section amplifies, by a predetermined gain, the signal that has been subjected to the frequency conversion to the baseband. A voltage calibration section performs calibration on an offset voltage generated in the signal subjected to frequency conversion to the baseband. A time constant control section sets a first time constant during a reception operation and sets a second time constant, which is reduced with respect to the first time constant, during the calibration.

Abstract: The present invention provides a DC offset correction system for a wireless communication device that removes a DC offset from a baseband receive signal during “training time” when the baseband receive signal should ideally have no DC content. In general, the DC offset correction system includes multiple configurable feedback loops that operate to remove or cancel the DC offset from the baseband receive signal. One or more of the multiple configurable feedback loops is activated for a period of time during operation when it is known that the received signal should ideally contain no DC content. This training time varies depending on the particular communication standard being used by the wireless communication device. For example, the training time may be during reception of the preamble and header of an IEEE 802.11 packet.

Abstract: Improved DC cancellation in zero-IF receivers for eliminating the DC offset that otherwise would be caused by the AC voltage on a coupling capacitor at the time of switching from AC coupling to DC coupling. The coupling capacitor normally is connected first as a high pass filter to block any DC component, and then directly coupled as a direct or DC coupler. However any AC component of voltage on the coupling capacitor at the moment of switching normally remains as a DC offset. In accordance with the invention, the component of AC voltage on a coupling capacitor is tracked, and when switched to DC coupling, the component of AC voltage on the capacitor at the time of switching is held and subtracted from the signal path, thereby canceling the DC offset component that otherwise would be caused. Alternate embodiments are disclosed, including embodiments for accelerating capacitance charging for speed-up of the method.

Abstract: One or more parameters of a tuner of a receiver may be adjusted by generating for the receiver one or more control signals associated with one or more parameters and applying control signals to the tuner during a cyclic prefix (CP) period. The receiver may generate a control strobe in synchronization with the CP period wherein the control strobe essentially begins with the CP period and has duration preferably shorter than the duration of the CP period. The duration of the control strobe may be chosen such that the one or more control signals, after being applied to the tuner, each reaches its steady state before the CP period lapses. The adjusted parameters, alone or in combination, may be, for example, the gain of the low-noise-amplifier (LNA), the synthesizer's local frequency, the DC correction level, the power gain amplifier, and the I/Q error, and the like. The demodulator of the receiver may generate one or more of the control signals required for adjusting one or more parameters.

Abstract: A signal receiver circuit including a transmission gate, a pull-low unit, a boost capacitor, a voltage division unit, and a receiver unit is provided. The transmission gate determines whether to conduct an input signal according to a control signal. The pull-low unit determines whether to pull down the voltage at a terminal of the boost capacitor according to the control signal. The boost capacitor boosts the input signal of the receiver unit. The voltage division unit sends a divided voltage to another terminal of the boost capacitor according to the control signal. When an input signal is received, the boost capacitor boosts the input signal, for overcoming low current issue caused by high threshold voltage of MOS transistors and accordingly the receiver unit achieves full swing.

Abstract: A DC offset estimation system is disclosed. A DC offset estimation system includes a carrier frequency offset estimator receiving an input signal and estimating a carrier frequency offset value, a symbol timing recovery unit providing a symbol boundary of the input signal, and a DC offset estimator estimating a DC offset value to compensate the input signal based on the input signal, the carrier frequency offset value, and the symbol boundary.

Abstract: A method to perform DC compensation on a Radio Frequency (RF) burst transmitted between a servicing base station and a wireless terminal in a cellular wireless communication system that first receives the RF burst modulated according to either a first or second modulation format. Samples from the RF burst, or taken from the training sequence, are produced and averaged to produce a DC offset estimate. The DC offset estimate is then subtracted from each of the samples. The modulation format of RF burst may then be identified from the samples. Depending on the identified modulation format the DC offset estimate may be re-added to the samples when a particular modulation format is identified as the modulation format of the RF burst. This decision is made based on how well various components within the wireless terminal perform DC offset compensation.

Abstract: In a direct-conversion type orthogonal demodulator used in a multi-band receiver, influence to signal-receiving characteristics of the receiver, caused by DC offset drift produced when a band is switched to another, is reduced. In a multi-band receiver including a plurality of orthogonal demodulators each carrying out orthogonal demodulation for each of a plurality of band inputs, a switch which selects one of outputs transmitted from the orthogonal demodulators in accordance with a band-switching control signal and a high pass filter receiving an output transmitted from the switch, a cut-off frequency of the high pass filter is raised when a band is switched to another, to thereby shorten a convergent time of DC offset drift included in an output signal.

Abstract: A digital demodulation method for a quadrature amplitude modulated signal uses a phase locked loop to generate a local carrier signal. The phase locked loop uses a feedback signal derived from one or more demodulated signals of interest. The loop has a filter characteristic with a stop band within the information bandwidth(s) of the information signal(s). The preferred method generates an error signal from DC components of in-phase and quadrature-phase baseband signals. DC components are preferably isolated using a low-latency, AC rejection filter.

Abstract: A method for correcting I/Q imbalance in a received signal is disclosed. The method includes the steps of grouping (202) the received signal into a predetermined number of clusters, and determining (204) at least one coefficient value by feeding the predetermined number of clusters into a nested loop. The method further includes computing (206) a compensation value based on the at least one coefficient value, and correcting (208) the I/Q imbalance in the received signal by using the compensation value.

Abstract: A system and method for compensating for DC offset and/or clock drift on a wireless-enabled device is described. One embodiment includes a radio module, an A/D converter connected to the radio module, a DC tracking loop connected to the A/D converter, and a multi-hypothesis bit synchronizer.

Abstract: The present invention relates to a method and a corresponding device for embedding a secondary information signal in a channel data stream of encoded primary information signal. In order to make it more difficult for unauthorized persons or devices to retrieve the location of storage of the secondary information signal or its content itself a device is proposed according to the present invention comprising: an encoder (1) for encoding said primary information signal into a channel data stream, a control unit (3) for controlling the DC content of said channel data stream, a secondary information signal embedding unit (2) for embedding said secondary information signal in said channel data stream by using freedoms in the DC control, and an adaptation unit (4) for adapting the DC control by making non-optimal, arbitrary or random choices of the DC control at a number of locations of said channel data stream.

Abstract: A read channel component of a magnetic recording system employs equalization of a signal received from the magnetic recording channel, the equalization being modified depending upon the presence or absence of DC shifts in the signal. Equalization corrects for DC shifts, if present, prior to detection and decoding of servo data, such as servo address mark (SAM) and Gray code data. In a first implementation, a DC shift detector detects the presence or absence of DC shifts and modifies equalization in a predetermined manner. In a second implementation, filtering is applied to the signal to enhance equalization in the presence of DC shift, and both filtered and unfiltered signals employed for detection of the servo data.

Abstract: An integrated circuit (IC) includes at least one baseband section, at least one radio frequency (RF) section, and an interface module. The interface module is operable to couple the at least one baseband section to the at least one RF section, wherein the interface module includes an analog interface module and a digital interface module.

Abstract: The dynamic DC offset canceling apparatus includes: section 104 that detects dynamic DC offset in longest overlapping part sequences from the differences between the sampling values of a first longest overlapping part sequence and the sampling values of a second longest overlapping part sequence, the first longest overlapping part sequence and the second longest overlapping part sequence being overlapping part sequences in a training sequence of the received signal; section 105 that detects dynamic DC offset outside the longest overlapping part sequences from the difference between an average value of sampling values of a received signal which exists in a burst before the first longest overlapping part sequence, and an average value of sampling values of a received signal which exists in a burst after the second longest overlapping part sequence; and section 106 that adaptively subtracts a DC offset value from the received signal based on these results.

Abstract: There are provided a direct sampling type wireless receiver and a method using the same that reduce nonlinearity and DC offset by using a multi-port network and a carrier frequency direct conversion method with a low sampling rate of a direct sampling method in a wireless communication receiver.

Abstract: A method of transmitting information in a WLAN (Wireless Local Area Network) network and corresponding WLAN communication devices and integrated circuit chips are provided. A correction signal is used for compensating for a dc offset in a data signal containing at least part of the information to be transmitted. The correction signal is varied by making it taking different values. For each of the different values, a strength of an indicator signal indicative of the dc offset is determined. Based upon the determined strength, an optimum value of the correction signal is identified at which the dc offset is minimized. The value of the correction signal is set to the optimum value. Further, a method of transmitting information in a WLAN network is provided, including compensating for a first and second dc offset in a first and second data signal, respectively, using a first and second feedback loop, respectively.