Abstract: A DC offset estimator and removal circuit removes the DC offsets for each of the I and Q signal components in a received signal. A gain imbalance estimator and compensator circuit estimates and compensates for gain imbalances within the I and Q signal components. A phase imbalance estimator and compensator circuit estimates and compensates for phase imbalances within the I and Q signal components to produce a communications signal that is compensated for received DC offsets and gain and phase imbalances within the I and Q signal components.

Abstract: An apparatus includes a frequency mixer circuit configured to generate a baseband signal based on a local oscillator signal and a radio frequency signal. The apparatus includes a compensation circuit configured to generate a DC offset-compensated signal based on the baseband signal, a DC offset compensation signal, and a second signal. The DC offset compensation signal and the second signal have currents approximately equal in magnitude and opposite in direction. A current of the DC offset-compensated signal is substantially the same as a current of the baseband signal. The compensation circuit may include a DC digital-to-analog converter circuit configured to generate the DC offset compensation signal and the second signal based on a control signal.

Abstract: In one embodiment, a method of communicating data values over a three conductor interface is provided. Different data values are transmitted by generating and transmitting three respective signals to a receiver using three conductors. The first signal is maintained as a set voltage level. The second signal is alternated between a high voltage and a low voltage according to a carrier frequency. The third signal is alternated between the high and low voltages and is out of phased with the second signal. To transmit a first data value, the first signal is generated on a first conductor, the second signal is generated on a second conductor, and the third signal is generated on a third conductor. To transmit a second data value, the second signal is generated on the first conductor, the first signal is generated on the second conductor, and the third signal is generated on the third conductor.

Abstract: A signal receiving apparatus, applicable in a wireless system calibrating direct current offset, includes: an adjusting circuit arranged to receive an receiving signal having a first DC (Direct Current) signal, and adjust the first DC signal to generate the receiving signal having a second DC signal according to an adjusting signal; a first arithmetic circuit arranged to generate an error signal according to the second DC signal and a target DC signal; and a second arithmetic circuit arranged to calculate an error signal slope according to the error signal, and update the adjusting signal according to the error signal slope and the error signal.

Abstract: A receiver including a mixer configured to generate (i) a first output and (ii) a second output, a first capacitance coupled to the first output, and a second capacitance coupled to the second output, A controller is configured to program (i) the first capacitance and (ii) the second capacitance to a first capacitance value in response to operating the receiver in a first mode, and program (i) the first capacitance and (ii) the second capacitance to a second capacitance value in response to operating the receiver in a second mode. The first capacitance value determines one or more of (i) linearity, (ii) gain, and (iii) noise figure of the receiver in the first mode. The second capacitance value determines one or more of (i) linearity, (ii) gain, and (iii) noise figure of the receiver in the second mode.

Abstract: Methods and systems for split voltage domain receiver circuits are disclosed and may include amplifying complementary received signals in a plurality of partial voltage domains. The signals may be combined into a single differential signal in a single voltage domain. Each of the partial voltage domains may be offset by a DC voltage from the other partial voltage domains. The sum of the partial domains may be equal to a supply voltage of the integrated circuit. The complementary signals may be received from a photodiode. The amplified received signals may be amplified via stacked common source amplifiers, common emitter amplifiers, or stacked inverters. The amplified received signals may be DC coupled prior to combining. The complementary received signals may be amplified and combined via cascode amplifiers. The voltage domains may be stacked, and may be controlled via feedback loops. The photodetector may be integrated in the integrated circuit.

Abstract: A system including a first filter module and a second filter module. The first filter module is configured to (i) pass a first DC shift in an input signal and (ii) convert a second DC shift in the input signal to a first component and a second component. The first DC shift is shorter in duration than the second DC shift. The second filter module is configured to detect one or more of (i) the first DC shift and (ii) the first component and the second component of the second DC shift. In response to detecting one or more of (i) the first DC shift and (ii) the first component and the second component of the second DC shift, the second filter module is configured to filter one or more of (i) the first DC shift and (ii) the first component and the second component of the second DC shift.

Abstract: The disclosure relates to a receiver system that employs multiple instances of a DC compensation system to reduce DC offsets in a receiver path. The receiver has a receiver front end configured to receive an RF input signal and to operate on the RF input signal according to a plurality of receiver states to generate a baseband signal having a DC offset that is based upon the plurality of receiver states. A DC offset compensation circuit implements a plurality of instances of DC offset compensation components that respectively generate an estimated DC offset corresponding to a receiver state. A controller controls the receiver state of the receiver front end and operates the DC offset elimination circuit to selectively apply one of the plurality of DC compensation components to the corresponding baseband signal based upon the receiver state.

Abstract: A method includes receiving a signal using a direct conversion receiver, while the receiver is set at a gain that is selected from a range of possible gain values. Multiple DC offset correction values are provided for use by a DC offset cancellation loop, each DC offset correction value being associated with a respective sub-range of the range of the possible gain values. A DC offset correction value is selected from among the multiple DC offset correction values based on the gain to which the receiver is set. A DC offset in the signal is canceled by setting the DC offset cancellation loop to the selected DC offset correction value.

Abstract: A pre-processing unit for a signal processor includes a pre-processing element. The pre-processing element is configured to receive data to be processed by the signal processor, to pre-process the receive data and to output the pre-processed data. The data is pre-processed based on a control signal describing an undesired signal characteristic of a supply voltage for the signal processor in order to compensate an influence of the signal characteristic of the supply voltage on the processing of the data.

Abstract: In accordance with some embodiments, receivers for receiving a wireless data transmission are provided, the receivers comprising at least one amplifier that receives an RF input signal and produces at least one amplified signal; a mixer that mixes the at least one signal to produce a mixed signal; a filter that filters the mixed signal to produce a filtered signal, a comparator that compares the filtered signal to a threshold voltage and produces a digital signal, a first pulse generate i that generates a first pulse in response to a transition in the digital signal, a second pulse generator that generates a second pulse that is longer than the first pulse in response to a transition in the digital signal; and digital logic that generates a clock output and that generates a data output based on a state of the first pulse when the second pulse expires.

Abstract: A digital circuit includes at least one input node, a biasing circuit, and a digital baseband circuit. The input node receives a digital signal including samples at a plurality of sample instances, the samples including a positive sample and a negative sample and represented by first plurality of bits. The biasing circuit generates a biased digital signal by adding a bias value to the digital signal so as to change the positive sample and the negative sample to first sample and second sample respectively and represented by second plurality of bits. The digital baseband circuit is configured to receive and process the biased digital signal such that reduced current consumption is realized based on a number of bit toggles in the second plurality of bits being less than a number of bit toggles in the first plurality of bits.

Abstract: Methods and systems for split voltage domain transmitter circuits are disclosed and may include amplifying a received signal in a plurality of partial voltage domains. Each of the partial voltage domains may be offset by a DC voltage from the other partial voltage domains. A sum of the plurality of partial domains may be equal to a supply voltage of the integrated circuit. A series of diodes may be driven in differential mode via the amplified signals. An optical signal may be modulated via the diodes, which may be integrated in a Mach-Zehnder or a ring modulator. The amplified signals may be communicated to the diodes, connected in a distributed configuration, via even-mode coupled transmission lines. The partial voltage domains may be generated via stacked source follower or emitter follower circuits. The voltage domain boundary value may be at one half the supply voltage due to symmetric stacked circuits.

Abstract: A signal receiver having a gain control circuit comprising: detection means configured to form a representation of the excess amplitude during a training period of a signal received by the receiver; a first gain stimulus generator configured to generate a first gain stimulus in dependence on the excess amplitude detected by the detection means during the training period; averaging means configured to estimate the average of the signal received by the receiver during the training period; a second gain stimulus generator configured to generate a second gain stimulus in dependence on the average estimated by the averaging means during the training period; and a gain control signal generator configured to generate a gain control signal for the receiver in dependence on the first gain stimulus and the second gain stimulus.

Abstract: Systems and methods for measuring transmitter and/or receiver I/Q impairments are disclosed, including iterative methods for measuring transmitter I/Q impairments using shared local oscillators, iterative methods for measuring transmitter I/Q impairments using intentionally-offset local oscillators, and methods for measuring receiver I/Q impairments. Also disclosed are methods for computing I/Q impairments from a sampled complex signal, methods for computing DC properties of a signal path between the transmitter and receiver, and methods for transforming I/Q impairments through a linear system.

Abstract: A center frequency of an adjustable filter is controlled to achieve a compromise between DC offset rejection and image rejection.

Abstract: Embodiments provide a digital RF receiver including a signal converting unit which converts an RF signal received from an external device into a digital signal, a plurality of functional modules which processes the digital signal in accordance with a predetermined algorithm when the digital signal is input, and a signal processing controller which selects at least one of the plurality of functional modules to control the digital signal to be processed in consideration of whether an IF signal component is included in the digital signal or a sampling rate related with sampling information of the digital signal.

Abstract: A quadrature demodulator receiver unit (100) comprises a first filter unit (360) that may delay an intermediate signal x(t) whose real part is based on a sampled in-phase IF signal (xi(t)) and whose imaginary part is based on a sampled quadrature IF signal (xq(t)). A second filter unit (366) filters a conjugate complex version of the intermediate signal x(t). The filter coefficients of the filter units (360, 366) are determined using a calibration signal, for example on the basis of ratios of complex-valued spectral components of intermediate signals xcal(t) obtained from the calibration signal cal(t). The filtered signal and the delayed signal are recombined to obtain a compensated output signal y(t). The calibration signal may be supplied from an oscillator circuit supplying a signal for processing a receive signal of the receiver unit (100).

Abstract: A method includes receiving a signal using a direct conversion receiver, while the receiver is set at a gain that is selected from a range of possible gain values. Multiple DC offset correction values are provided for use by a DC offset cancellation loop, each DC offset correction value being associated with a respective sub-range of the range of the possible gain values. A DC offset correction value is selected from among the multiple DC offset correction values based on the gain to which the receiver is set. A DC offset in the signal is canceled by setting the DC offset cancellation loop to the selected DC offset correction value.

Abstract: In accordance with an example embodiment, there is disclosed herein an apparatus where transmitter operating parameters are adjusted based on channel condition data obtained from a transmitter and/or from a receiver communicating with the transmitter. For example, the transmitter's contention window may be increased responsive to determining channel occupancy at the receiver is increasing. As another example, aggregation/fragmentation may be adjusted based on channel occupancy at the receiver. Still another example, the data rate employed by the transmitter may be changed responsive to changes in receiver success count.

Abstract: A downconverter capable of being normally operated even in the case where a universal dual downconverter is made up by use of multiple downconverter circuits. The downconverter includes first and second downconverter circuits, and an amplification unit having at least a first amplifier LNA for receiving a horizontally polarized wave signal, and a second amplifier LNA for receiving a vertically polarized wave signal. If a Tone/Pola signal is a signal indicating a power-saving mode, a control circuit of the first downconverter circuit causes both a local oscillator and a frequency converter to be in a non-operating state, controlling a bias circuit such that power is supplied to the first amplifier LNA.

Abstract: Techniques are disclosed that involve the reduction of DC offsets. For instance, embodiments may receive a baseband signal, and determine a DC characteristic of the baseband signal. When the DC characteristic has a value that is outside of a predetermined range, a correction signal is adjusted. The correction signal is injected into the baseband signal.

Abstract: In accordance with the teachings described herein, systems and methods are provided for calibrating DC offset in a receiver. A DC calibration circuit may be used that is configured to remove DC offset from a digital multi-carrier modulated (MCM) signal that includes a sequence of MCM symbols. The DC calibration circuit may include an accumulator and a compensator. The accumulator may be used to determine an estimated DC offset of a current MCM symbol in the sequence of MCM symbols. The compensator may be used to remove the estimated DC offset from a next MCM symbol in the sequence of MCM symbols. The accumulator may also be used to receive a plurality of digital samples that comprise the current MCM symbol and to determine the estimated DC offset by calculating an average of the plurality of digital samples.

Abstract: A receiver architecture is disclosed which employs an RC double-sampling front-end and dynamic offset modulation technique. A low-voltage double-sampling technique provides high power efficiency by avoiding linear high-gain elements conventionally employed in typical transimpedance-amplifier (TIA) receivers. In addition, a demultiplexed output of the receiver helps save power in the subsequent digital blocks. Various applications are described including optical receivers, electrical on-chip interconnects, as well as pulse amplitude modulation. The receiver can be implemented in CMOS and is scalable and portable to other technologies.

Abstract: The present invention provides a method and an apparatus for eliminating direct current offset.

Abstract: There are provided a base band processor having a peak suppression function, a transmitter, and a method of transmitting a signal. The base band processor includes: a signal generating unit generating digital signals; a variable up/down sampling unit changing a sampling rate in real time according to a magnitude of signal bandwidth changed in real time and sampling the digital signals from the signal generating unit according to the sampling rate; a peak suppression processing unit detecting peak power of sampled signals from the variable up/down sampling unit for a respective section in which a peak exists and suppressing corresponding peak power according to the peak power of the respective section; and a signal converting unit converting the digital signals from the peak suppression processing unit into analog signals.

Abstract: An apparatus for receiving data in a communication system includes: a detection unit configured to calculate power values of a data packet and a ratio of the power values by using a preamble of the data packet in a received signal, and detect the data packet through the calculated ratio of the power values; a control unit configured to calculate a gain compensation value of the detected data packet, and perform an automatic gain control (AGC) on the detected data packet by using the gain compensation value; a compensation unit configured to calculate a DC offset in the received signal, and remove the DC offset from the received signal; and a demodulator configured to demodulate the AGCed data packet.

Abstract: A channel impulse response (CIR)/DC offset (DCO) joint estimation for a time division synchronous code division multiple access (TDSCDMA) system includes generating from a basic midamble and received midamble an initial estimation of the CIR as a series of CIR taps; storing the initially estimated CIR taps; calculating a DC compensated CIR from the initially estimated CIR taps; filtering out the noise from the DC compensated CIR to produce the CIR estimation; and calculating the DC offset estimation from the CIR estimation.

Abstract: A method (500) for estimating at least one offset in a subcarrier that is subject to distortion in a multicarrier communication system. The method comprises receiving a plurality of subcarriers wherein the plurality of subcarriers contain the subcarrier that is subject to the distortion; and generating a plurality of first channel estimates for a respective plurality of received subcarriers that are not subject to the distortion. The method further comprises processing a number of the plurality of first channel estimates for the respective plurality of received subcarriers that are not subject to the distortion to generate a second channel estimate for the subcarrier that is subject to the distortion; and estimating an offset associated with the subcarrier that is subject to the distortion.

Abstract: A communications system receiver incorporates a time-averaged DC component subtracter to subtract a time-averaged DC offset component from a received, processed signal. The time-averaged DC offset is selectably calculated from a moving average or a running average. The selection of the time-averaged DC offset can be done depending on whether the receiver operates in a frequency hop mode or not.

Abstract: Embodiments of a receiver for using a first oscillator signal provided by a crystal resonator to support multiple, different functionalities are provided. The receiver comprises a phase-locked loop (PLL) configured to provide a second oscillator signal based on the first oscillator signal provided by the crystal resonator; a first mixer configured to mix a received signal received over a first input path with the second oscillator signal received over a second input path to provide a first frequency-shifted signal; and an automatic frequency controller (AFC) configured to estimate a frequency offset of the second oscillator signal and adjust the PLL to compensate for the frequency offset. The receiver further can include solutions for mitigating potential sources of noise caused by the frequency of the first oscillator signal not being compensated for by the AFC.

Abstract: Receiver circuitry for processing a received Very Low Intermediate Frequency signal wherein the receiver circuitry comprises a main processing path. The main processing path comprises mixing circuitry arranged to mix a received VLIF signal with a frequency down conversion signal to produce a main path signal. The receiver circuitry further comprises a direct current cancellation path comprising mixing circuitry arranged to mix a DC element of the received VLIF signal with the frequency down conversion signal to produce a DC cancellation signal. The receiver circuitry still further comprises signal summing circuitry arranged to add the DC cancellation signal in anti-phase with the main path signal.

Abstract: An apparatus has demodulation circuitry to demodulate a radio frequency signal and produce a baseband signal, wherein the radio frequency signal comprises a periodic signal having a predetermined period. An analog-to-digital converter converts the baseband signal into a digital signal that comprises a periodic signal having the predetermined period. A first DC offset adjustment circuit estimates a DC offset contained in the digital signal based on digital samples in a sample period having a length equal to the predetermined period. A second DC offset adjustment circuit estimates the DC offset contained in the digital signal. A selection circuit selects one of the first DC offset adjustment circuit or the second DC offset adjustment circuit to be used to estimate the DC offset contained in the digital signal.

Abstract: A direct-conversion type wireless receiver includes a pair of mixers for frequency-converting a radio signal received from an antenna into a base band signal by local signals having different phases; a first amplification circuit for amplifying the base band signal up to a demodulation level; a second amplification circuit provided between the mixer and the first amplification circuit; and a variable current circuit including a multi-stage current mirror to add a current 2n times as high as a reference current. The wireless receiver further includes a control unit configured to correct a DC offset of the mixer by allowing a current to flow into the second amplification circuit from the variable current circuit, based on an output of the first amplification circuit, and a capacitor connected between a gate and a source of a PchMOSFET which allows the reference current to flow therethrough.

Abstract: Device for compensating a DC component inherent in any radio frequency chain in which from a single measurement, generally obtained from a digital stage, a set of multiple compensation values is determined by a compensation value vector generating module and which compensation values are applied to multiple compensation points of the analog chain. The compensation values are calculated by an iterative process converging toward cancellation of the DC component and avoid saturating amplification components and components of the analog-to-digital converter. The module includes compensation value calculation units each configured to calculate a respective compensation value and provide the calculated compensation value to the respective compensation point.

Abstract: Methods and systems for blocker and/or leakage signal rejection by DC bias cancellation are disclosed and may include undersampling a received signal including a desired signal and an undesired signal. A biasing current in the wireless system may be utilized to reduce a measured DC signal generated by the undersampling of the received signal. The received signal may be undersampled at a frequency of or an integer sub-harmonic of the undesired signal, which may include a leakage signal and/or a blocker signal. The DC biasing current may be controlled utilizing successive approximation, control logic and a digital to analog converter. The output DC voltage may correspond to said undesired signal, and the received signal may be undersampled utilizing a mixer.

Abstract: A ZIF direct-conversion OFDM receiver capable of estimating and correcting an I/Q imbalance in a baseband signal. A complex down-conversion is performed on a received signal r(t). The received signal r(t) is divided into an In-phase signal (I) and Quadrature-phase signal (Q). An I/Q imbalance is introduced by the local oscillator such that the I/Q imbalance includes an amplitude imbalance factor (?) and phase imbalance factor (?). The I and Q signals are amplified, filtered and digitized. The digitized I and Q signals are processed via a Fast Fourier Transform (FFT). An I/Q compensation algorithm estimates the values of the amplitude imbalance factor (?) and, the phase imbalance factor (?) based on a time expectation calculation. The imbalance factors are applied to the baseband signal to recover the signal of interest x(t). The OFDM receiver outputs the signal of interest x(t) to an information display device.

Abstract: In a dual-carrier, double-conversion Orthogonal Frequency Division Multiplexing (OFDM) receiver a frequency synthesizer generates a first local oscillator signal for the first down-conversions stage of the receiver. A frequency divider is used to derive a second local oscillator signal from the first local oscillator signal, thus eliminating the need for a separate frequency synthesizer for the second down-conversion stage. A controller determines the frequency of the first local oscillator signal and a divisor M to align subcarrier grids for said first and second baseband signals with DC.

Abstract: A communication system comprises a direct conversion receiver for correcting imbalance errors. The direct conversion receiver receives a radio frequency (RF) signal and converts the RF signal to baseband signals. The direct conversion receiver further translates the baseband signals to digital signals having a direct current (DC) offset and applies a DC offset correction to the digital signals having the DC offset to generate first DC offset corrected signals. An imbalance correction unit of the direct conversion receiver applies an imbalance correction to the first DC offset corrected signals by estimating an error between an average envelope of the first DC offset corrected signals and an average envelope of second DC offset corrected signals. The imbalance correction unit is fixed at initial imbalance parameter values. The direct conversion receiver further updates the initial imbalance parameter values of the imbalance correction unit based on the estimated error for correcting imbalance errors.

Abstract: Techniques are disclosed relating to reducing wander created by AC couplers. In one embodiment, an integrated circuit is disclosed that includes an AC coupler and a DC-level shifter. The AC coupler is configured to receive a differential input signal at first and second nodes, and to shift a common-mode voltage of the differential input signal. The DC-level shifter is coupled to the first and second nodes, and configured to reduce wander of the AC coupler. In various embodiments, the DC-level shifter is configured to supply a differential reference signal to the AC coupler, and to create the differential reference signal from the differential input signal at the first and second nodes by changing a common-mode voltage of the differential input signal.

Abstract: A procedure for compensating the DC component inherent in any radio frequency chain making it possible from a single measurement, generally located in the digital stage, to determine a set of multiple compensation values that must be applied to multiple compensation points of the analogue chain. The compensation values are calculated by an iterative process converging towards a cancellation of the DC component and avoid saturating amplification components and components of the analogue digital converter.

Abstract: In a data processing apparatus and a data processing system including the same, the data processing apparatus includes a clock signal generation unit configured to receive a data signal comprising a preamble signal, information about DC balance codes for DC balance, an embedded clock signal between the DC balance codes, and information about serialized valid data, to generate a synchronous clock signal that is synchronized with the serialized valid data based on the data signal, and to generate at least one sample clock signal based on the synchronous clock signal; and a data processor configured to deserialize the serialized valid data based on the at least one sample clock signal, to decode deserialized data based on the DC balance codes, and to output decoded data.

Abstract: Transmit IQ imbalance is calibrated and compensated for within a receiver. In at least one embodiment, a Multimedia over Coax Alliance (MoCA) Type II probe signal is transmitted from the transmitter to the receiver for use in performing transmit IQ imbalance calibration.

Abstract: A method and apparatus for decoding a baseband signal of a radio signal removes, from the baseband signal, low-frequency and long-term noise that increases the possibility of decoding errors. The removal of low-frequency and long-term noise is performed by accumulating differences between the actual signal levels of the baseband signal and the expected signal levels for the baseband signal and subtracting the accumulated difference from the baseband signal before decoding. In one scheme, the baseband signal contains a predetermined training sequence of signal levels, where the differences between the actual signal levels of the baseband signal and the expected signal levels for the predetermined training sequence are accumulated. At the end of the training sequence, the accumulated training sequence difference is used as the accumulated difference and subtracted from the baseband signal, thereby providing stable operation for decoding signal levels that follow the training sequence.

Abstract: A digital nonlinear adaptive mechanism for frequency offset compensation for use in a digital Frequency Shift Keying (FSK) receiver such as a Bluetooth GFSK receiver. The mechanism is intended to aid in the recovery of a frequency-modulated signal in the presence of an unknown additive frequency offset, which could be greater than the peak frequency deviation and which must be suppressed to enable proper data recovery in the receiver. The mechanism utilizes a demodulator to convert the frequency offset into a digitally represented DC level. This level is extracted by a non-linear estimator based on peak detectors and filters. Active suppression of the DC level is achieved by feed-forwarding the estimated value into a subtractor that removes it from the digital signal. A gear shift mechanism incorporated within the DC estimation block enables the dynamic control of the DC estimation process.

Abstract: A radio frequency (RF) apparatus has a receiver. The receiver includes a mixer, a clock generator, and a common mode controller. The clock generator couples to the mixer. The common mode controller couples to the outputs of mixer. The mixer, the clock generator and the common mode controller are operated collectively to program linearity and a gain of the receiver.

Abstract: An apparatus comprising an analog filter, an analog to digital converter coupled to said analog filter; and a digital filter coupled to said analog to digital converter; wherein the apparatus is configured such that distortion introduced into a filtered signal by said analog filter is substantially compensated by said digital filter.

Abstract: A differential radio frequency signal transmitter is provided. The differential radio frequency signal transmitter includes an oscillator, a modulator and an amplifier module. The oscillator generates a pair of differential oscillation signals. The modulator generates a pair of differential modulated signals according to an input signal and the pair of differential oscillation signals. The input signal is a digital signal. When the input signal is at a first state, the modulator outputs the pair of differential oscillation signals as the pair of differential modulated signals, and when the input signal is at a second state, the modulator outputs a constant voltage signal as the pair of differential modulated signals. The amplifier module receives and amplifies the pair of differential modulated signals and generates a pair of differential radio frequency signals, accordingly.

Abstract: According to an embodiment, a DC offset canceller includes a first DA converter, a first adder, an amplifier, a comparator, an averaging circuit, and a successive approximation register. The first DA converter is configured to DA-convert first correction data into a first correction voltage. The first adder is configured to add an input signal and the first correction voltage to output a first added signal. The amplifier is configured to amplify the first added signal to output an amplified signal. The comparator is configured to compare the amplified signal and a reference voltage to output a comparison result. The averaging circuit is configured to receive the comparison results of the comparator to obtain a majority decision result by performing majority decision on logical values of the comparison results in a predetermined time period.

Abstract: A burst optical signal receiving device is provided, which includes an optical receiving component and a limiting amplifying circuit unit. The optical receiving component further includes a photodetector, a trans-impedance amplifier, a first direct current (DC) cancellation forbidding circuit, and a DC bias circuit, and the limiting amplifying circuit unit further includes a group of alternating current (AC) coupling capacitors, a limiting amplifier, and a second DC cancellation forbidding circuit. Through the technical solution, an input burst optical signal within a certain dynamic range can be recovered into a valid burst electric signal in shorter time. The technical solution can be applied in a burst optical signal receiver in a 10-Gigabit Ethernet passive optical network (10GEPON).