Abstract: A method is provided for reducing a DC bias in a receiver. This method includes isolating a second circuit portion from a first circuit portion (535) and determining a second DC bias correction value for the second circuit portion that will eliminate a second DC bias at the isolated second circuit portion (540). The second circuit portion is then connected to the first circuit portion (550) and a bias-maximizing code word is generated at the first circuitry (505). A first DC bias correction value is then determined that will eliminate a first DC bias at the first circuit portion (555). The bias-maximizing code word is formed such that: a first integrated value of a first half of the bias-maximizing code word has a positive value, and a second integrated value of a second half of the bias-maximizing code word over half of the code word length has a negative value.

Abstract: There are provided, as a low noise amplifier (70) a low noise amplifier (71) with a low gain and a low noise amplifier (72) with a high gain, selectively operable under control of a bias current, and an output from the low noise amplifier (72) and a quadrature demodulator (80) are connected with a serial capacitance (73) and also an output from the low noise amplifier (71) and the quadrature demodulator (80) are serially connected. A control section (66) controls a reception circuit so that the low noise amplifier (71) operates when a reception signal level is high and the low noise amplifier (72) operates when the reception signal level is low. When the low noise amplifier (72) operates, a DC bias current thereof is made flow separately from a DC bias current of the quadrature demodulator (80), and, when the low noise amplifier (71) operates, a DC bias current thereof is shared with the quadrature demodulator.

Abstract: A system for calculating DC offset and achieving frame detection is described. In one embodiment, the present invention includes an electronic device with an integrated receiver module. The receiver module can take advantage of a known synchronization pattern such as the Bluetooth access code to determine an initial DC offset and to provide frame detection.

Abstract: A receiver with baseline wander correction for correcting a received input signal. The receiver includes first and second biasing resistor networks configured to receive first and a second signal of the received input signal, and to produce a first correction signal and a second correction signal. A comparator is employed to compare the first and the second correction signals in order to produce a control signal. The receiver also has comparison logic and compensation control circuitry. The comparison logic generates a logic signal according to the first and the second correction signals. Finally, the compensation control circuitry produces a compensation signal and provides it to respective output terminals of the first and the second biasing resistor networks so as to correct respective DC values of the first and the second correction signals.

Abstract: A device for processing an intermediate analogue signal received from a previous system with a baseband processor. The processor includes an ordinary feedback loop for adjusting the strength of the intermediate analogue signal received from the previous system. The processor further includes a first DC offset reduction loop and a second DC offset reduction loop. A programmable filter bank and the corresponding control elements are provided so that the second DC offset reduction loop can reduce the DC offset in a flexible way. In the present invention, the DC offset can be reduced effectively and the gain training period relating to the previous system and the baseband processor can be shortened.

Abstract: A wireless communication device (WCD) performs DC removal on a received signal using a coarse DC removal unit that removes relatively large DC components and a fine DC removal loop that removes residual DC components. The coarse DC removal unit can be implemented in a receiver, and the flue DC removal loop can be implemented in a modem. In addition, a coarse DC estimation loop implemented on the modem may be coupled to the coarse DC removal unit to update DC offset values stored in the DC removal unit. By storing coarse DC offset values locally on the receiver, DC removal can be achieved very quickly.

Abstract: Apparatus for reducing DC offset in a signal path of a conversion system comprising a front end circuit for providing an input signal having an a DC offset; an amplifier system coupled to the front end circuit to receive and amplify the input signal; a multi-bit sigma delta modulator for receiving the input signal from the amplifier system and providing a first bit quantizer; a DC adapt circuit coupled to the sigma delta modulator for receiving the first bit quantizer from the sigma delta modulator and for providing an operation to reduce DC offset; a digital to analog converter (DAC) coupled to the digital DC adapt circuit to provide an analog signal representative of the DC offset correction to the input of the amplifier system, wherein the digital DC adapt circuit and the DAC form a feedback path originating at the first bit of the multi bit sigma delta modulator to the input of the amplifier system.

Abstract: A DC tracking arrangement includes a first tracking unit for slow tracking receiving an input signal and generating a first output signal, a second tracking unit for fast tracking receiving the input signal and generating a second output signal, and a decision unit receiving the first and second output signal for selecting the first or second output signal.

Abstract: A fixed impedance in parallel with a variable impedance form a high pass filter with a capacitor. An input signal is provided to the capacitor. The value of the variable impedance is controlled in relation to the magnitude of a dynamic DC offset in the input signal to control the corner frequency of the high pass filter, providing a higher corner frequency and more rapid suppression of dynamic DC offset for larger dynamic DC offset magnitudes.

Abstract: Systems and methods for estimating and correcting a DC offset in a receiver in the presence of a carrier frequency offset. Samples corresponding to a transmitted signal are received. Each sample is corrected for a carrier frequency offset. An average value is computed for a training sequence of the corrected samples, where the training sequence has a known DC offset. The average value is adjusted using an adjustment factor that reflects an effect on the DC offset of the act of correcting for a carrier frequency offset, thereby generating a DC offset estimate.

Abstract: Simultaneous bi-directional communication of digital signals across an isolation barrier, such as a pulse transformer, is presented. On the pimary side of the barrier, a voltage driver drives a digital transmit data stream, that is encoded to be DC balanced in both current and voltage domains, across the barrier. On the secondary side, an impedance switching circuit modulates the load impedance of the voltage driver in accordance with a digital receive data stream. The modulation of the load impedance is detected on the primary side by sampling the sourced current of the voltage driver to extract the digital receive data. The voltage driver may be sampled at predictable points in time when the current it is sourcing is primarily dependent upon the load impedance of the secondary side. Alternatively, the magnetizing inductance current of the isolation barrier can be subtracted from the current sourced due to the known transmit data.

Abstract: A communication system in which a reception signal can be accurately obtained from a signal transmitted over two-wire type transmission lines without any significant reduction in the communication speed. The communication system utilizing two-wire type transmission lines for transmitting transmission signals in opposite phases has a plurality of nodes connected to the two-wire type transmission lines, and each of the nodes incorporates terminating resistors acting upon the two-wire type transmission lines. A node which includes a reception circuit for receiving a transmission signal has an AC coupling circuit for extracting AC components in a transmission signal input through the transmission lines, a bias circuit for applying a bias voltage to a signal output from the AC coupling circuit and a clip circuit for clipping the level of a signal output from the bias circuit, which are provided at each of the two-wire type transmission lines.

Abstract: A direct conversion or VLIF receiver corrects DC offset by, prior to receiving a burst of data, the receiver determines a coarse DC offset with the antenna of the receiver switched off. The receiver then adjusts an analog portion of the receiver (e.g., the output of the mixers) based on the coarse DC offset. The receiver then determines a gain setting of the receiver (e.g., for the low noise amplifier and/or programmable gain amplifiers) with the antenna on. The receiver then sets the gain of at least one gain stage of the receiver based on the gain setting. The receiver then determines a fine DC offset with the antenna off. The receiver then, while receiving a burst of data, subtracts the fine DC offset from the digital baseband or low IF signal prior to data recovery.

Abstract: In order to compensate for performance degradation caused by inferior low-cost analog radio component tolerances of an analog radio, a wireless communication transmitter employs a control process to implement numerous digital signal processing (DSP) techniques to compensate for deficiencies of such analog components so that modern specifications may be relaxed. By monitoring a plurality of parameters associated with the analog radio, such as temperature, bias current or the like, enhanced phase and amplitude compensation, as well as many other radio frequency (RF) parameters may be implemented.

Abstract: A receiver (50) includes a self-calibrating receive path correction system for correction of I/Q gain and phase imbalances in a radio frequency signal. The system includes a signal-processing block (53), an I/Q phase imbalance detection and correction circuit (98), an I/Q gain imbalance detection and correction circuit (96), and an adaptive loop bandwidth control circuit (102). The I/Q phase imbalance detection and correction circuit (98) equalizes for the relative phase imbalance and the I/Q gain imbalance detection and correction circuit (96) equalizes for the relative gain imbalance between the I and Q channels created by the analog portion of a quadrature receiver. The adaptive loop bandwidth control circuit (102) dynamically adjusts at least one loop bandwidth for the I/Q gain imbalance detection and correction circuit (96) and the I/Q phase imbalance detection and correction circuit (98) on a slot boundary.

Abstract: A method and a device for estimating the DC offset portion of a signal, especially of a signal containing parts with sinusoidal shape, for example a signal which results from demodulation of a frequency modulated receive signal. A method is presented for correcting the direct current offset portion (DC offset) of a first signal which includes phase shifting the first signal for obtaining a second signal and comparing the first signal and the second signal with an estimated DC offset. The estimated DC offset is adjusted if the result of the comparison is that the first signal and the second signal are on different sides of the estimated DC offset and the estimated DC offset remains constant as long as the result of the comparison is that the first signal and the second signal are on the same side of the estimated DC offset.

Abstract: An apparatus, method, and system for providing dc offset reduction in a communications channel include two or more feedback loops to generate dc offset correction signals, which in turn are combined with an input analog signal and a processed digital signal thereby reducing dc offset. Each feedback loop may include an adaptive filter. At least one feedback loop may be responsive to an error signal that represents the difference between the delayed input of a first detector, and its output. Further, the dc offset correction signal, partially delayed, may be added to the error signal, thereby improving the response time of the dc offset correction loop.

Abstract: Cell search synchronization in spread spectrum communications systems using primary and second synchronization codes with symbol partitioning for shorter coherent combinations (despreading) which are combined non-coherently, and Fourier transform analysis automatically adjusts for phase rotation of the despread sub-symbols.

Abstract: A DC offset cancellation apparatus in a time division duplexing mode direct conversion receiver is disclosed that cancels DC offset of a present frame by using DC offset information of a previous frame by using a receive time difference between data transmission frames. Therefore, the DC offset cancellation unit has advantages of canceling the DC offset in an active mode in real time, of canceling the DC offset varying depending on time and circumferential conditions, and of minimizing power consumption by using an optimized element alignment.

Abstract: The invention relates to a transmitter of radio signals (SMS), which are amplitude-modulated according to a discrete plurality of amplitude levels, in which at least one output power transistor (6) receives, on one of its terminals, a bias-voltage level which is adapted to the amplitude level represented by the instantaneous value of a selection signal (SS) generated by analysis means (11) on the basis of the digital control signals (1). The electrical consumption is hence optimized.

Abstract: An FM radio receiver includes a low noise amplifier, down conversion mixing module, local oscillation module, bandpass filter, demodulation module, and a DC offset estimation module. The low noise amplifier, the down conversion mixing module, the bandpass filter, and the demodulation module are operably coupled to recapture data from a received a radio frequency (RF) signal. The local oscillation module is operably coupled to generate the local oscillation based on a reference oscillation and a DC offset correction signal. The DC offset estimation module is operably coupled to generate the DC offset correction signal based on a determined a DC offset. The DC offset estimation module determines the DC offset prior to compensation of the local oscillation, such as during a test sequence and/or during a preamble.

Abstract: A method to perform DC compensation on a Radio Frequency (RF) burst transmitted between a servicing base station and a wireless terminal in a cellular wireless communication system that first receives the RF burst modulated according to either a first or second modulation format. Samples from the RF burst, or taken from the training sequence, are produced and averaged to produce a DC offset estimate. The DC offset estimate is then subtracted from each of the samples. The modulation format of RF burst may then be identified from the samples. Depending on the identified modulation format, the DC offset estimate may be re-added to the samples when a particular modulation format is identified as the modulation format of the RF burst. This decision is made based on how well various components within the wireless terminal perform DC offset compensation.

Abstract: A receiving apparatus and a power control method that permit standby power consumption to be reduced. If a Digital Signal Processor (DSP) stores an Entitlement Management Message (EMM), which is contained in a MPEG transport stream (MPEG TS) packet, in a memory, the DSP supplies a startup signal to a human interface (HI) microcomputer. According to the startup signal from the DSP, the HI microcomputer supplies power to a back-end portion to start up a main microcomputer, which causes the main microcomputer to initiate processing.

Abstract: A system and method for DC offset compensation wherein a received first signal is despread using a first spreading code to generate a second signal. The second signal along with a first set of pilot symbols is used to estimate a radio channel. The first signal is also despread using a second spreading code to generate a third signal. A DC offset is estimated from the third signal, the estimated radio channel and a second set of pilot symbols. The estimated DC offset may then be subtracted from the second signal.

Abstract: A system for calculating DC offset and achieving frame detection is described. In one embodiment, the present invention includes an electronic device with an integrated receiver module. The receiver module can take advantage of a known synchronization pattern such as the Bluetooth access code to determine an initial DC offset and to provide frame detection.

Abstract: A signal compensation circuit compensates for direct-current offset of an input signal by amplifying the input signal with an amplifier having a variable direct-current offset. A low-speed negative feedback loop charges and discharges a capacitor in an integrating circuit according to the direct-current component of the amplified signal. A high-speed negative feedback loop charges and discharges the same capacitor at a faster rate when the amplified signal goes outside an allowable amplitude range. The capacitor potential is used to control the direct-current offset of the amplifier. The allowable amplitude range is adjusted according to the amplitude of the amplified signal. High-speed compensation can thus be combined with a tolerance for runs of identical code levels in the input signal.

Abstract: A method and system for reducing the DC offset in a receiver in the presence of carrier frequency offset between the transmitter and the receiver. The present invention utilizes the knowledge of the carrier frequency offset to determine the phase difference between two (or more) snapshots of the same transmitted symbol. The receiver DC offset is solved for using a linear system solver which can be implemented outside the analog domain. The DC offset may be tracked in order to maintain a constant adjust of the DC offset, which in combination with the above DC offset estimation technique implements a complete solution for the DC offset cancellation problem.

Abstract: A method and an arrangement for determining correction parameters used for correcting DC-offset of an I/Q modulator in a transmitter comprising an I/Q modulator and a corrector for correcting the DC-offset caused by the I/Q modulator are presented. The method comprises sampling the I/Q-modulated test signals, which are formed from I/Q-plane test vectors, A/D-converting the signal samples taken from the test signals, I/Q-demodulating the signal samples digitally into I- and Q-feedback signals, determining the DC-offset caused by the I/Q modulator on the basis of the test vectors and the feedback vectors caused by the test vectors and formed from the I- and Q-feedback signals, and determining the correction parameters of DC-offset on the basis of the determined DC-offset.

Abstract: A radio frequency (RF) integrated circuit (IC) includes a local oscillation module, analog radio receiver, analog radio transmitter, digital receiver module, digital transmitter module, and digital optimization module. The local oscillation module is operably coupled to produce at least one local oscillation. The analog radio receiver is operably coupled to directly convert inbound RF signals into inbound low intermediate frequency signals based on the local oscillation. The digital receiver module is operably coupled to process the inbound low IF signals in accordance with one of a plurality of radio transceiving standards to produce inbound data. The digital transmitter is operably coupled to produce an outbound low intermediate frequency signal by processing outbound data in accordance with the one of the plurality of radio transceiving standards. The analog radio transmitter is operably coupled to directly convert the outbound low IF signals into outbound RF signals based on the local oscillation.

Abstract: There is provided a digital data receiver for recovering at least one message word signal from a digital data frame.

Abstract: A method for refining a DC-Offset estimate and removing of the DC-Offset includes the step of determining if any AM is present (602). If AM is determined to be present, it is next determined if the I and Q path DC-Offset estimates are closely matched, if they are, then only a single search using the average of the I and Q path estimates is used (608). If it determined however, that the two path estimates are not closely matched, than two searches are performed, one for each path (610). After this, the blocking signals are searched for up to a predetermined number and the DC-Offset vector is generated (612). Once the DC-Offset vector is generated, the DC-Offset is removed from the received signal (614). After which it is determined if the AM level is high (616), and if so, a transient correction routine is performed (618).

Abstract: A method for estimating and removing a time varying DC-offset includes the steps of dividing the received burst into blocks (902), then finding the maximum and minimum values in each block (904). Once the maximums and minimum values have been found, the upper and lower envelopes are determined (906). The DC-offset path is then calculated by taking the average of the upper and lower envelope (908). Once determined, the DC-offset path information is used in order to subtract the DC-offset from the desired signal.

Abstract: A receiver circuit is disclosed for use in a communication system. The receiver circuit includes a forward path with a channel selection filter and a feedback path. The output of the channel selection filter is provided to an output device. The feedback path includes a feedback filter and a mixer. The input of the feedback filter is coupled to the output of the channel selection filter and the output of the feedback filter is coupled to a first input of the mixer. The second input of the mixer is coupled to a multi-frequency signal generator, and the output of the mixer is coupled to the forward path of the receiver circuit.

Abstract: A novel method and apparatus for calibrating DC offsets in a direct conversion receiver. The present DC offset calibration method and apparatus comprises a direct conversion receiver equipped with a frequency shifter means and a DC offset measurement and correction technique. In accordance with the present invention, DC offsets are calibrated in direct conversion receivers through an inventive method including two steps: a DC offset measurement step and a DC offset correction step. In the DC offset measurement step the frequency of a local oscillation signal (typically generated by a voltage-controlled oscillator (VCO)) is shifted by a selected frequency shift value during the inactive time intervals of the receiver. DC offsets are measured while the frequency of the down-conversion oscillation signal is shifted by the frequency shift value. Before the inactive time interval expires, the frequency of the down-conversion oscillator signal is shifted back to its original value.

Abstract: A method to perform DC compensation on a Radio Frequency (RF) burst transmitted between a servicing base station and a wireless terminal in a cellular wireless communication system that first receives the RF burst modulated according to either a first or second modulation format. Samples from the RF burst, or taken from the training sequence, are produced and averaged to produce a DC offset estimate. The DC offset estimate is then subtracted from each of the samples. The modulation format of RF burst may then be identified from the samples. Depending on the identified modulation format, the DC offset estimate may be re-added to the samples when a particular modulation format is identified as the modulation format of the RF burst. This decision is made based on how well various components within the wireless terminal perform DC offset compensation.

Abstract: A device for processing an intermediate analogue signal received from a previous system with a baseband processor. The processor includes an ordinary feedback loop for adjusting the strength of the intermediate analogue signal received from the previous system. The processor further includes a first DC offset reduction loop and a second DC offset reduction loop. A programmable filter bank and the corresponding control elements are provided so that the second DC offset reduction loop can reduce the DC offset in a flexible way. In the present invention, the DC offset can be reduced effectively and the gain training period relating to the previous system and the baseband processor can be shortened.

Abstract: To demodulate a frequency-modulated signal having an offset, two time constants are provided in a filter unit. The filter unit has two analog or digital low-pass filters or high-pass filters. A first switch is used to change over between the two time constants. If a plurality of bits having the same state succeed one another in a setting mode, the first switch is used to change over to a slower time constant so as not to corrupt the threshold voltage that is to be ascertained. In a normal mode, the stored threshold voltage is, then, used to distinguish between the states coded in an input signal. In such a context, the slower time constant is valid in the normal mode.

Abstract: In a radio apparatus, the band of a loop filter of a synthesizer in a blank channel searching state is narrower than the band in a communicating state. In addition, a radio wave environment is measured. A characteristic necessary for the radio apparatus is determined corresponding to the measured radio wave environment. The power is controlled corresponding to the performance of the radio apparatus. Thus, the power consumption is decreased. In addition, the efficiency of the output power is improved. In the radio apparatus, the current consumption of a power amplifier PA is measured. A matching circuit (LNA or MIX) of the antenna is adjusted with the measured result so as to decrease an antenna loss. In the radio apparatus, a DC offset is removed from the transmitted power and the reflected wave. When the DC offset is removed using an AC coupling capacitor, the deterioration of the frequency characteristic of the receiving portion is compensated with a capacitor in a digital signal process.

Abstract: A digital DC bias estimation apparatus and a method thereof for estimating a DC bias of a received signal obtained from a packet after it is received and sampled are provided. The digital DC bias estimation apparatus comprises a symbol boundary detection unit, a preamble pattern identification enabling unit, a preamble pattern identification unit, and a bias calculation unit. The symbol boundary detection unit differentiates a received signal to obtain a differential curve, slices the differential curve into a binary-type comparison base signal by assigning a starting point on a region beyond a transition setting threshold range in the differential curve as a transition point, and issues a boundary signal when a transition is occurred.

Abstract: A read channel component of a magnetic recording system employs equalization of a signal received from the magnetic recording channel, the equalization being modified depending upon the presence or absence of DC shifts in the signal. Equalization corrects for DC shifts, if present, prior to detection and decoding of servo data, such as servo address mark (SAM) and Gray code data. In a first implementation, a DC shift detector detects the presence or absence of DC shifts and modifies equalization in a predetermined manner. In a second implementation, filtering is applied to the signal to enhance equalization in the presence of DC shift, and both filtered and unfiltered signals employed for detection of the servo data.

Abstract: A wireless receiver 200 and corresponding method 500 is arranged to mitigate the effects of non-ideal receiver processing and comprises: a signal source 202 for providing an injection signal that is controlled to have a unique frequency at each of a plurality of time periods; and a non-ideal receiver device 208 constructed to use the injection signal for down converting a received signal having a known frequency to collect a plurality of waveform samples, each having a desired characteristic that varies with the unique frequency and an undesired characteristic, wherein one of the plurality of waveform samples with the undesired characteristic removed will retain the desired characteristic of the received signal.

Abstract: A data slicer for an FSK demodulator employs a peak and valley detector, each of which has a discharge path with selectable decay rates. One of the decay rates is significantly faster than another. The data slicer employs a decay rate selector that selects between the faster and slower decay rates. The data slicer is fed with a frequency-to-voltage converted FSK modulated signal. The faster decay rate for the peak and valley detector outputs is selected when the difference between the current peak and valley voltages exceeds a predetermined percentage (e.g. 75%) of the expected swing of the voltage input (i.e., when there is a DC offset present due to an offset in the carrier frequency of the transmitter). In this mode, the faster decay rate permits faster acquisition of packet data in the presence of DC offset, as it permits the data slicer to converge on an appropriate switching point more quickly.

Abstract: A radio receiver and method is provided that effectively compensates for an undesirable DC offset in a digital section of the radio receiver by preloading a filter with an average DC offset before filtering a signal within the filter. More specifically, the radio receiver includes an antenna for receiving a radio signal, and an analog section for demodulating the received radio signal into at least one baseband signal. The radio receiver also includes an analog-to-digital section for converting the at least one baseband signal into at least one digital baseband signal. The radio receiver further includes a preloading system for calculating an average DC offset using a predetermined number of symbols from the at least one digital baseband signal and for preloading a filter with the calculated average DC offset prior to filtering the at least one digital baseband signal in the filter.

Abstract: Circuit arrangement for evaluating an information signal and a method for adjusting a circuit arrangement of this type.

Abstract: A determining section (18) and gain variation amount detecting section (9) detect a period having a possibility of a DC-component offset in an internal circuit of a direct conversion receiver increasing beyond an allowable value due to AGC operation, and during the period, a cut-off frequency of each of high-pass filters (12a to 12d) is set at a frequency higher than that in general operation, thereby rapidly converging transient responses of signals passed through the high-pass filters, while controlling precisely operation timings of reception power measuring section (16), gain calculating section (22), gain control section (23) and circuit power supply control section (24) composing an AGC loop, whereby the DC offset is prevented from increasing and stable circuit operation is assured. It is thereby possible to achieve further reductions in size and power consumption of a CDMA receiver using the direct conversion receiver.

Abstract: An FM demodulator compensates for DC offset by detecting the positive peak value of the frequency demodulated signal (D1, C2, R1) and the negative peak value of the frequency demodulated signal (D2, C3, R2). The mean of the positive and negative peak values is determined (C1, R3, R4) to produce an estimation of a DC offset value. This estimated DC offset value is then used to compensate for DC offset in the frequency demodulated signal. This circuit has the advantage of enabling the DC offset to be calculated without requiring complex digital signalling processing, and without requiring the input signal to have a zero mean. A signal strength signal RSSI may be used to disconnect the DC offset compensation circuitry during periods when the input signal strength is weak.

Abstract: A method and offset removing apparatus for removing DC offset from a digital baseband signal value pair included in a set of digital baseband signal value pairs is described. The digital baseband signal value pairs, when plotted on a complex signal space I-Q diagram, lie on a predetermined figure. The I and Q coordinates of the central point of this predetermined figure are determined by a two-dimensional fitting of this figure through a subset of signal value pairs included within the set. These coordinates of this center point are subsequently subtracted from the I and Q coordinates of the digital baseband signal.

Abstract: An amplification system for reducing DC offset in an input signal uses a low pass filter to isolate a DC component of the input signal. The system then subtracts the DC component from the input signal. In one embodiment, the system includes first and second amplifiers in addition to the low pass filter. The first amplifier amplifies the input signal to generate a first amplified signal at a differential output port of the amplification system. The second amplifier amplifies a low pass filtered version of the input signal to generate a second amplified signal at the differential output port of the amplification system. The outputs of the first and second amplifiers are connected to the differential output port of the amplification system in such a way that the first and second signals combine 180 degrees out of phase at the output port.

Abstract: A method 10 is provided to mitigate DC offset in a sign bit correlator associated with a packet detection circuit. The input sign pattern is monitored; and if a long run of the same sign is seen, a sign bit is replaced with a bit generated using a desired pseudorandom noise (PN) sequence. This ensures that the correlator only reacts substantially to correlations that are not due to DC offset.

Abstract: A direct conversion receiver includes a detector that provides a measure of bias offset that is caused by component mismatches in the direct conversion mixer, and a corrective network that reduces the bias offset based on this measure. The direct conversion mixer demodulates a radio-frequency (RF) input signal via mixing with a local-oscillator (LO) signal to provide a differential baseband output signal. A differential peak detector compares the peak signal value at each side of the mixer's differential output, and a differential integrator averages the difference between these peak signal values to provide the measure of bias offset. The corrective network adds a correction offset to each of the local oscillator local oscillator paths on each of the switching pairs that provide the differential output, but opposite to the local oscillator connections.