Abstract: Offset voltage compensation in baseband in a radio receiver path is achieved by control and programming signals which are required in any case to set the desired states in the circuit module. For this purpose a sequencer is started which is integrated on the module and provides additional control signals that are defined in time, without any additional computation power being required from a separate baseband processor. The offset voltage compensation can be used in receiver and transceiver chips for portable mobile radios, for example for GSM or PCN/PCS.

Abstract: An offset estimation and bit timing system and method configured to detect a DC offset in a received signal is disclosed herein. The inventive system includes a first circuit for receiving and correlating a transmitted signal and generating a trigger signal in response thereto. A second circuit accumulates the received signal and provides a second signal on receipt of the trigger signal. The second signal is then converted to an offset error signal. The error signal is converted to analog and used as a reference input for an A/D converter. As an alternative, the error signal may be used to adjust the signal output by an intermediate frequency downconversion stage.

Abstract: An FM radio receiver includes a low noise amplifier, down conversion mixing module, local oscillation module, bandpass filter, demodulation module, and a DC offset estimation module. The low noise amplifier, the down conversion mixing module, the bandpass filter, and the demodulation module are operably coupled to recapture data from a received a radio frequency (RF) signal. The local oscillation module is operably coupled to generate the local oscillation based on a reference oscillation and a DC offset correction signal. The DC offset estimation module is operably coupled to generate the DC offset correction signal based on a determined a DC offset. The DC offset estimation module determines the DC offset prior to compensation of the local oscillation, such as during a test sequence and/or during a preamble.

Abstract: A wireless communication device (WCD) performs DC removal on a received signal using a coarse DC removal unit that removes relatively large DC components and a fine DC removal loop that removes residual DC components. The coarse DC removal unit can implemented in a receiver, and the fine DC removal loop can be implemented in a modem. In addition, a coarse DC estimation loop implemented on the modem may be coupled to the coarse DC removal unit to update DC offset values stored in the DC removal unit. By storing coarse DC offset values locally on the receiver, DC removal can be achieved very quickly.

Abstract: A method and apparatus for trimming of a local oscillation within a radio frequency integrated circuit (RFIC) includes processing that begins when an RFIC receives a radio frequency (RF) signal having a known frequency. The processing then continues when the RFIC mixes the RF signal with a receiver local oscillation to produce a low intermediate frequency (IF) signal, which may have a carrier frequency of zero (i.e., a baseband signal) or up to a few mega Hertz). The processing then continues when the RFIC demodulates the low IF signal to produce demodulated data. The processing then continues as the RFIC determines a DC offset from the demodulated data, where the DC offset is reflective of the difference between the known frequency and the frequency of the receiver local oscillation. The processing then continues as the RFIC adjusts the receiver local oscillation to reduce the DC offset when the DC offset compares unfavorably with an allowable offset threshold.

Abstract: A DC offset correction method and apparatus. In a differential system, a DC offset correction loop includes a gain stage (104) having a differential input, a gain G and a differential output. A DAC circuit (130) provides a correction DC signal at the inputs to produce differential output signals Vo′ and {overscore (Vo)}′. A controller (120) corrects the DC offset by stepping the DAC circuit (130) to change the correction DC signal by an amount equal to approximately (Vo′−{overscore (Vo′)})/Gx, where GX is the gain G times the gain of the DAC expressed in volts per DAC step. A similar algorithm can be applied to single ended systems wherein a single ended VOFFSET is corrected by an amount equal to approximately VOFFSET/Gx.

Abstract: When an input unit amplifier is employed in which transistors are longitudinally stacked in order that an input amplitude of a quantizing feedback circuit is made coincident with an output amplitude thereof, this quantizing feedback circuit cannot receive an ECL signal having a large amplitude under low power supply voltage. In a DC recovery circuit for correcting a shift contained in a DC level of an input signal by employing a quantizing feedback circuit having an adder, a comparator, and low-pass filters, a DC level of an input signal of the quantizing feedback circuit is compared with a DC level of an output signal thereof by an AGC circuit. A control signal corresponding to a level difference of these DC levels is supplied to a variable current source of a differential amplifier which constitutes a comparator so as to control a current of this variable current source.

Abstract: A method and apparatus for data recovery includes processing that begins by receiving an encoded signal at a transmit symbol rate. Such an encoded signal includes data that is represented by positive and negative pulses. The processing continues by determining at least one reference crossing of the encoded signal (e.g., detecting a 0 crossing). The processing then continues by determining a sampling phase of a system symbol rate based on the reference crossing. The processing then continues by sampling the encoded signal at the determined sampling phase with respect to the system symbol rate to recapture the data.

Abstract: An automatic gain control circuit for an optical receiver couples the low level signal produced by an optical detector to a signal amplifier, preferably a double-ended differential amplifier with the optical detector output fed into the high input and the low input coupled to ground, the gain of which is controlled by a negative feedback circuit. The feedback circuit comprises a signal level detection circuit coupled to the amplifier output, such as high-speed Schottky diodes acting in conjunction with an operational amplifier. The Schottky diodes are coupled to ground through AC coupling capacitors, and oriented in opposite directions, so when the amplified signal exceeds a conduction threshold of the Schottky diodes the capacitors are respectively charged and drained, establishing a voltage difference between the input terminals of the operational amplifier.

Abstract: A communication signal receiver has a plurality of components. The components are arranged along at least one signal path and comprise a filter (130a-b) for processing a received signal and averaging means (134a-b) for deriving a mean value of the signal. An output of the averaging means (134a-b) is connected to a component (128a-b) located prior to the filter (130a-b) along the signal path, so that the mean value may be selectively fed back to the filter (130a-b).

Abstract: A digital DC offset correction circuit (68) provides DC offset correction within a receiver (50) using an area-optimum, rapid acquisition cellular multi-protocol digital dc offset correction scheme. The digital DC offset correction circuit (68) includes an integrator (90), a low pass filter (92), a decimator (94), a digital to analog converter codeword clamp (96), and a digital to analog converter (98).

Abstract: Methods and apparatuses for reducing DC offsets in a communication system are described. In a first aspect, a feedback loop circuit reduces DC offset in a wireless local area network (WLAN) receiver channel. The frequency response of the feedback loop circuit can be variable. In a second aspect, a circuit provides gain control in a WLAN receiver channel. The stored DC offset is subtracted from the receiver channel. First and second automatic gain control (AGC) amplifiers are coupled in respective portions of the receiver channel. In a third aspect, a feedback loop circuit reduces DC offset in a WLAN receiver channel. The feedback loop circuit includes a storage element that samples and stores receiver channel DC offset. The loop is opened, and the DC offset stored in the storage element is subtracted from the receiver channel. Circuits for monitoring DC offset, and for providing control signals for controlling the frequency response of the DC offset reducing circuits are also provided.

Abstract: Methods and apparatuses for reducing DC offsets in a communication system are described. In a first aspect, a feedback loop circuit reduces DC offset in a wireless local area network (WLAN) receiver channel. The frequency response of the feedback loop circuit can be variable. In a second aspect, a circuit provides gain control in a WLAN receiver channel. First and second automatic gain control (AGC) amplifiers are coupled in respective portions of the receiver channel. Circuits for monitoring DC offset, and for providing control signals for controlling the frequency response of the DC offset reducing circuits are also provided.

Abstract: A system and method for DC offset compensation wherein a received first signal is despread using a first spreading code to generate a second signal. The second signal along with a first set of pilot symbols is used to estimate a radio channel. The first signal is also despread using a second spreading code to generate a third signal. A DC offset is estimated from the third signal, the estimated radio channel and a second set of pilot symbols. The estimated DC offset may then be subtracted from the second signal.

Abstract: A DC offset correction circuit (68) provides DC offset correction within a receiver (50) for receiving and processing a radio frequency signal (28) within a radio communication system (30). The DC offset correction circuit (68) includes a feedback loop (88) for shifting a digital signal (80) by a programmable amount; and a coarse DC offset correction path (104) coupled to the feedback loop (88) for performing coarse DC offset correction.

Abstract: A system and method for compensating for DC offset and/or clock drift on a wireless-enabled device is described. One embodiment includes a radio module, an A/D converter connected to the radio module, a DC tracking loop connected to the A/D converter, and a multi-hypothesis bit synchronizer.

Abstract: A system for calculating DC offset and achieving frame detection is described. In one embodiment, the present invention includes an electronic device with an integrated receiver module. The receiver module can take advantage of a known synchronization pattern such as the Bluetooth access code to determine an initial DC offset and to provide frame detection.

Abstract: A data receiver equalization technique utilizes a receiver clock that has a frequency different that the incoming data frequency (i.e., an “asynchronous clock”) to asynchronously sample the incoming data waveform. The resulting information about the data, typically including the rise and/or fall times, overshoot and/or undershoot, and amplitude, may be used to equalize a data channel. Other adjustments to the receiver, including the gain level and DC offset compensation, may also be made using the resulting information. An illustrative embodiment using clocked comparators, continuous-time comparators, and a statistical analysis circuit is shown.

Abstract: A radio-frequency receiver circuitry includes a down-converter circuitry, an analog-to-digital converter circuitry, and a DC offset reduction circuitry. The down-converter circuitry accepts a received radio-frequency signal and processes the radio-frequency signal to provide an in-phase down-converted signal and a quadrature down-converted signal to the analog-to-digital converter circuitry. The analog-to-digital converter circuitry converts the in-phase and quadrature down-converted signals to an in-phase digital output signal and a quadrature digital output signal, respectively. The DC offset reduction circuitry couples to the analog-to-digital converter circuitry, and tends to reduce a DC offset transmitted to the in-phase and quadrature digital output signals.

Abstract: A method for estimating and removing a time varying DC-offset includes the steps of dividing the received burst into blocks (902), then finding the maximum and minimum values in each block (904). Once the maximums and minimum values have been found, the upper and lower envelopes are determined (906). The DC-offset path is then calculated by taking the average of the upper and lower envelope (908). Once determined, the DC-offset path information is used in order to subtract the DC-offset from the desired signal.

Abstract: A method for refining a DC-Offset estimate and removing of the DC-Offset includes the step of determining if any AM is present (602). If AM is determined to be present, it is next determined if the I and Q path DC-Offset estimates are closely matched, if they are, then only a single search using the average of the I and Q path estimates is used (608). If it determined however, that the two path estimates are not closely matched, than two searches are performed, one for each path (610). After this, the blocking signals are searched for up to a predetermined number and the DC-Offset vector is generated (612). Once the DC-Offset vector is generated, the DC-Offset is removed from the received signal (614). After which it is determined if the AM level is high (616), and if so, a transient correction routine is performed (618).

Abstract: Apparatus for reproducing data from a selected digital television signal, transmitted in packet form as vestigial-sideband (VSB) amplitude-modulation (AM) of a carrier, has a tuner for selecting a digital television signal and converting it to a final intermediate-frequency signal, which is digitized by an analog-to-digital converter before synchrodyning to baseband in the digital regime. VSB synchrodyning circuitry synchrodynes the digitized final intermediate-frequency signal to baseband in the digital regime to generate in-phase and quadrature-phase baseband signals. The quadrature-phase baseband signal is lowpass filtered to generate an automatic frequency and phase control (AFPC) signal for controlling a local oscillator in the tuner, so that the in-phase baseband signal comprises digitized VSB symbol coding. Symbol decoding circuitry responsive to the VSB symbol coding generates a digital data stream.

Abstract: In a direct conversion receiving apparatus, a first frequency converting section includes a first capacitor, and frequency-converts a high frequency reception signal into a first base band signal using a first local oscillation frequency signal. Then, the; first frequency converting section removes a DC component from the first base band signal using the first capacitor, and converts the first base band signal with the DC component removed into a first digital signal. A second frequency converting section includes a second capacitor, and frequency-converts the high frequency reception signal into a second base band signal using a second local oscillation frequency signal which is different from the first local oscillation frequency signal by 90 degrees in phase. Then, the second frequency converting section removes a DC component from the second base band signal, using the second capacitor, and converts the second base band signal with the DC component removed into a second digital signal.

Abstract: The invention relates to a method and a device for estimating the DC offset portion of a signal, especially of a signal containing parts with sinusoidal shaping, for example a signal which results from demodulation of a frequency modulated receive signal.

Abstract: A receiver having a function of a direct current offset, and including a receiving section for receiving a radio frequency signal, an analog signal processing section for amplifying, band-converting and frequency-converting an analog signal inputted from the receiving section, and an AD converting section for converting an output of the analog signal processing section from an analog signal to a digital signal. Also included is a digital signal processing section for processing the digital signal converted by the DC converting section.

Abstract: A binary data signal of a very high speed rate travelling over a transport network is regenerated using two threshold levels. The first threshold, or the preset threshold is initially set by the performance monitor, and thereafter adjusted based on the current quality of the signal eye. The second threshold, or the decision threshold, is determined by the performance monitor based on the preset threshold and on the provisioned BER.

Abstract: A method and circuit for compensation control of offset voltages of a radio receiving circuit integrated in a circuit module that can be used in receiver and transceiver chips for portable mobile radio transceivers, for example in GSM or PCN/PCS systems. In the course of offset voltage compensated in the baseband of a radio receiver, the charge state of a capacitor, which is switched on in a sample-and-hold circuit by predetermined, constant control pulses is evaluated on-chip. The evaluation result is used to match the charging current of a sample operational amplifier to the respective charge state of the capacitor, thereby achieving a minimal compensation time with stable regulation.

Abstract: A radio signal that has been received from a channel is equalized by estimating the channel, generating an initial estimate of a DC-offset that has been introduced into the radio signal, and estimating a variance of the initial estimate of the DC-offset. The channel estimate, the initial estimate of the DC-offset and the estimated variance are then used to determine a most likely symbol represented by the radio signal. The initial estimate of the DC-offset that has been introduced into the radio signal may be determined from a training sequence portion of the received signal and a reference training sequence signal. For example, a least squares technique may be used to generate the DC-offset as well as the channel estimate and the variance of the initial estimate of the DC-offset. In an equalizer section, the DC-offset and variance values are taken into consideration when the most likely symbol represented by the radio signal is decided.

Abstract: A receiver circuit allows extracting information from baseband components of a received signal. Means are disclosed for removing constant disturbance components from the baseband signal components.

Abstract: A receiver having a variable bit slicer for detecting bits in a demodulated signal, comprises a demodulator (14) for deriving a demodulated bit rate signal, means (36) for storing a plurality of threshold values, each of the threshold values being selectively adjustable, means (28, 38) for selecting the threshold value for comparison with the current bit signal (Sn) in response to a sequence of N bits (where N is at least 2) (Bn-1, Bn-2) received prior to the current bit (Bn) and means (38, 40) for using the current bit to update the selected threshold value.

Abstract: A demodulator for use with a digital wireless communication system is disclosed, that comprises a DC offset controller for removing a DC offset of a modulated signal that is input to the demodulator, a complex multiplying unit for complex-multiplying an output signal of the DC offset controller, a phase detector for detecting an amplitude error signal and a phase error signal from an output signal of the complex multiplying unit, an LPF (low pass filter) for outputting a low band component of the phase error signal, and an NCO (numerical controlled oscillator) for converting an output signal of the LPF into a sin component and a cos component that have orthogonal relation, wherein the sin component and the cos component are input to the complex multiplying unit, and wherein the amplitude error signal, the sin component, and the cos component are input to the DC offset controller.

Abstract: A system for the controlling the operational mode of an adaptive equalizer quickly determines the operational mode of the adaptive equalizer by measuring the amplitude variation of a DC offset for every segment.

Abstract: In a detection circuit for ASK or OOK modulation, the received modulated signal is ac coupled to a dc restoration circuit and amplified. The dc restoration is carried out on signal peaks corresponding to “mark” intervals of the modulated signal. Thus data may be recovered even in the presence of high levels inband continuous interfering signals.

Abstract: A DC-offset canceller in a receiver of a communication system using a burst signal including a training sequence with a predetermined periodicity at the head thereof is disclosed. In the canceller, a quadrature demodulator 112 converts the received burst signal to a base band signal. An AD converter 113 converts an output signal of the quadrature demodulator to a digital signal. A one-cycle delay element 114 makes a delay of an output signal of the AD converter 113 corresponding to one-cycle of the training sequence. A DC-offset detector 115 detects a DC-offset component in the converted signal by the AD converter 113 on the basis of an output signal of the AD converter 113 and an output signal of the one-cycle delay element 114. A subtractor 116 removes the DC-offset component detected by the DC-offset detector 115 from the output signal of the AD converter 113.

Abstract: A direct conversion receiver uses an algorithm implemented by a DSP to cancel residual dc offsets during demodulation of a GMSK modulated signal. The algorithm exploits the characteristics of GMSK modulation by determining the modulation extremes within sampled I/Q signals and calculates the DC offset as the mean of the extremes. This offset is used to weight a declining exponential function which is subtracted from the original signal samples to achieve compensation.

Abstract: A data carrier (1) on which a carrier signal (TS) can be applied to an electric circuit (3), comprises supply voltage generation means (6) which are arranged for generating a DC supply voltage (U) that can be tapped from a supply tapping point (10) while use is made of the carrier signal (TS), and further includes control means (11) for controlling the DC supply voltage (U) in accordance with a controlled variable signal (CV) that represents the carrier signal (TS) occurring at a control means circuit point (20), and further includes decoupling means (49) with the aid of which the control means circuit point (20) and the supply circuit point (10) can be decoupled from each other.

Abstract: In order to increase accuracy of DC-offset compensation within radio receivers and to ensure that such compensation does not erode the dynamics of the decoders located within the receivers, the present invention separately performs mean value estimation and channel estimation. Additionally, a bias DC offset value caused by the use of a training sequence to perform mean value estimation can be corrected for in the channel estimator and equalizer.

Abstract: In a zero intermediate frequency (ZIF) receiver (300) a desired signal is detected (902) and downmixed (924) to baseband, off-centered by an amount determined by at least one of (a) whether (906) pilot symbols are present in the desired signal, and (b) signal levels (908) of the desired signal and adjacent channel signals.

Abstract: A method and concomitant apparatus for adapting a logic threshold level in response to a background noise level in an information signal. Information signal excursions beyond the logic threshold are indicative of the presence of an information packet in the information signal. In this manner, a relatively low dynamic range information packet processor may reliably receive information packets.

Abstract: To reduce the DC-offset in bursts (B1, B2) of a digital signal (S1), some samples of one of the digital bursts (B1) which have no predetermined value are averaged by an averager (AV) resulting in a correction value (CV). Meanwhile the samples of this digital burst (B1) are temporarily stored in a memory (MEM1). The DC-offset correction value (CV) calculated by the averager (AV) is then substracted from the samples of the digital bursts (B1, B2). In this way, the dynamic range of the samples is reduced significantly.

Abstract: A method and an arrangement for determining correction parameters used for correcting DC-offset of an I/Q modulator in a transmitter comprising an I/Q modulator (7) and a corrector (4A, 4B, 16) for correcting the DC-offset (DC) caused by the I/Q modulator, the arrangement comprising means (9) for sampling the I/Q-modulated test signals, which are formed from I/Q-plane test vectors (T1, T2), means (14) for A/D-converting the signal samples taken from the test signals, means (15) for I/Q-demodulating the signal samples digitally into I- and Q-feedback signals, means (17) for determining the DC-offset (DC) caused by the I/Q modulator on the basis of the test vectors and the feedback vectors (M1, M2) caused by the test vectors and formed from the I- and Q-feedback signals, and means (17) for determining the correction parameters of DC-offset on the basis of the determined DC-offset.

Abstract: An automatic input threshold selector includes a maximum value level decision circuit, and an input threshold setting circuit. The maximum value level decision circuit decides, among m+1 level layers defined by m maximum value decision levels, a level layer to which the maximum value of an input signal belongs. The input threshold setting circuit sets an input threshold by selecting one of n input threshold candidates in response to the level layer to which the input signal maximum value belongs. These circuits are implemented as a simple combination of a voltage comparator, logic gates and the like. This makes it possible to solve a problem of a conventional automatic input threshold selector in that its circuit scale and power consumption is rather large because it includes a peak-hold circuit and a bottom-hold circuit.

Abstract: An optical receiver includes a light-receiving device, an equalizing amplifier, a regenerating circuit, a timing signal extraction circuit, a reference voltage generation circuit, and a comparator. The light-receiving device converts input signal light into an electrical signal. The equalizing amplifier amplifies the electrical signal output from the light-receiving device and performs waveform shaping. The regenerating circuit regenerates data from an output from the equalizing amplifier on the basis of a retiming signal. The timing signal extraction circuit extracts a timing signal from an output signal from the equalizing amplifier. The reference voltage generation circuit generates a reference voltage changing in accordance with a variation in ambient temperature. The comparator compares an output signal from the timing signal extraction circuit with the reference voltage output from the reference voltage generation circuit and supplies the retiming signal to the regenerating circuit.

Abstract: A mobile communication system comprising an analog baseband processor that is configured for providing improved DC offset compensation. An offset compensation circuit of the analog baseband processor generates a first DC offset compensation signal to preset DC offset voltage of analog baseband signal when the mobile communication system is power on. A mobile station modem of the mobile communication system generates a second DC offset compensation signal to compensate for a detected DC offset voltage during operation of the mobile communication system subsequent to the DC offset voltage being preset. In addition, the offset compensation circuit re-presets the DC offset by generating a third DC offset compensation signal whenever the mobile communication system enters a predetermined mode of operation such as a “data send” mode.

Abstract: A wireless communication network comprising a wireless receiver. The wireless receiver comprises at least a first antenna for receiving packets, wherein each of the received packets comprises a plurality of bits and each of the plurality of bits is modulated by a frequency offset. The wireless receiver also comprises circuitry for cycling through a hopping sequence, wherein the hopping sequence comprises a sequence of frequency bands and circuitry for demodulating each received packet in response to a frequency band in the hopping sequence. The wireless receiver also comprises circuitry for detecting the frequency offset of each of the plurality of bits and converting the frequency offset of each of the plurality of bits into a corresponding DC voltage for each of the plurality of bits.

Abstract: A serial digital data communications receiver with an improved automatic cable equalizer that is less susceptible to jitter and has greater multi-standards capability, and an improved automatic gain control system with a DC restorer that provides optimal edge jitter performance while avoiding the possibility of a latch-up condition at the start of data transmission. The automatic cable equalizer for equalizing signals received over cables of different lengths has multiple stages each having a transfer function of 1+Ki[fi(j)] wherein each of the Ki vary in accordance with a sequential gain control methodology. The AGC system uses the difference between band-pass filtered versions of the amplitudes of the input and output of a DC restorer based on quantized feedback, to regulate the AGC circuit.

Abstract: A DC-offset eliminating circuit changes a coefficient &agr; for determining a DC-offset follow-up speed. The coefficient &agr;, is changed to a smaller value or 0 in a case where a signal showing a detection that a reception is ceased, is received from a signal-end detecting circuit, or in a case where a signal for partly turning off the circuits for the reduction of power consumption is received from a control circuit, if the received frame is not destined for the receiver itself. The circuit remains the coefficient &agr; to a smaller value immediately after the reception is resumed. Additionally, the circuit returns the coefficient &agr; to the normal value in response to the reception of a signal showing that an alignment signal is detected immediately after a preamble portion. The circuit then reduces the DC-offset follow-up speed as much as possible at the time when the preamble portion is received, thereby avoiding the DC-offset deviation caused by the preamble patterns.

Abstract: A receiver for processing a VSB modulated signal containing terrestrial broadcast high definition television information and a pilot component includes an input analog-to-digital converter (19) for producing a datastream which is oversampled at twice the received symbol rate, and a digital demodulator (22; FIG. 3) with a data reduction network (330, 332) in a phase control loop. A segment sync detector (24; FIGS. 4, 5) uses an abbreviated correlation reference pattern to recover a twice symbol rate sampling clock for the digital converter (19). A DC offset associated with the pilot component is removed (26; FIG. 6) from the demodulated signal before it is applied to an NTSC interference detection network (30; FIG. 7). The interference detection network includes a comb filter network (710, 718) responsive to a twice symbol rate sampled data datastream, and exhibits a sample delay dimensioned to avoid aliasing in the combed frequency spectrum (FIG.

Abstract: An audio frequency recovery—DC restorer circuit after demodulation that includes an operational amplifier, a diode, a capacitor and resistor circuitry arranged to supply a reference voltage signal Vref to the operational amplifier. The operational amplifier is also coupled with a demodulated audio frequency baseband signal via the capacitor. The demodulated audio frequency baseband signal is in a filtered condition free of high frequency noise that may otherwise affect quality and having an average voltage Vavg at a level.

Abstract: A direct conversion receiver comprising mixers for mixing a received radio frequency signal and a local oscillation signal in frequency, a signal processing unit for converting the output signal of the mixers into a baseband signal, a delta-sigma modulator for detecting offset voltage from the output signal of the signal processing unit, a holding circuit for supplying offset canceling voltage for canceling the offset voltage, and a switch of supplying the output signal of the mixers to the delta-sigma modulator during a given period and supplying the offset canceling voltage sent from the holding circuit to the output side of the mixers.