Abstract: A structure and method for demodulating two-level differential amplitude-shift-keying signals using simple adding operations are provided. Threshold values are dynamically adjusted according to the channel response. By comparing the threshold values and the differential amplitude values, it can be found whether the amplitude of the received signal is changed. Furthermore, it no needs to know the changed value of received signal amplitudes and the differential two-level amplitude-shift-keying signals can be demodulated by just detecting whether the amplitude of the received signal is changed. By this idea, the complexity of the receiver implementation is simplified and the demodulator can get better performance.

Abstract: A method and apparatus are provided for low power simultaneous frequency, automatic gain control and timing acquisition in a low power radio receiver. A baseband signal received is split into a limited signal having limited data and a non-limited signal. The limited signal is fed through a limited phase-shift keying (PSK) correlation path in which a PSK correlator operating on the limited signal simultaneously determines coarse frequency estimations, timing estimations, and packet synchronization detection. The non-limited signal is fed through an automatic gain control path where automatic gain control is performed on the non-limited signal simultaneously with the coarse frequency and timing estimations and packet synchronization detection performed by the PSK correlator.

Abstract: An apparatus and method are described that provide an optimal blind channel estimation approach for a differential quadrature phase shift keying (DQPSK) modulation communication receiving system. The described blind channel estimation technique takes advantage of the characteristics of DQPSK constellations and the fact that estimates of relative channel phase distortion, and not absolute channel phase distortion, are sufficient for a DQPSK demodulation scheme. The described channel estimation approach provides low complexity, offers improved demodulation performance, and is theoretically optimal. It is particularly useful in existing DQPSK-based communications protocols that do not provide sufficient reference symbols for channel estimation.

Abstract: A method of performing alternating quadratures differential binary phase shift keying modulation involves limiting phase changes between adjacent in time modulator output symbols to ±90 °, and transmitting modulator input data by 0° and 180° phase differences between non-adjacent in time modulator output symbols.

Abstract: A method of estimating a coarse frequency offset in a receiver includes providing at least one candidate frequency offset in Orthogonal Frequency-Division Multiplexing (OFDM) symbols having transmission and multiplexing configuration control (TMCC) bins and auxiliary channel (AC) bins, modulating the TMCC bins and AC bins using differential binary phase shift keying (DBPSK) modulation, estimating a phase difference between a first symbol and a second symbol for the candidate frequency offset of the TMCC and AC bins to obtain a resulting phase difference, correcting the resulting phase difference based on a difference between the candidate frequency offset and a Fast Fourier Transform (FFT) center bin to obtain a corrected phase difference, mapping the corrected phase difference to numeric numbers, and adding the numeric numbers for the candidate frequency offset to obtain a summation result. The numeric numbers correspond to at least one of +1 or ?1.

Abstract: A method and system of improving sensitivity in the demodulation of a received signal over an arbitrary measurement time epoch, the method comprising the steps of: correlating the received signal in a coherent fashion (80); and utilizing a Viterbi phase state keying trellis demodulation with a variable resolution of phase states over 360° to demodulate the radio frequency phase trajectory of the signal throughout the measurement time epoch (70); and the system comprising a receiver for receiving a direct sequence spread spectrum signal, the receiver comprising: an antenna (10) for receiving the direct sequence spread spectrum signal; a downconverter (40) for downconverting the received signal, producing a downconverted signal; an analog to digital converter (60) to convert the downconverted signal to a digital signal; a despreader (80) for despreading and coherently correlating the digital signal to a known signal, creating a despread signal; and a processor (70) for applying a Viterbi algorithm to the despre

Abstract: Methods and apparatuses process a communication signal to detect a burst packet comprising an access code. The method comprises deriving a differential phase signal indicating differential phases of a first set of the access code in the communication signal, and comparing the differential phase signal with an ideal differential phase signal to calculate a frequency offset value, compensating the differential phase signal by the frequency offset value to generate a compensated differential phase signal, and detecting a burst packet transmitted via the communication signal according to the compensated differential phase signal.

Abstract: A demodulation circuit demodulates a differential phase shift keying (DPSK) modulated received signal. A phase difference data generator compares phase data representing a phase of the received signal input at every predetermined sampling time with previous phase data preceding by one symbol time to generate phase difference data representing a phase shift amount of the phase data. A symbol selection unit evaluates the phase difference data generated at every sampling time to select as a symbol.

Abstract: A receive circuit for receiving a signal transmitted via an electric signal conductor. A first sampling circuit generates a first sample value that indicates whether the signal exceeds a first threshold level, and a second sampling circuit generates a second sample value that indicates whether the signal exceeds a second threshold level. A first select circuit receives the first and second sample values from the first and second sampling circuits and selects, according to a previously generated sample value, either the first sample value or the second sample value to be output as a selected sample value.

Abstract: A receiver includes a signal input for receiving a differentially-encoded quadrature phase-shift keyed (DEQPSK) communication signal. A demodulator performs bit decisions on a received coherent symbol and bit decisions on a received differential symbol. A processor is operative with the demodulator and scales a soft decision by a factor from 0 to 1 when the results of the bit decisions on the received coherent branch and differential branch are different.

Abstract: Embodiments are directed to binary phase shift key modulating a first pilot symbol according to a reference sequence, and differentially binary phase shift key modulating a second pilot symbols. The original reference sequence and the delayed differentially modulated sequence are then combined before performing an Inverse Fast Fourier Transform and inserting a guard interval. Receiver operations are an inverse of the transmitter operations, which were just discussed. The receiver does not have to know the reference sequence. Embodiments are directed to specifying a plurality of seeds that are bit patterns each having r bits not all of which have a value of zero, extending the seeds into respective sequences by applying to each seed a recurrence formula; and using one of the sequences as a comb sequence and using the sequences other than the comb sequence as binary phase shift keying patterns.

Abstract: An apparatus and method for use by a receiver in decoding information sent by phase-shift keying over a carrier frequency is disclosed. The method is well suited for use with power line carrier (PLC) applications as it is adapted to appropriately position the sampling window based on a zero crossing of one of the phases of the power line. The method allows for receipt and processing of information on more than one carrier frequency and from transmitters operating on a phase of the power line that is different than the phase used by the receiver to detect the zero crossings of the alternating current at the power grid frequency on the power line. A number of alternative embodiments are included.

Abstract: A system for implementing the soft decision of a 3-chip differential binary phase shift keying (DBPSK) optical signal using digital components. Pair-wise comparisons of three differentially detected signals are performed and analyzed by digital logic which determines the most likely sequence of data. In a first variant, pairs of adjacent data bits are detected simultaneously, whereas in a second variant, data bits are detected individually. The digital logic can be implemented using conventional logic gates.

Abstract: This invention discloses a method of accurately detecting the current bit in a SDPSK modulated signal at the receiver. The proposed method calculates the current bit from the past-detected bits and the past symbols. Each past symbol estimates the current bit. Each of these estimates is summed up to provide the final estimate of the bit. The proposed method for the reception of SDPSK modulated data improves the bit error rate performance. The proposed method can be applied in any communication system that uses SDPSK modulation.

Abstract: A DPSK demodulator demodulates DPSK signals in a computationally efficient manner to reduce the power requirements of the DPSK demodulator. A DPSK signal is received, digitized, converted to its in-phase (I) and quadrature (Q) components and filtered to remove noise. The I and Q components are processed to determine a relative phase and frequency offset. The phase is adjusted using the frequency offset. The adjusted phase is converted to an absolute phase, which is then mapped to a symbol representative of one or more bits of data.

Abstract: A variable load circuit for adjusting a phase of a differential signal including a first transistor having a first terminal adapted to receive a first component of the differential signal, a second transistor having a first terminal adapted to receive a second component of the differential signal and a second terminal coupled to a second terminal of the first transistor, and a variable current source coupled to a third terminal of both the first and second transistors. The variable current source generates a bias current based on a control signal. For each of the first and second transistors, a first capacitance is created between the first and second terminals, and a second capacitance is created between the first and third terminals. The first and second capacitances are each a function of the bias current and thus the control signal and operate to adjust the phase of the differential signal.

Abstract: Methods and apparatuses employing symmetrical phase-shift keying (SPSK) for data modulation and demodulation. Each symbol in a transmission signal carries n-bit information and is transmitted with one of 2n+1 directions. Half directions among the 2n+1 directions are regarded as default directions and the remaining are regarded as complementary directions. Each default direction has a corresponding complementary direction with a phase difference of ? and representing the same n-bit information as the default direction. The phase difference between any two successive symbols after modulation is less than or equal to ?/2.

Abstract: An active 90-degree phase shifter with LC-type emitter (source) degeneration is provided, which is practiced in an integrated circuit. The phase shifter comprises a first differential amplifier, having one first signal output end and comprising an inductor, a first transistor and a second transistor, wherein the inductor is connected to the emitters (sources) of the first and the second transistors; and a second differential amplifier, having one second signal output end and comprising a capacitor, a third transistor and a fourth transistor, wherein the capacitor is connected to the emitters (sources) of the third and the fourth transistors. Wherein the bases (gates) of the first and the fourth transistors are signal input ends, and the bases (gates) of the second and the third transistors are coupled together.

Abstract: In one embodiment, the present invention is a low-power, and high performance receiver including an IF demodulator for high data rate, frequency modulated systems, such as Bluetooth. The IF demodulator is implemented in analog domain for simplicity and lower power consumption and operates at an IF frequency. An IF demodulator comprises: a first IF differentiator for differentiating an I signal; a second IF differentiator for differentiating a Q signal; a cross-coupled multiplier for multiplying the differentiated I signal with the Q signal and multiplying the differentiated Q signal with the I signal to extract frequency information from the I signal and the Q signal; and a slicer for converting the frequency information to digital data.

Abstract: Demodulating an optical Differential Phase-Shift Keying (DPSK) signal is accomplished using a self-homodyne receiver for receiving the optical signal. A converter converts the optical signal received by the self-homodyne receiver into a representative electrical signal. A processor that processes the representative electrical signal using decision feedback multi-symbol detection in order to obtain a decision variable that indicates a differential phase-shift in the optical signal.

Abstract: This method reduces the variance of the estimation of the signal-to-noise rate in a multiuser digital communications system. These communications require a sending of a phase reference symbol prior to sending a information, where the estimation is made of the signal-to-noise rate in order to use a modulation with a maximum number of bits per symbol, maintaining a bit error probability in reception within certain given margins. The method minimizes and equalizes the variance of the samples obtained for the different values, even and odd of bits per carrier, which the system uses. The estimation is necessary for selecting the number of bits per carrier in order to be adapted to the channel and as back-up information in the event of using a receiver with diversity.

Abstract: A method and pre-processor for processing a MCPM signal including a phase multiplier for multiplying a MCPM signal by a scaling factor. The pre-processor also includes a frequency shifter for shifting the scaled MCPM signal to create a frequency offset. The pre-processing allows a MDPSK demodulator to demodulate the received MCPM signal. This Abstract is provided to comply with rules requiring an Abstract that allows a searcher or other reader to quickly ascertain subject matter of the technical disclosure. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).

Abstract: A method and device is provided for the detection of data symbols contained in a received radio signal, whereby each data symbol is allocated transmit-side a symbol value-specific PN sequence of successive PN chips in the chip clock and the PN sequences allocated to the data symbols are offset QPSK modulated. The method of the invention for incoherent detection provides for converting the received radio signal into a complex baseband signal sampled in the chip clock, generating a demodulated signal by differential demodulation of the complex baseband signal sampled in the chip clock, providing the derived sequences, calculating correlation results by correlating the demodulated signal with the derived sequences, and deriving, i.e., detecting, the values of the data symbols by evaluating the correlation results.

Abstract: A receive circuit for receiving a signal transmitted via an electric signal conductor. A first sampling circuit generates a first sample value that indicates whether the signal exceeds a first threshold level, and a second sampling circuit generates a second sample value that indicates whether the signal exceeds a second threshold level. A first select circuit receives the first and second sample values from the first and second sampling circuits and selects, according to a previously generated sample value, either the first sample value or the second sample value to be output as a selected sample value.

Abstract: An OFDM receiver apparatus receives an OFDM signal including a plurality of DBPSK signals transmitting identical information. An extraction unit extracts the plurality of DBPSK signals from the OFDM signal. A phase difference calculation unit calculates a phase difference between symbols of each of the plurality of extracted DBPSK signals. An accumulation unit accumulates the plurality of phase differences. A decision unit decides data transmitted by the DBPSK signals on the basis of an accumulation result.

Abstract: A demodulating unit demodulates a differential M-phase shift keying signal light by causing delay and interference. A phase-error detecting unit detects an error of a control phase amount of the delay and the interference caused by the demodulating unit. A control unit adjusts the control phase amount to a predetermined phase amount based on the error. A data processing unit monitors an error state of data signal that is demodulated by the demodulating unit. The control unit changes the control phase amount from the predetermined amount when the error state is in a predetermined state, and determines a reception state of the differential M-phase shift keying signal light based on an error that is detected after the control phase amount is changed.

Abstract: A technique is described for simultaneously and synchronously transmitting digital data and a clock signal in a digital integrated circuit, circuit board, or system. The technique is based on the phase shift keying (PSK) modulation of an RF high frequency carrier which is distributed on low impedance interconnection transmission lines. The PSK modulation contains the digital data while the carrier itself constitutes the clock signal, and the clock signal and digital data are transmitted in a synchronous manner. The carrier frequency may be near fT, the maximum operation frequency of the transistors. Since the digital data and clock signal are simultaneously transmitted on the same interconnection, the digital data never becomes skewed with respect to the clock signal, or vice versa.

Abstract: Demodulating a DPSK signal is accomplished using a saturated signal, and subjecting the signal to a low pass filter for noise reshaping. Higher order demodulation is then conducted on the reshaped signal. Sporadic constellation pull-away which occurs will result in random demodulation errors which will be correctly interpreted as in more conventional approaches using higher order demodulation.

Abstract: An efficient system and method for modulation and demodulation to achieve a high data rate using Bit-Interleaved Coded Modulation and OFDM uses either a coherent or a non-coherent transmission scheme using differential modulation. In order to maintain a high data rate impervious to sudden phase changes, a communication system uses an efficient constellation having multiple rings with different sizes and modulation/demodulation schemes utilizing this constellation. In power line communications, the channel gain information is obtained easily at a receiver (100) while the phase information is not. Thus, the communication system uses an absolute magnitude and differential phase coding for modulation and demodulation of the signals.

Abstract: A quadrature signal generator receives a differential input signal and generates quadrature output signals that are 90 degrees out-of-phase with each other. The quadrature generator includes a coarse stage and a plurality of refinement stages. The coarse stage generates quadrature signals that may have some phase error, and the refinement stages process the quadrature signals to reduce any phase error. The refinement stages receive quadrature signals from the output of the coarse stage, and processes the quadrature signals to reduce the phase errors. The coarse stage and the refinement stages are configured using delay circuits that can be implemented with inverter circuits, such as, for example, CMOS inverter circuits. In the refinement stages, corresponding outputs of the delay stages are averaged together to reduce the quadrature phase error.

Abstract: A demodulator of a differential detection system for a ?/4 shifted QPSK or DQPSK modulation wave in digital communication. The demodulator includes a differential detector connected to receive orthogonal components of the modulation wave, a corrector connected to receive an output of the differential detector for correcting a deviated distribution of signal points on a constellation, and a slicer/decoder connected to receive an output of the corrector. The slicer/decoder decodes a received bit from the signal points after the deviated distribution is corrected. The corrector has average calculators connected to receive respective outputs of the differential detector, and subtractors connected to receive the associated outputs of the differential detector and also to receive associated outputs of the average calculators for subtracting an average value of the outputs of the differential detector from the outputs of the differential detector.

Abstract: Methods, apparatus and systems for implementing an algorithm for N-symbol noncoherent processing of M-ary DPSK signals in a pilotless, wireless system is provided. The algorithm is carried out with (N?1) recurrent steps (iterations) plus a decision step. Each iterative step includes simple trigonometrical transformation of quadrature components of the current symbol and summation of the transforms with results of the previous step. A final N-symbol decision regarding the current transmitted symbol corresponds to the vector of maximum length, calculated after the (N?1)-th step of the iterative procedure. The general algorithm is optionally implemented with one or more intersymbol processors, one or more memory blocks for saving results of the intersymbol processors, and a decision block. In addition, shift registers for quadrature components of the received signal may be utilized.

Abstract: A technique of decoding a biphase signal comprises sampling the biphase signal to obtain phase sample values and sampling the biphase signal to obtain magnitude sample values. A first digital signal is derived from the phase sample values and associated bit combinations are formed from the first digital signal. A decision is made whether the bit combination is an erroneous bit combination, and a probability check is performed to obtain probability values that decide which parts of the erroneous bit combination are true and which are false. A corrected bit combination is generated from the obtained probability values, and a second digital signal is generated whose data states are formed from the valid bit combination and, in the presence of an erroneous bit combination, from the corrected bit combination.

Abstract: A method and apparatus for phase-domain semi-coherent demodulator including a receiver for receiving at least a phase component of an input signal. The phase domain semi-coherent demodulator may include a decision unit for forming a decision based on a delayed reference signal and the phase component of the input signal. In addition the phase domain semi-coherent demodulator may include a phase sum adder for subtracting the decision from the phase component of the input signal to form a rotated input phase, a second phase sum adder for subtracting the delayed reference signal from the rotated input phase to form a resulting signal, and a scaler for scaling the resulting signal to form an update signal. A third phase sum adder adds the update signal to the delayed reference signal to form a reference signal.

Abstract: A technique is described for simultaneously and synchronously transmitting digital data and a clock signal in a digital integrated circuit, circuit board, or system. The technique is based on the phase shift keying (PSK) modulation of an RF high frequency carrier which is distributed on low impedance interconnection transmission lines. The PSK modulation contains the digital data while the carrier itself constitutes the clock signal, and the clock signal and digital data are transmitted in a synchronous manner. The carrier frequency may be near fT, the maximum operation frequency of the transistors. Since the digital data and clock signal are simultaneously transmitted on the same interconnection, the digital data never becomes skewed with respect to the clock signal, or vice versa.

Abstract: A received continuous phase modulation (CPM) signal (which is formed with a set of pulse shaping functions) is approximated as a phase shift keying (PSK) modulated signal (which is formed with just the dominant pulse shaping function having the largest energy). Channel estimation and data detection are performed in accordance with the CPM-to-PSK approximation. A signal power estimate and a noise power estimate are obtained for the received CPM signal and have errors due to the CPM-to-PSK approximation. The difference ? between the energy of the dominant pulse shaping function and the energy of the remaining pulse shaping functions is determined. An approximation error is estimated based on the signal power estimate and the difference ?. A C/I estimate for the received CPM signal is computed based on the signal power estimate, the noise power estimate, and the approximation error estimate.

Abstract: A system for and method of modulating and demodulating a communication signal using differential quadrature phase shift keying (DQPSK) can include, upon receiving an inbound communication signal, demodulating the inbound communication signal by obtaining Pi/4 differential quadrature phase shift keying (DQPSK) symbols, translating the Pi/4 DQPSK symbols into quadrature phase shift keying (QPSK) symbols, and mapping the QPSK symbols to a pair of bits. Upon initiating an outbound communication signal, the system and method can include modulating the outbound communication signal by obtaining communication bits indicative of the outbound communication signal, translating the communication bits to three communication bits, and mapping the translated bits to DQPSK symbols.

Abstract: A technique of decoding erroneous biphase signals is disclosed comprising the following steps. First, phase and magnitude sample values (ps, bs) are formed, from which a first digital signal (d1) is derived. From this, associated bit combinations (St1, St2; Stp) are determined, and a decision is made as to whether the respective bit combination (St1, St2; Stp) is a valid combination (Sg1, Sg2; Sgp) or an erroneous one (Sf1, Sf2; Sfp). Probability values (Sw1, Sw2; Swp) are determined that decide which parts of the erroneous bit combination (Sf1, Sf2; Sfp) are probably true and/or which are probably false. Next, a corrected bit combination (Sk1, Sk2; Skp) is formed from the existing information. Finally, a second digital signal (d2) is generated as an output signal, whose data states are formed either from the valid bit combination (Sg1, Sg2; Sgp) or from the corrected bit combination (Sk1, Sk2; Skp).

Abstract: High speed data transmission schemes often use differential lines to reduce the effect of noise on the data signal. Unfortunately, the signal propagation on the positive and negative lines may be different, which leads to a signal skew problem. This document describes a novel way of compensating for differential line skew in data transmission lines.

Abstract: A demodulator and a demodulating method for a mobile phone are provided. In particular, the present invention can simultaneously perform operation of improving the demodulation error rate caused by such as noise and external feedback loop operation being correction after detected, and can reduce the current consumption by restraining the increase of the process time at the simultaneous operation with an external correction circuit after detected, and can improve the CN ratio (ratio between carrier power and noise power).

Abstract: The present invention relates to a method for receiving CDMA signals with synchronization being obtained through double delayed multiplication, and an associated receiver. According to the invention, the correlation signal undergoes double delayed multiplication. Synchronization is established on the signal thus generated. Applied to digital communications, in particular with mobile phones.

Abstract: A method and apparatus that differentially encodes and decodes data symbols in dual domains is taught. Data packets are encoded, transmitted, and decoded during a plurality of symbol intervals on a plurality of sub-carriers. Encoding and decoding are accomplished across both the time and frequency domains such that the minimum number of carrier states are employed as reference only states that do not encode a symbol of data in and of themselves. A rule of adjacency is followed, both across time and frequency, so that decorrelation is minimized. Any modulation scheme that is applicable to differential encoding and decoding can be utilized. Communication systems that couple via radio waves, through metallic conductors, or over fiber optic paths can be employed.

Abstract: The present invention discloses an improved method of timing synchronization with transmitted data packets in a receiver on a communication channel using differential phase shift keying (DPSK) modulation—especially an RF wireless communication channel. The invention reduces the complexity of the circuits, especially the multipliers, required for digital signal processing. The invention also increases performance compared to previously known methods.

Abstract: A frequency offset may be determined by detecting phase information for both a one-symbol difference and a two-symbol difference of a received known signal. Half a value representing the phase information detected for the two-symbol difference is averaged, for a particular interval, with a value representing the phase information detected for the one-symbol difference. The frequency offset is determined from the average.

Abstract: A differential detector generates, for each symbol, a phase difference between phase information received from a phase detector and one-symbol-delayed phase information of the received phase information. The one-symbol-delayed phase information is transferred to a differential detector, which generates, for each symbol, a phase difference between the one-symbol-delayed phase information and two-symbol-delayed phase information. The generated phase differences are fed to another differential circuit, which in turn generates, for each symbol, a difference between both received phase differences to produce phase-difference difference information. A clock regenerator circuit extracts symbol timing from the phase-difference difference information and regenerates clock signals synchronizing with the extracted symbol timing.

Abstract: A technique is described for simultaneously and synchronously transmitting digital data and a clock signal in a digital integrated circuit, circuit board, or system. The technique is based on the phase shift keying (PSK) modulation of an RF high frequency carrier which is distributed on low impedance interconnection transmission lines. The PSK modulation contains the digital data while the carrier itself constitutes the clock signal, and the clock signal and digital data are transmitted in a synchronous manner. The carrier frequency may be near fT, the maximum operation frequency of the transistors. Since the digital data and clock signal are simulaneously transmitted on the same interconnection, the digital data never becomes skewed with respect to the clock signal, or vice versa.

Abstract: A soft-output decoder that uses a-priori likelihood values to compute metrics while decoding a received data stream also uses the a-priori likelihood values to decide whether or not to compute the metrics for each position in the received data stream. Unnecessary computation can thereby be avoided, saving time and power. In an iterated soft-output decoding scheme, the soft-output decoder may decide whether or not to compute metrics for each position in the next iteration of the soft-output decoding process. These decisions may also be used to decide when to terminate the decoding process.

Abstract: The present invention relates to a circuit and method for symbol timing recovery in phase modulation systems. First, phase differences of in-phase signals and quadrature signals in a polar coordinate are generated at the same sampling points of neighboring symbols. Second, an operator is generated by taking a square of a value subtracting the phase difference from a default phase value. Third, the sums of phase differences of every sampling point in a symbol are computed to determine an optimal sampling point in a symbol period and correctly recover symbol timing of signal sequences. By the above properties, the present invention has a simple structure and can shorten an execution time.

Abstract: A tangent angle computation device and associated DQPSK decoder. The computation device uses an eight-bit divider and a four-quadrant technique for finding a quantized angular value from an incoming signal. The quantized angular value is subsequently used to decode the incoming signal.

Abstract: The present invention discloses an improved method of timing synchronization with transmitted data packets in a receiver on a communication channel using differential phase shift keying (DPSK) modulation—especially an RF wireless communication channel. The invention reduces the complexity of the circuits, especially the multipliers, required for digital signal processing. The invention also increases performance compared to previously known methods.