Abstract: A digital demodulator and method for demodulating digital data representing a phase shift keyed (PSK) signal are provided. The demodulator comprises a phase detector, automatic frequency controller, automatic timing recovery controller, data decoder, and unique word detector. According to the method of the present invention, a PSK signal is received and digitized to substantially remove the signal's amplitude characteristics. The phase detector receives an input of the digital data and based upon transitions in the data from a high state to low state and from a low state to a high state, provides phase estimates. The phase estimates are converted by the data decoder into binary data representing the symbols transmitted to form the PSK signal. A number of overlapping windows of digital data are used to determine phase estimates.

Abstract: A digital radio communication system achieves low envelope variations in a transmitted signal by encoding digital information as phase angle differences in a transmitted radio signal and by constraining the maximum possible phase angle difference. This reduction in envelope variation relaxes the linearity requirements for a desired level of distortion suppression of a radio frequency (RF) amplifier means employed for transmitting the radio signal. In addition, lower envelope variations imply a higher average transmit power for a given maximum transmitted power, thereby extending range and battery life.

Abstract: A circuit and method for demodulating a .pi./4-DQPSK (differentially quadrature phase shift keying) modulated signal. A receiving .pi./4-DQPSK modulated signal is shifted to a base band and simultaneously separated to an I channel and Q channel. The separated I channel and Q channel signals are converted into digital data. The digitally converted data is stored in a memory and decoded to binary data by phase comparison or Viterbi algorithm.

Abstract: A method is disclosed of demodulating a signal (20) modulated by differential quadrature phase shift keying so that two bits of information are coded into each symbol period. The method comprises using a high frequency clock to determine the time taken (t.sub.1, t.sub.2, t.sub.3, t.sub.4), for the modulated signal to execute a predetermined number of cycles, such as 21, in the symbol period (T) and comparing the time thereby determined with the time (t.sub.o) of execution of the predetermined number of cycles for an unmodulated signal.

Abstract: A carrier tracking loop that uses a frequency locked loop (FLL) and incorporates synchronized matched filters to minimize complexity of the system. The synchronized matched filters eliminate out-of-band interference while minimizing computation. The carrier tracking loop has an improved error signal generation to extend a frequency range and by employing error signal normalization, which extends the dynamic range of the amplitude of the input signal and allows the frequency to flywheel when signal fading occurs.

Abstract: In a signal demodulating and decoding apparatus, plural demodulators and decoders corresponding to plural modulation systems are provided respectively, and these are operated at the same time, and respective decoding results are outputted. Further, the signal demodulating and decoding apparatus evaluates decision error amounts of respective demodulators and selects the decoding data by the demodulator and the decoder having the least decision error amount. When an operation device for adaptively correcting the parameters used within the demodulator is provided so that decision errors on inputting the decision results of the demodulator into the decoder are made small, the decision error amount inputted to the operation device is selected in a manner similar to that above.

Abstract: A selectable demodulator (32) operates in the phase domain to implement a coherent demodulation path (40) and a differentially coherent demodulation path (42). The coherent path (40) includes a differential encoder circuit (46) to produce coherently demodulated differential data. Magnitude converters (62, 62') convert phase errors in each path into magnitude values. A comparison circuit (66) compares magnitude values from the two paths (40, 42) and selects the path encountering the least phase error. A selection circuit (60) provides data codes demodulated in accordance with the selection.

Abstract: A .pi./4 delay spread detection and compensation arrangement effectively detects distortion due to multipath delay spread in a digital channel and compensates for this distortion with minimum circuit complexity. An improvement in the bit error rate performance for a differential detector in the receiver is achieved through use of a detected direct current (DC) component, which is proportional to the amount of multipath delay spread on the digital channel. This DC component is used in the differential detector for compensating for this delay spread. In addition, the differential detector also provides a channel quality measure of the level of delay spread on the digital channel for use by the receiver in selecting either the differential detector or an equalizer for decoding of the data on the digital channel.

Abstract: A demodulator (20) demodulates a received signal having phase information into a demodulated signal by differential detection. The demodulator comprises a delay section (22-1 to 22-3) which is supplied with an input signal based on a received signal. The delay section delays the input signal to produce first through third delayed signals which have first through third delayed times different from one another. A differential detecting section (23-1, 23-2) carries out differential detection in accordance with the input signal and the first through the third delayed signals to produce first and second output signals. A first correcting section (24) corrects the first delayed signal on the basis of the first output signal to produce a first corrected signal. A second correcting section (25) corrects the second delayed signal on the basis of the second output signal to produce a second corrected signal.

Abstract: An intermediate frequency (IF) to baseband frequency signal converter for decoding an analog IF signal using phase information contained in the IF signal includes a first signal generator for generating an analog square wave signal from the IF signal. The signal converter also includes a second signal generator for generating a local phase reference signal, and a phase difference determinator for determining at a particular sampling interval a phase difference between a phase of the analog square wave signal and a phase of the local phase reference signal, wherein the phase difference represents a symbol which the signal converter has decoded from the IF signal.

Abstract: A clock recovery signal generating circuit for generating a clock recovery signal includes a plurality of detection axis cross detectors varied in magnitude of detection axis admitting a phase difference signal, for detecting the time at which the phase difference signal crosses the detection axis of a prescribed magnitude. A locus sorter discriminates and sorts the locus of a change in the phase difference signal based on the data of timing obtained by the detection axis cross detectors and generates a timing adjusting signal in conformity with the result of the sorting. Timing control generates a clock recovery signal by correcting the data of timing obtained by one of the plurality of detection axis cross detectors designated by the timing adjusting signal with the time designated by the timing adjusting signal.

Abstract: A clock synchronization circuit for use in a baseband demodulator of communication equipment of a digital modulation type, in which detection data is subjected to an interpolating operation with respect to at least one point between adjacent two sample values of the detection data, subjected to a conversion into one-bit data indicative of a positive or negative value, and then passed through a one-bit-input band pass filter to perform phase error detection. Consequently, clock synchronization accuracy is improved while preventing a sampling rate and circuit scale from being made large.

Abstract: A PSK signal demodulating apparatus having a clock extracting circuit. The clock extracting circuit includes a counter that is operable by a clock having a frequency N time the carrier frequency of a phase modulated signal such as a .pi./4 shift DQPSK modulated wave is latched at the leading edge timing of the above signal thereby to obtain phase data. Also, a difference between these phase data is calculated at mod.2.pi. thereby to extract a clock component.

Abstract: A method for demodulating the carrier signal of powerline communication networks. The method involves demodulating an HDLC data body that had been modulated through differential phase shift keyed modulation. Under the method, the data body is split with data input into a single bit digital delay circuit which outputs a delayed or "previous" binary data bit. A "present" binary data bit is input to one input of an XNOR circuit and the previous binary data bit is input into a second input of the XNOR circuit. When the present binary data bit and the previous binary data bit have unlike phases the XNOR circuit outputs a first binary data bit value. When the present binary data bit and the previous binary data bit have like phases, the XNOR circuit outputs a second binary data bit value. Preferably, the demodulated data is input into a post detection filter.

Abstract: Within the differential detection demodulator, the received signal is first quantized by a limiter amplifier and then subjected to frequency conversion by a frequency converter including: an exclusive OR element; a running average generator consisting of a shift register and an adder; and a comparator. In response to the output of the frequency converter, the phase comparator outputs a relative phase signal representing the phase shift of the received signal after frequency conversion relative to the phase signal representing the phase shift of the received signal after frequency conversion relative to the phase reference signal. The phase comparator includes: an exclusive OR element; an absolute phase shift measurement means consisting of an adder and D flip-flop arrays and; and a D flip-flop serving as a phase shift polarity decision means.

Abstract: Receiver (5) for digital signals which comprises a differential decoding circuit deinterleaving and convolution decoding circuit for received digital signals. The differential decoding circuit restores each received symbol to the original phase it had on transmission. This permits the calculation of optimum metrics(M.sub.k.sup.a,M.sub.k.sup.b)which are used by convolution decoding circuit to provide optimum decoding of received symbols.

Abstract: A plurality of reception branches receive digital modulated signals and convert received digital modulated signals into intermediate frequency signals having frequency differences having a predetermined relationship with a modulation baseband signal. An adder adds the intermediate frequency signals converted by the plurality of reception branches. A delayed and differential detection section delays and differentially detects a sum signal from the adder. A post detection filter filters a delayed and differentially detected signal from the delayed and differential detection section at a bandwidth higher than a Nyquist frequency of the received digital modulated signals, thereby outputting demodulated signals of the received digital modulated signals.

Abstract: A data receiver receives differential phase-shift keyed (DPSK) signals, and filters the signal by a process including frequency conversion, under the control of an estimated carrier frequency (f.sub.re), to produce a filtered output signal which is applied to a DPSK demodulator. The filtering compensates for the Doppler frequency errors, and reduces the phase error. The estimated frequency is determined by second and third controllable filters, which filter the DPSK carrier signal at frequencies above and below the estimated carrier frequency by an offset frequency which depends on the data rate. A first frequency error estimate is made in a processor coupled to the second and third filters, from the ratio of the amplitudes of the first and second filter output signals. A second-order tracking loop is coupled to the processor for averaging the frequency error estimate over a predetermined number of bits, to generate the estimate of the carrier frequency.

Abstract: A data demodulator wholly consisting of digital circuits for time division multi-access (TDMA) signals subjected to differential phase-shift-keying (DPSK) is provided. The data demodulator generates a phase difference signal by subjecting .pi./4-shift quadrature phase-shift-keying (.pi./4 QPSK) signals to delayed detection of phase in synchronism with N-phase clock signals (where N is a positive integer), and reproduces a resulting phase difference signal into decision data. A first such data demodulator detects decision errors from the phase difference signal and decision data, and achieves symbol synchronism by sampling the decision data in a clock signal phase involving little decision error. A second such data demodulator supplies the phase difference signal after correcting its D.C. offset due to a frequency drift. In these two data demodulators, the formulas for computing said decision errors and correction values are flexibly varied according to preceding burst information.