Abstract: An apparatus for and a method of determining the envelope of a complex baseband signal having an in-phase component I and a quadrature component Q by determining (I2+Q2)½ for sampled values of the baseband signal. The maximum and minimum values of I and Q are detected by detecting the larger of I and Q in a first detection circuit (18) and the smaller of I and Q in a second detection circuit (20). A value x=½{(the detected minimum value)÷(the detected maximum value)}2 is calculated in a first calculation circuit (22). The value of (I2+Q2)½ is then calculated based on the value of x. In a first embodiment the value of (I2+Q2)½ is calculated in a second calculation circuit (24, 26, 28, 30, 32, 34, 36, 38) as the (the detected maximum value)×(1+x)/2+½(1+x−x2+x3−x4+x5−x6).

Abstract: A network interface is presented that receives packet data from a shared medium and accomplishes the signal processing required to convert the data packet to host computer formatted data separately from receiving the data packet. The network interface receives the data packet, converts the analog signal to a digitized signal, and stores the resulting sample packet in a storage queue. An off-line processor, which may be the host computer itself, performs the signal processing required to interpret the sample packet. In transmission, the off-line process converts host-formatted data to a digitized version of a transmission data packet and stores that in a transmission queue. A transmitter converts the transmission data packet format and transmits the data to the shared medium.

Abstract: An intradyne receiver provides a received intradyne signal X which comprises at least two, mutually phase-shifted, and N-ary phase shift keyed intradyne part signals Xk. Here N=2 for binary and N=4 for quaternary PSK. For carrier recovery purposes their frequency is multiplied by a factor of N in an intradyne frequency multiplier FM. After passing a lowpass filter TPY the filtered, frequency-multiplied intradyne signal is passed through an intradyne frequency divider IDF1, IDF2 with carrier intradyne signals C1, C2 as output signals that allow to demodulate the received intradyne signal X. The intradyne frequency divider undertakes more than one state change while changing the phase of the carrier intradyne signal by 2&pgr;/N. It can be formed as a regenerative intradyne frequency divider. When used for coherent optical data transmission this allows to tolerate comparatively large laser line widths.

Abstract: An apparatus for generating quadrature phase signals in a half-rate data recovery circuit, which is adapted to generate a first and a second clock signals having the same frequency and being 90 degrees out of phase with each other. The apparatus for generating quadrature phase signals mainly comprises a base selector, a first phase interpolator and a second phase interpolator. The base selector generates, based on a region control signal, a pair of phase region boundaries for the first clock signal as well as a pair of phase region boundaries for the second clock signal by using a plurality of reference clock signals. The first and second phase interpolators perform, based on a position control signal, weighted average processes for the two pairs of phase region boundaries, respectively, to thereby obtain the first and the second clock signals.

Abstract: Briefly, a method and apparatus to calculate cross-correlation values of complex binary sequences are provided. The apparatus may include a transformation unit and a cross-correlator. The cross-correlator may include a cross-correlation controller to provide, based on a type bit and a sign bit, a real component and/or an imaginary component of signals of complex binary sequences to a real accumulator and/or to an imaginary accumulator.

Abstract: A method and offset removing apparatus for removing DC offset from a digital baseband signal value pair included in a set of digital baseband signal value pairs is described. The digital baseband signal value pairs, when plotted on a complex signal space I-Q diagram, lie on a predetermined figure. The I and Q coordinates of the central point of this predetermined figure are determined by a two-dimensional fitting of this figure through a subset of signal value pairs included within the set. These coordinates of this center point are subsequently subtracted from the I and Q coordinates of the digital baseband signal.

Abstract: A wideband fast-hopping receiver front-end uses direct digital synthesis (DDS) to provide quadrature LO signals to the front-end's mixers. A DDS circuit stores multiple digital word sequences which represent desired waveforms, and outputs desired sequence pairs to a pair of DACs in response to a clock signal and a command signal. The DACs convert the sequences to analog signals, which are filtered and squared as necessary to provide quadrature LO signals to the mixers. Frequency hopping is accomplished by changing the command signal, which causes a different pair of sequences to be output and the frequency of the LO signals provided to the mixers to be changed. Active image rejection is combined with DDS LO generation to provide faster frequency hopping. The front-end is combined with an ADC and a communications signal processor to provide a complete system, all of which can be integrated together on a common substrate.

Abstract: When reception of a multiplexed wave to be PSK-modulated of BPSK, QPSK, and 8PSK is started, a selector (16A) of a demodulating circuit (1A) reads high-order three bits &Dgr;&phgr;(3) of phase error data corresponding to I and Q symbol streams out of one phase error table (15-1) for BPSK among phase error tables provided for each modulation system and each phase rotation angle. A received-signal-phase rotation angle detecting circuit (8A) detects phase rotation angles of portions corresponding to bits (1) and (0) of a frame-synchronizing signal of a received symbol stream from the &Dgr;&phgr;(3) and the MSB of I symbol stream and outputs the phase rotation angles to a remapper (7) to make the remapper perform absolute phasing.

Abstract: A circuit for providing phase shifted I and Q output signals from a received FSK modulated signal and the method of its operation. The circuit includes apparatus for receiving an FSK modulated signal, first, second and third mixers, to which the received FSK modulated signal is applied, a local oscillator, generating an oscillator signal and phase shifters providing first, second and third phase shifted versions of the oscillator signal to the first, second and third mixers to produce first, second and third mixer output signals which are likewise phase shifted. The mixer output signals are provided to summing circuits providing an I output signal corresponding to the difference between the first and second mixer output signals a Q output signal corresponding to the difference between the second and third mixer output signals.

Abstract: A direct conversion receiver which compensates for interfering signals introduced during processing. Direct conversion is achieved using direct detection techniques which introduce interfering signals which become inseparable from the wanted signal. A pilot signal (202) is added to an input RF signal (200) prior to passing the summed signal (206) to four separate paths (210, 212, 214, 216). Signal (206) is modulated so that the phase is different in each path using local oscillator signals and switches (230, 232, 234, 236), and then digitised by ADCs (260, 262, 264, 266). Correction is introduced into respective paths (210, 214) by cancellation loops (310, 314) to compensate for unwanted signals prior to the paths being grouped so that the pairs of digitised signals (272, 300; 276; 304) which are 180° out of phase with one another are subtracted to provide output inphase and quadrature signals (220, 224).

Abstract: A phase detection apparatus for receiving an I-channel signal an a Q-channel signal as a received signal modulated with a quadrature phase-shift keying and compensating a phase rotation error of the received signal, includes: a phase detector for detecting a phase error through the use of the I- and Q-channel signals and providing an error signal; a shifting unit for shifting said I-channel signal by a plurality of predetermined different numbers of bits and providing shifted I-channel signals; a first multiplexing unit, in response to an external selection signal, for selecting signals among said shifted I-channel signals; a subtracting unit for providing difference signals between said selected signals and said Q-channel signal; a comparison unit for comparing said difference signals with a reference signal and producing logic signals; a logic gate for producing a logically ORed signal of said produced logic signals; and a second multiplexing unit, in response to said ORed signal, for selecting a signal fro

Abstract: Reduction in an output level of an IQ demodulator starts when a QPSK modulation signal is at a first level. Reduction in an output level of a first variable attenuater occurs when the QPSK modulation signal is at a second level higher than the first level. Reduction in an output level of a second variable attenuater starts when the QPSK modulation signal is at a third level higher than the second level.

Abstract: The invention relates to a system for transmitting TDMA packets between interactive terminals and a head station via a transmission medium, in which the receiver effects a oversampling of the received signal so as to retrieve the optimal sample corresponding to the transmitted symbol. The invention proposes a method of recovering this optimal sampling instant very rapidly by performing a polynomial interpolation computation between the generated oversamples so as to derive the optimal sampling instant and by filtering the received signal by means of a low-pass filter centered at the optimal sampling instant.

Abstract: A QPSK modulation scheme uses a data spreading mechanism to rob a relatively limited portion of available transmitter power, and inject into the QPSK waveform a prescribed amount of carrier signal power, through which detection and non-regenerative extraction of the carrier at the receiver may be achieved without incurring a signal-to-noise degradation penalty. In addition, the injected carrier-based modulation scheme of the invention may employ high performance forward error correction coding, to significantly reduce the signal power required for achieving a very low energy per bit-to-noise density ratio (Eb/N0)—on the order of one to zero dB.

Abstract: Converting section 201 converts I signal and Q signal in phase modulated signal of which delay wave distortion is cancelled into I′ signal and Q′ signal shown in I′-Q′ plane, respectively. Positive/negative decision section 202 outputs decoded bit in I′ signal as bit 3N+1. Positive/negative decision section 205 outputs an inversely rotated value by decoded bit in Q′ signal as bit 3N. Subtractor 206 outputs a decoded bit obtained by carrying out subtraction using the absolute value of I′ signal and absolute value of Q′ signal as bit 3N+2. Thus, it is possible to carry out decoding of phase modulated signal while keeping apparatus size and calculation amount.

Abstract: An image reject mixer arrangement 1 comprises a transconductor 2, first and second mixer cores 3 and 4, first and second phase shifters 5 and 6 and a summer or combiner 7. The mixer arrangement 1 receives a single-ended RF voltage signal on a terminal 8, a differential local oscillator signal on I-LO terminals indicated at 9 and a 90° phase shifted differential local oscillator signal on Q-LO terminals 10, and provides differential IF output signals on output terminals 11. From the output of the transconductor 2 to the output of the combiner 7, the image reject mixer arrangement 1 carries signals in what can be described as a “current mode”, i.e. it is the current, not the voltage, which conveys the desired signal. In this current mode, it is advantageous to provide each active circuit block with a high output impedance and a low input impedance wherever possible.

Abstract: A method and apparatus for computing soft decision input metrics to a turbo decoder includes circuits associated with eight-ary phase shift keyed (8PSK) modulation and sixteen-ary quadrature amplitude modulation (16QAM). In both implementations log-likelihood ratio (LLR) metrics on code symbols are estimated as products of various constant values and various combinations of the in-phase and quadrature components of a demodulated soft decision. In the implementation associated with the 16QAM modulation scheme, an estimate of the carrier-signal-to-interference (C/I) ratio is also used to estimate some of the LLR metrics. Estimates of the LLR metrics may also be obtained in association with generalized square QAM and M-ary PSK modulation schemes including, e.g., 64QAM, 256QAM, and 16PSK.

Abstract: A radio receiver has an input coupled to first and second quadrature related low-IF frequency translation stages generating IF signals at substantially half the channel bandwidth or channel spacing. The IF signals which may be optionally filtered in a pre-filter, for example a polyphase filter, are applied to first and second cross-coupled continuous time, low pass Sigma-Delta modulators. The modulators include transconductor-capacitor integrators, all but the first integrators of which are cross-coupled by gyrators set to resonate at the IF frequency. Outputs of the Sigma-Delta modulators include 1 bit oversampled signals. The oversampled signals may be filtered in first decimation stages which provide anti-aliasing. The decimated signals are derotated and decimated in a second decimation means to provide outputs at base band. The base band outputs are equalized and demodulated to provide an output. The input signal may be frequency translated to zero IF and then filtered in low pass filters.

Abstract: A simplified method for frequency offset estimation in a TDMA cellular PCS environment using &pgr;/4-shifted DQPSK comprises the steps of multiplying a complex conjugate of a received complex-valued symbol and a succeeding symbol to produce a comparison vector having an angle equal to the phase angle between the received complex-valued symbol and the succeeding symbol, rotating the comparison vector so that the angle thereof is between 0° and 90°, and estimating the frequency offset by determining a constant deviation of the phase angle from an ideal phase angle value of 45° by calculating an average phase angle for a plurality of successive comparison vectors or correlating the rotated comparision vector against a bank of unit vectors to determine a maximum correlation.

Abstract: A radio signal receiving apparatus and a method of radio signal receiving for improving the receiving characteristic by limit the excessive compensation in the AFC circuit are realized. The base band phasing signal output from the phase detector is input to the AFC unit. In the AFC unit, the base band phasing signal is supplied to two ways, one is supplied to a series processing path of the frequency error detecting part, the integrating equalizing part, the numerical limiting part and the integrator, and another is supplied to the adder.

Abstract: An 8-ary PSK demodulation apparatus for receiving an input signal Rk(Xk, Yk) comprised of a kth quadrature-phase component Yk and a kth in-phase component Xk, and for generating soft decision values &Lgr;(sk,0), &Lgr;(sk,1), and &Lgr;(sk,2) for the input signal Rk(Xk, Yk) by a soft decision means. A calculator calculates Zk by subtracting a level |Yk| of the quadrature-phase signal component Yk from a level |Xk| of the in-phase signal component Xk, and outputs the Zk as a first soft decision value. A first selector selects the Zk or reverse −Zk, according to an MSB of the quadrature-phase signal component Yk. A second selector selects the Zk or the reverse −Zk according to an MSB of the in-phase signal component Xk. A third selector selects an output of the second selector or a value “0” according to an MSB of the Zk.

Abstract: A method, device and computer program product for a demodulator 200 for use in a communications channel 110, including a channel estimator section 204 configured to receive a modulated signal r[k] over the communications channel 110 and generate reference symbols based on the modulated signal r[k]; a fuzzy adaptive filter (FAF) parameter determination section 206 coupled to the channel estimator section 204 and configured to receive the modulated signal r[k] and the reference symbols and generate signal samples based on the modulated signal r[k] and the reference symbols; and a detector section 208 coupled to the FAF parameter determination section 206 and configured to receive the signal samples and generate a soft decision signal and a hard decision signal based on the signal samples.

Abstract: A method and apparatus are provided for combining pilot symbols and Transmit Parameter Signalling (TPS) channels within an OFDM frame. The method uses Differential Space-Time Block Coding to encode a fast signalling message at an OFDM transmitter. At an OFDM receiver, the encoded fast signalling message can be decoded using differential feedback to recover information about the channel responses that would normally be carried by pilot symbols. In wireless data transmission employing adaptive modulation and coding, an instantaneous channel quality measurement, independent of the origin of interference for example, neighboring-cell interference, white thermal noise, or residual Doppler shift is provided. Using the correlation between a signal which has been symbol de-mapped, and one which has also been soft decoded and re-encoded, a channel quality indicator is produced. Another embodiment uses TPS data as pilot symbols by decoding TPS and then re-encoding.

Abstract: Angle-modulated signals are transmitted in a communications system, in which coding information has been inserted into the transmitted data at regular intervals. The coding information is phase-modulated together with the transmitted data. This coding is used for pulse shaping, so that the receiver can recover the digital transmitted data with less implementation complexity and without carrier phase control by using appropriate signal processing.

Abstract: In a direct conversion receiving apparatus, a first frequency converting section includes a first capacitor, and frequency-converts a high frequency reception signal into a first base band signal using a first local oscillation frequency signal. Then, the; first frequency converting section removes a DC component from the first base band signal using the first capacitor, and converts the first base band signal with the DC component removed into a first digital signal. A second frequency converting section includes a second capacitor, and frequency-converts the high frequency reception signal into a second base band signal using a second local oscillation frequency signal which is different from the first local oscillation frequency signal by 90 degrees in phase. Then, the second frequency converting section removes a DC component from the second base band signal, using the second capacitor, and converts the second base band signal with the DC component removed into a second digital signal.

Abstract: A digital modulator and digital demodulator with quadrature amplitude modulation (QAM) schemes, which are designed to modulate or demodulate RZ-coded baseband signals. The digital modulator comprises first to fourth roll-off filters and a first and second inverters connected to the second and fourth roll-off filters. It also comprises a parallel-to-serial converter to successively selects the outputs of the first roll-off filter, third roll-off filter, first inverter, and second inverter. A D/A converter converts the selected digital signal stream into an analog signal. The roll-off filters and inverters operate at a predetermined clock frequency, while the parallel-to-serial converter and the D/A converter work at a frequency four times the predetermined clock frequency. The digital demodulator reverses the above modulation process to reproduce the baseband signals.

Abstract: Disclosed is a digital communication system for mobile communication, which has: a transmitter for mixing and outputting outputs from two independent and equivalently synchronized transmitting circuits in a &pgr;/4 shift QPSK modulation system; and a receiver for receiving a mixed wave transmitted from the transmitting circuits and demodulating the received signal by using information as to its phase and amplitude.

Abstract: A method and apparatus to efficiently calculate log-likelihood ratios for each bit within M-ary QAM modulated symbols transmitted in a communication system. The method and apparatus utilize characteristics of square Karnaugh mapping of the QAM symbol constellation in order to reduce the number of distance calculations needed to determine the log-likelihood ratios for each of the bits within a demodulated symbol. The reduction in the number of calculations affords significant reduction in the time needed to determine log-likelihood ratios, especially for higher order M-ary QAM systems.

Abstract: An apparatus for and method of reducing the soft output information packet to be computed by a soft symbol generator. The reduced soft output information packet generated by the soft symbol generator is subsequently used by a soft symbol to soft bit mapper which functions to convert soft symbol decision information into soft bit decision information. A symbol competitor table is constructed that includes the most likely symbol competitors for each bit of the symbol. The table is populated with m entries for each possible symbol value, where m represents the number of bits per symbol. Symbol competitors are retrieved from the table in accordance with the hard decision. Soft symbol information is generated only for the symbol competitors rather than for all possible symbol thus substantially reducing the size of the information packet. The method of the invention can be performed in either hardware or software. A computer comprising a processor, memory, etc.

Abstract: A quadrature output oscillator device (22) includes a first voltage controlled oscillator (40) and a second voltage controlled oscillator (44). The second voltage controlled oscillator (44) generates a first output (C) and a second output (D) to drive a first amplifier (42). The second output (D) of the second voltage controlled oscillator (44) is a quadrature-phase signal component output (Q) of the quadrature output oscillator device (22). The first voltage controlled oscillator (40) generates a first output (A) and a second output (B) to drive a second amplifier (46). The second output (B) of the first voltage controlled oscillator (40) is an in-phase signal component output (I) of the quadrature output oscillator device (22). The first amplifier (42) generates feedback signals for the first output (A) and the second output (B) of the first voltage controlled oscillator (40).

Abstract: A receiver for signals generated using a modulation scheme such as quadrature-phase shift-keying (QPSK) modulation. The receiver characterizes the variance in the detected signal constellation and, when appropriate, adjusts at least some part of its processing in order to reduce power consumption or error rate. For example, when the variance is low and full receiver operation is not required to achieve accurate phase detection, one or more of the following changes are made to reduce power consumption: the resolution of the A/D converter is reduced, the precision of digital filtering is reduced, and/or one or more of the digital filters are turned off. If the variance in the detected signal constellation should increase, appropriate changes may be made to gradually restore the operations of the full receiver as needed to reduce error rate. In this way, the receiver can efficiently regulate its power consumption without jeopardizing the accuracy of its signal processing.

Abstract: A demodulator for use in a satellite communication system, which is operative for receiving a modulated signal having a data rate R (i.e., the demodulator receives R input samples per second). The demodulator includes a demultiplexer circuit having N shift registers, which functions to receive the R data samples per second as an input signal. The demultiplexer circuit operates to input the R input samples sequentially into the N shift registers such that each of the shift registers receives input samples at a data rate of R/N samples per second. The demodulator further includes signal recovery circuitry for processing the input samples contained in each of the N shift registers so as to regenerate the data contained in the incoming modulated signal transmitted by the satellite.

Abstract: A method (100) for simplifying soft-decision metric decisions in a M-ary modulation system includes determining (102) a single function for a soft-decision metric for each bit in a symbol by restricting the set of all possible Gray-coded constellation points to those closest to a boundary between a bit value of 0 and 1 for each bit in the input symbol and applying a predetermined function corresponding to the range of restricted constellation points to the entire possible range of symbols. A next step includes inputting (104) a symbol having real part, x, and an imaginary part, y. A next step includes (106) setting a soft-decision metric for each bit in the symbol using the predetermined function from the determining step (102).

Abstract: A method for phase encoding DPSK and N-PSK which maintains phase continuity and which does not require any reference symbols when using N-PSK. A sequence of known DPSK phases are encoded with respect to an initial phase. The N-PSK phases are then all offset by this same initial phase. The known DPSK phases can be used at a receiver to determine a sum consisting of the initial phase and any further phase shift introduced by the channel, and this sum is used to decode the unknown N-PSK phases. The method is more generally applicable to any case where a switch between a phase encoding method which requires an absolute phase reference and a phase encoding method which does not have an absolute phase reference is to be implemented on a single carrier or channel.

Abstract: A communication system (10) includes a transmitter (12) which induces in a communication signal (16), a first component of in-phase to quadrature phase (I-Q) imbalance and a receiver (14) which adds a second component of I-Q imbalance. A digital, intermediate frequency (IF) I-Q balancer (38) compensates for the receiver-induced I-Q imbalance so that total distortion is sufficiently diminished and a data directed carrier tracking loop (60) may then perform carrier synchronization to generate a baseband signal (70). An adaptive equalizer (64) within the carrier tracking loop (60) may then effectively operate to compensate for additional distortions, such as the transmitter-induced I-Q imbalance.

Abstract: A searcher is centered on frequency bins to search for an incoming signal. The frequency locked loop generates an initial phase signal and a phase increment signal that are input to an accumulator. The accumulator accumulates the phase increments over a predetermined interval. After the interval, the accumulator generates a control signal that instructs a rotator to perform a phase rotation function.

Abstract: A system for balancing a signal having I and Q components includes means for cross correlating the I and Q components to produce a cross correlation product; means for adjusting the gain of each I and Q signal component in accordance with said cross correlation product; and means for adding one component with the adjustable gain of the other component to produce a phase-balanced signal.

Abstract: The efficient quadrature amplitude modulator of the present invention allows from 6 to 8 independent compressed channels to occupy a 6 MHz bandwidth while reducing processing power by 33 percent for 8 levels of modulation offered by 64-QAM and by 25 percent for 16 levels of modulation offered by 256-QAM. The modulator achieves this efficiency using an improved digital filter architecture combining the modulation and filtering with post filtering carrier combination. The QAM modulator presented is implemented with a reduction in the total number of binary parallel multipliers. To increase operational throughput, the speed of operation increases with the use of LUTs (look-up tables) storing precomputed filter weighting coefficients. The reduction in multipliers is also achieved by using post filtering carrier combination which similarly reduces the number of MAC operations performed during filtering.

Abstract: A compensation circuit for phase modulation systems, such as QPSK and QAM systems, which compensates for phase errors in the I and Q components of the QPSK or QAM signals to minimize carry over of such phase errors in analog up and down conversions of such signals. In particular, the invention relates to a relatively simple circuit, which compensates for channel phase errors by providing a direct correction of one of the channels based on the measured correlation between the I and Q components, which should ideally be 0. As such, cross talk between I-Q channels is minimized, which improves the signal-to-noise ratio of transmitted and received QPSK or QAM signals.

Abstract: A circuit for demodulating two-dimensional data symbols transmitted by carrier-based data transmission. The circuit has a tuner and a quadrature demodulator. The tuner has a first intermediate frequency stage for converting a carrier frequency of an input signal containing the two-dimensional data symbols to a first intermediate frequency f1, a surface wave filter, and a second intermediate frequency stage connected downstream of the surface wave filter for converting the carrier frequency of the input signal to a second intermediate frequency f2. The second intermediate frequency f2 is lower than the first intermediate frequency f1. The demodulator converts the input signal at the second carrier intermediate frequency f2 to a baseband and splits it into in-phase and quadrature components.

Abstract: The present invention relates to an arrangement (1) and a method in a receiver in a multi-mode mobile radio (m), wherein the intention is to design the receiver so that it uses the same hardware to process several different channel bandwidths corresponding to the different networks used by the radio (m). This is done by changing a sampling frequency (fs) which controls a digital filter unit (25) situated in the digital part of the receiver. The changing of the sampling frequency (fs) results in that the bandwidth of the digital filter unit (25) is scaled accordingly, wherein the desired channel bandwidth at baseband of the radio network (GSM1900, AMPS) to be used by the radio (m) is selected in the digital filter unit (25). As a complement, the digital filter unit (25) can be implemented with a programmable function, where a change of parameters and/or filter structure inside the digital filter unit (25) can be used to adjust the filter bandwidth.

Abstract: A differential ring oscillator is provided with three differential amplifiers and provides three-phase output signals which can be used for synchronous detection of a received multi-phase modulated signal in a multi-phase receiver, wherein the phase of the local oscillator signals may be in other-than-quadrature relation. Two of the phase outputs of the local oscillator can be combined to provide a signal that is in quadrature with the remaining output. The oscillator is preferably controlled in coarse frequency control steps and using a fine voltage control signal responsive to a phase-locked loop to reduce frequency modulation of the oscillator signal arising out of leakage signals.

Abstract: The invention presents an apparatus capable of demodulating stably if there are time-course changes in the constituent parts in a demodulator of digital modulated signal. This demodulator comprises an operator for setting the oscillation frequency of a local oscillator 2, and within a passing frequency band of a band pass filter BPF 3, the operator controls the local oscillator 2 so that the frequency of the output signal of a first mixer 1 may settle within a control band in a controllable frequency band of an AFC feedback loop composed of an orthogonal detector 4, a carrier regenerator 9, a frequency error detector 10, a frequency controller 11, a signal selector 12, a D/A converter 13, and a VCO 14, and a local carrier is issued from the local oscillator 2 to the first mixer 1.

Abstract: In a transmission side, a k-bit parallel signal is divided into n signals, which are respectively encoded and then phase-shifted so as to causing a mutual phase difference of &pgr;/2n. Spectrum spreading is performed on the phase-shifted encoded signals which are combined together to produce a transmission digital signal. In a receiving side, reverse spreading is performed on a receiving signal to produce reverse-spread signals, which are given the phase difference to cancel the phase shift of the transmission side, and then decoded. Thus, the original k-bit parallel signal is reproduced in the receiving side.

Abstract: Incoming signals in a receiver for Direct Sequence Code Division Multiple Access systems are despread using Offset-QPSK spreading as the transmitting spreading format combined with arbitrary data modulation formats, such as BPSK and QPSK. The receiver has a pseudonoise (PN) generator for generating a unique PN sequence signal. The PN sequence signal is divided into a real and an imaginary component. The complex input signal is divided into inphase and quadrature components. The inphase and the quadrature components of the input signal are downsampled to provide either two complex samples per chip period or one complex sample per chip period. In the latter case, the downsampling instants are delayed by a quarter of a chip period. Each downsampled complex signal is correlated with the corresponding segment of the complex PN sequence signal of the receiver.

Abstract: The invention provides a single chip implementation of a digital receiver for multicarrier signals that are transmitted by orthogonal frequency division multiplexing. Improved channel estimation and correction circuitry are provided. The receiver has highly accurate sampling rate control and frequency control circuitry. BCH decoding of tps data carriers is achieved with minimal resources with an arrangement that includes a small Galois field multiplier. An improved FFT window synchronization circuit is coupled to the resampling circuit for locating the boundary of the guard interval transmitted with the active frame of the signal. A real-time pipelined FFT processor is operationally associated with the FFT window synchronization circuit and operates with reduced memory requirements.

Abstract: The invention relates to a threshold extension block phase estimator (TEBPE) which estimates phase in the presence of noise. Threshold and sector slips are controlled by an iterative calculation. This can be of crucial advantage in coded systems. Another attribute of the TEBPE is it can be configured as a hybrid feedback loop incorporating characteristics of both the BPE and the PLL. This gives a high degree of flexibility with very fast acquisition times at high signal-to-noise ratio (SNR), and improved threshold performance at low SNR.

Abstract: A method for weighting orthogonal frequency division multiplexed soft symbols is provided, including the steps of receiving a plurality of sub-carriers modulated by digital information and filtering the sub-carriers to produce complex soft decision outputs. The magnitudes of the soft decision outputs are used to creating a first sequence of data. The differences between successive samples in the first sequence are used to create a second sequence of data. The first and second sequences are filtered and compensated for differences in effective group delay of the first and second sequences to produce third and fourth sequences. Then these third and fourth sequences are used to determine a plurality of weights and the weights are applied to the complex soft decision outputs. A receiver which incorporates the method is also disclosed.

Abstract: A device for transmitting digital data includes a selector which selects certain digital data couples which follow each other, a mapper, which, in accordance with a set of rules, maps each digital data couple selected to an amplitude couple, and a transmitter which transmits a signal in quadrature, the two components of such signal being modulated by the first and second amplitudes, respectively, of the amplitude couple. The set of mapping rules includes a rule that states that when the estimated probability that two amplitude couples will be confused, after the transmission has occurred, is greater than a certain value, then the digital data couples corresponding to the two amplitude couples have first or second digital data items whose value is the same.

Abstract: A transmitter which includes a quadrature phase shift keying (QPSK) modulator, and a receiver which includes a pilot correlation filter (PCF), a data matching filter (DMF), a timing recovery mechanism, a sampler, and a QPSK demodulator are provided in a wireless communication system. The transmitter transmits a frame of data symbols and pilot symbols to a receiver in a wireless system. The pilot symbols are inserted in the frame at known time intervals. The QPSK modulator modulates the frame of data and pilot symbols. As the receiver receives the frame of data and pilot symbols from the transmitter, the PCF recovers the pilot symbols sent by the transmitter, whereas the timing recovery mechanism tracks the timing of the pilot symbols in the frame. The DMF enhances the multipath response of the frame of data and pilot symbols at the known time intervals of the pilot symbols, and outputs a plurality of enhanced peaks.