Abstract: A data receiver for transmitting data by changing the data into transmitted frames and by phase-modulating the data in a digital manner has a demodulation circuit for demodulating a phase-modulated signal by sync detection, a conversion circuit for converting the phase of an output from the demodulation circuit into a correct phase, and a sync detection circuit for detecting sync data of the transmitted frames from an output from the conversion circuit and for controlling the conversion circuit on the basis of a sync data undetected condition.

Abstract: An in-phase component and a quadrature component of a digitized input DQPSK modulated signal are provided from interpolation filters, respectively. An instantaneous amplitude and an instantaneous phase of the input signal for each symbol clock are detected from the in-phase and quadrature components and are fed to adders. At the same time, that one of symbols "0, 0," "0, 1," "1, 0" and "1, 1" which corresponds to the instantaneous phase is detected by a symbol detector. An ideal reference signal generating part generates an ideal amplitude component and an ideal phase component corresponding to the detected symbol and provides them to a parameter calculating part. In an I-Q origin offset detecting part, an I-Q origin offset is calculated on the basis of the relationship between a triangle formed by the current detected vector corresponding to an ideal symbol and a vector detected one symbol clock before and a triangle formed by the said two vectors.

Abstract: It is an object to enlarge the phase range in which a phase error can be determined. An operating block (1) calculates a power of carriers from data DI and DQ. An ideal symbol estimating block (2a) outputs a plurality of ideal symbols which correspond to the power of carriers outputted from the operating block (1). A phase error tan(.theta.) calculating block (2b) calculates prediction phase errors between the ideal symbols and the symbol given by the data DI and DQ. A phase error determining block (3) determines a phase error from among the prediction phase errors outputted from the phase error tan(.theta.) calculating block and outputs the phase error.

Abstract: A digital audio broadcasting system includes an RF transmitter and a corresponding RF receiver. In the RF transmitter, a digitally compressed audio signal is encoded into a symbol stream that is first rotated using a frequency of 150,000 hertz (hz) before transmission to the RF receiver.

Abstract: A timing recovery process for digital receivers employing decision-feedback equalization (DFE) or delayed decision-feedback sequence estimation (DDFSE) can be executed prior to equalization, minimizes training complexity, and provides fast equalizer start-up for transmissions of short packets. The optimum symbol timing and burst timing is determined by (i) calculating a signal-to-intersymbol interference-plus-noise ratio (SINR) index by estimating the channel impulse response and the noise power, and (ii) varying the symbol timing and the burst timing to maximize the calculated SINR index. The timing recovery process particularly improves performance of a digital receiver utilizing (a) decision-feedback equalizer structures in which the delay spread is large compared to the span of the feedforward filter, and (b) equalizer structures based on delayed decision-feedback sequence estimation in which the delay spread is large compared to the memory of the Viterbi sequence estimator section.

Abstract: The in-phase channel 28 of a complex demodulated resonator data output signal 12 should contain all of the sensed information, and the quadrature-phase channel 32 should contain none of it. This will not happen if the phase of the reference signal 14 is incorrect. The phase may be adjusted by first filtering each demodulated channel with a respective low-pass dc-blocked filter 34, 38 which passes only the frequencies of the sensed information. If the sensed information gets through on both channels, then there will be a non-zero cross-correlation between the channels. This cross-correlation can be servoed to a minimum by use of a feedback signal 22. Doing so will cause all of the sensed information to be in one channel 28, and diagnostic information to be in the other channel 32.

Abstract: A low power zero-IF selective call receiver has a local oscillator (106) that generates an injection signal for a first mixer (104) and a pair of quadrature phase related injection signals (122, 124) for a pair of second mixers (112, 114). The first mixer converts the received carrier signal (102) to an intermediate signal (108). A digital phase shifter/divider (116) coupled to the local oscillator (106) generates the pair of quadrature phase related injection signals (122, 124) at the frequency of the intermediate signal (108) which also equals the frequency of the local oscillator (106) divided by an integer greater then 1. The pair of second mixers (112, 114) coupled to the digital phase shifter/divider (116) converts the in and quadrature phase components (122, 124) of the intermediate signal (108) to respective in and quadrature phase baseband signals (126, 128).

Abstract: The invention relates to an 8-PSK differential coder for trellis-coded modulation and to a corresponding pragmatic decoder, enabling 90.degree., 180.degree., and 270.degree. phase ambiguities to be lifted. The invention applies in particular to transmitting images at high rate by radio link.

Abstract: The method makes it possible digitally to evaluate the phase of any carrier that has been subjected to rPSK modulation subsequent to clock recovery, sampling, and digitizing the in-phase and quadrature components of the samples, by processing that is performed in polar coordinates and that comprises reducing the range over which the phase of each sample is defined to a range of +.pi./r to -.pi./r and then seeking the center of gravity over 2.sup.N successive samples (N being an integer) by performing successive averaging calculations, each time on two values, in application of an N-stage tree structure. Each average of two values is associated with an index indicative of the degree of reliability of the average, and those averages which are associated with a small reliability index are ignored while calculating subsequent averages in the tree structure.

Abstract: Delayed symbols (204), including a current symbol (205), are compared by a comparator (206) with at least one predetermined pattern when the current symbol is equivalent to one of a set of predetermined values. Alternatively, a sign of the current symbol is compared with signs of a previous and a subsequent symbol when the current symbol is equivalent to one of the set of predetermined values. When the current symbol is equivalent to one of the set of predetermined values and when either the delayed symbols are equivalent to one of the at least one predetermined pattern or the sign of the current symbol matches the signs of the previous and subsequent symbols, a symbol corrector (208) applies a predetermined function to the current symbol to produce a received symbol (210).

Abstract: The number of oscillators required to construct a digital radiocommunication terminal can be reduced and a circuit used for the digital radiocommunication terminal can be reduced in size. For this purpose, the digital radiocommunication terminal for effecting information transmission using an N (integer)-phase-shift-keyed signal (identification symbol number N=4 upon .pi./4 shifted QPSK modulation), is constructed such that an oscillation frequency generated from a reference oscillator employed with a frequency synthesizer is selected to have a common multiple of a second intermediate frequency and an identification symbol phase N and is supplied to a detector for outputting received data therefrom.

Abstract: A locally coherent Quadrature Phase Shift Keying (QPSK) detector that uses a normalized fourth power weighting technique to generate an ambiguous local phase reference of a current symbol. A phase adjusted previous symbol reference is used to resolve the ambiguity using differentially coded data and yield current soft symbol information.

Abstract: A radio-frequency broadcasting system and method for simultaneously broadcasting analog and digital signals in a standard AM broadcasting channel wherein the system includes: a transmitter for providing, and broadcasting, a composite signal containing an adaptively-modulated phase-shift-keyed digital signal with analog programming material modulated thereon; and a receiver for detecting the composite signal, extracting the analog audio signal and digital audio, or data, therefrom, and playing back the received audio programming. The adaptively-modulated phase-shift-keyed digital signal is responsive to the transmitted signal, dynamically increasing the digital data transmission rate as the transmitted signal power increases. Symbol states are generally arranged around concentric arcs, and adjacent symbol states are generally equidistant.

Abstract: In a digital data demodulating apparatus, total number of low-pass filters is reduced by supplying variable sampling clock signals to A/D converters coupled to the low-pass filters. The digital data demodulating apparatus for receiving/demodulating a transmission signal that is modulated by digital data in a predetermined modulation manner, includes: a detecting unit for detecting the transmission signal; a low-frequency component passing unit for causing a low-frequency component of the transmission signal detected by the detecting unit to selectively pass therethrough; an analog-to-digital (A/D) converting unit for A/D-converting the output from the low-frequency component passing unit into a digital transmission signal; a demodulating unit for demodulating the digital transmission signal from the A/D converting unit; and a switching unit for switching a frequency of a sampling clock produced from the A/D converting unit in response to an external switching instruction.

Abstract: To receive a response signal from a radio card, a card reader transmits a carrier (not modulated) to the radio card. In the radio card, a phase modulator phase-modulates the a sub-carrier with a response signal, thereby generating a PSK signal, and a phase modulator phase-modulates the carrier with the PSK signal, producing a PSK-PSK signal. The PSK-PSK signal is supplied to an antenna via a signal-extracting device. The antenna sends the PSK-PSK signal toward the card reader. In the card reader, a distributor distributes the PSK-PSK signal to a synchronous detector and an orthogonal detector. The detectors performs synchronous detection by using carriers which differ in phase by 90.degree.. Low-pass filters extract sub-carrier components from the outputs of the detectors. The sub-carrier components are delayed and detected by delay detectors and added together by an adder.

Abstract: The optimum decoding of component codes in Block Coded Modulation (BCM) schemes requires the use of the Log-Likelihood Ratio (LLR) as the signal metric. The essence of the invention is a means of accurately approximating the computation of the LLR in a way which is simple to implement directly. The invention, the Log-Likelihood Ratio Planar Approximation (LLRPA), mathematically consists solely of planar equations with fixed point arithmetic that provides both an accurate estimate of the LLR and is easily realized in electronic hardware.

Abstract: For demodulating a phase-modulated signal having 2M states of a carrier (M being an integer), the signal is converted into two baseband signals in quadrature. For that, they are multiplied by a signal delivered by a local oscillator at a transposed carrier frequency. Then the baseband signals are digitized by sampling at the clock frequency of the modulating signal. The clock of the signal is recovered by adjusting the phase of a local clock, stabilized at a bit frequency. For that, a minimum value of the intersymbol interference is searched. The signal clock is recovered before the carrier is recovered. Devices for implementing the method are also disclosed.

Abstract: A television receiver includes a synchronous demodulator including a bi-phase stable PLL for controlling sampling of the received signal to produce data. A phase inverter reverses the phase of the data in response to a control signal. Data segment sync characters are recovered with a sync correlation filter that also yields a sign bit indicating polarity. If the sign bit is wrong for a predetermined number of data segment sync characters, a control signal is produced to operate the phase inverter.

Abstract: A received signal sample sequence is inversely modulated by a symbol sequence forming the trellis state at the immediately preceding time, by which a reference signal is generated. This reference signal and the inner product of the received signal sample at the current time and a candidate symbol phase are used as a branch metric to make a sequence estimation by the Viterbi algorithm.

Abstract: A phase modulated signal demodulation system which is not affected by noise and distortion of an input signal. The system includes a carrier reproduction PLL circuit for generating a reproduction reference clock having a frequency which is N times of a carrier frequency which is synchronized with an N-phase phase modulated input signal, and a clock generation circuit for dividing the reproduction reference clock by 1/N and for generating N clocks, each of which has a different phase offset by 360.degree./N. The system further includes a phase detector which detects a phase of the N-phase phase modulated signal by using the N clocks together with the input N-phase phase modulated signal; and an operating circuit which detects a data edge of the input signal and the reproduction reference clock.

Abstract: A method and an apparatus is provided for decoding a communicated radio frequency signal containing a sequence of phase values. The method includes the steps of amplitude limiting the communicated signal and maximum likelihood decoding the amplitude limited signal.

Abstract: In a radio receiver for receiving vestigial sideband (VSB) signals including symbol codes descriptive of digital signals, HDTV signals being exemplary of such VSB signals, a tuner provides for selecting one of channels at different locations in a frequency band used for transmitting such VSB signals. The tuner also includes mixers for performing plural conversion of the selected channel to a final intermediate-frequency (IF) signal, which is digitized by an analog-to-digital converter. The pilot carrier is detected by a narrowband quadrature-phase synchronous detector operative in the digital regime, for controlling the frequency and phase of the local oscillations applied to one of the mixers in the tuner so that the pilot carrier component of the final IF signal is locked to a submultiple of symbol frequency. The fullband final IF signal is synchronously detected by an in-phase synchronous detector to detect symbol codes.

Abstract: A synchronous detector has first and second mixer circuits and a voltage controlled oscillator. The voltage controlled oscillator provides a local oscillator signal directly to the second mixer circuit and indirectly to the first mixer circuit through a phase transformer. The output of the first and second mixer circuits are combined in combiner circuitry to produce a jitter cancelled output signal. The jitter cancelled output signal is filtered in a loop filter and applied to the voltage controlled oscillator to control the frequency and phase of the local oscillator signal. The combiner circuitry includes a summer and a jitter cancellation filter. The jitter cancellation filter is preferably a high pass filter matched to spectrum of the signal detected. The output of the first mixer circuit is passed through the high pass filter into one input of the summer while the output of the second mixer circuit is passed to the second input of the summer. The output of the summer is passed to the loop filter.

Abstract: An in-phase component and a quadrature component of a digitized input DQPSK modulated signal are provided from interpolation filters, respectively. An instantaneous amplitude and an instantaneous phase of the input signal for each symbol clock are detected from the in-phase and quadrature components and are fed to adders. At the same time, that one of symbols "0, 0," "0, 1," "1, 0" and "1, 1" which corresponds to the instantaneous phase is detected by a symbol detector. An ideal reference signal generating part generates an ideal amplitude component and an ideal phase component corresponding to the detected symbol and provides them to a parameter calculating part. In an I-Q origin offset detecting part, an I-Q origin offset is calculated on the basis of the relationship between a triangle formed by the current detected vector corresponding to an ideal symbol and a vector detected one symbol clock before and a triangle formed by the said two vectors.

Abstract: An object of the present invention is to provide a soft decision circuit by which the reception accuracy can be improved. Each of first and second receivers of the soft decision circuit includes a phase amount detector for detecting a phase amount of a receive signal, an I table and a Q table for converting the phase amount into orthogonal I/Q signals, an A/D converter for converting a receive level signal of the receive signal into a digital value, a log linear table for converting an output of the A/D converter into a squared value of a true value, and first and second multipliers for multiplying outputs of the I table and the Q table with the output of the log linear table to weight the outputs of the I table and the Q table.

Abstract: An automatic frequency control apparatus used in an MPSK communication system detects a frequency offset between a carrier and a local oscillation signal for adjustment of a local oscillation frequency. A phase difference detector generates a first phase difference detection signal having, as a phase value, a difference between the phases of various samples of the sampled signal. A phase altering unit generates a second phase difference detection signal having a phase value different from that of the first phase difference detection signal. A frequency offset signal generator estimates transmission phase information by using the phase value of the second phase difference detection signal and reference phase signals used for MPSK modulation, thereby generating a frequency offset signal which is determined by the transmission phase signal and the second phase difference detection signal.

Abstract: A clock synchronization circuit for use in a baseband demodulator of communication equipment of a digital modulation type, in which detection data is subjected to an interpolating operation with respect to at least one point between adjacent two sample values of the detection data, subjected to a conversion into one-bit data indicative of a positive or negative value, and then passed through a one-bit-input band pass filter to perform phase error detection. Consequently, clock synchronization accuracy is improved while preventing a sampling rate and circuit scale from being made large.

Abstract: A digitized quasi-phase synchronous phase detecting signal of the PSK signal is used to generate digitized quasi-synchronous phase detecting signal phase-corrected by phase correcting data and a first phase display data indicating the phase of the carrier of the PSK signal is generated from the phase-corrected digitized quasi-synchronous phase detecting signal. Alternatively, the digitized quasi-synchronous phase detecting signal of the PSK signal is used to generate second phase display data indicating the phase of the carrier of the PSK signal and third phase-corrected phase display data is generated from the second phase display data. The first or third phase display data is used to generate fourth phase display data indicating the phase assigned to the code of the PSK signal and a decoded digitized code is generated from the fourth phase display data.

Abstract: A technique of demodulating a .pi./4-DQPSK composite carrier waveform using a non-coherent discriminator based receiver is presented. In particular, a means of recovering .pi./4-DQPSK modulated data symbols using a dual output discriminator in conjunction with a dual binary amplitude detection process in a discriminator based receiver is discussed. Means which improve the bit error rate of the receiver over the prior art are presented. Additionally, an amplitude detection means which readily provides synchronization of the detected data symbols is discussed which was not heretofore possible with the 4-level slicer of the prior art.

Abstract: A numerical value (Y-X).multidot.0.5 indicative of a phase angle .theta..sub.1 in the first quadrant is calculated on the assumption that a quadrant of an input vector signal (x+jy) is judged and the signal is rotated into the first quadrant by a rotational vector signal (a+jb) and the phase angle of 0 to .pi. is expressed by 0 to +2 and the phase angle of .pi. to 2.pi. is expressed by -2 to 0 as a prerequisite. Further, a numerical value c indicative of an offset phase angle .theta..sub.2 to return the vector signal into the original signal and the phase number indicative of each of the (N) divided phase regions of the phase plane is directly obtained as bit data.

Abstract: In a circuit arrangement for correcting phase errors of P-channel and Q-channel baseband signals of a QPSK signal, input registers are provided corresponding respectively to possible bit patterns which the unique words of the P-channel and Q-channel baseband signals may assume. Each input register stores 2N bits of incoming unique words of the P- and Q-channel signals. Reference registers corresponding to the possible bit patterns are provided for individually storing 2N bits of a corresponding one of the possible bit patterns. Mismatches between the bits stored in each input register and the corresponding reference register are detected and compared with thresholds to produce a phase error correcting signal. In response, the connecting paths of the P- and Q-channel baseband signals to output terminals are controlled and bit reversals are effected on the P- and Q-channel baseband signals.

Abstract: A QPSK modulated wave is inputted to an in-phase detector and an orthogonal detector. The detected components are converted to substantially a base band, and each component is digital-converted by A/D converters. Each digital component is spectrum-shaped by digital LPFs. The outputs of digital LPFs are inputted to a complex multiplier and calculated by use of first and second reproduction carriers and expressed as first and second calculation outputs, and inputted to a phase detector. The phase detector obtains phase difference data between the phase expressed by the first and second calculation outputs and a predetermined phase and quadrant data of the phase. The phase difference data is used for a PLL. The phase difference data is is inputted to a frequency error detection circuit detecting a frequency error. The frequency error output is smoothed by a filter of an AFC loop, and used as a control signal controlling the oscillation frequency of the local oscillation unit.

Abstract: In a demodulator, a delay detection means receives a .pi./4-shift QPSK signal and performs delay detection of a signal at an interval of symbols. An averaging circuit respectively averages two channel quadrature signal components of a signal. A preamble detection means detects a preamble having a specific pattern in which a phase shift of .pi./4 of the phase of a received symbol from the immediately preceding symbol and a phase shift of -3.pi./4 of a phase of a next symbol from the immediately preceding symbol are alternately repeated on a phase plane of the two channel quadrature signal components. A phase angle calculating means calculates the phase angle of an output signal from the averaging circuit. A frequency offset estimating circuit calculates a carrier frequency offset. A voltage-controlled oscillator has an output oscillation frequency variably controlled by an output signal from the frequency offset estimating circuit.

Abstract: A device for demodulating a signal modulated on two axes in phase quadrature using a .pi./4-QPSK type digital modulation technique employing alternately two phase-shifted constellations. The device includes: a voltage-controlled oscillator (28) supplying a local signal substantially at the carrier frequency; a demodulator means using the local signal and supplying, after filtering (30, 31), the phase component P and quadrature component Q of the demodulated received signal; a phase controller (32) producing a control signal (39) for controlling the oscillator (28) and including a phase estimator (33) producing a phase estimation signal E (35) involved in control of the oscillator (28), the phase estimation signal being derived from the phase component P and quadrature component Q of the demodulated received signal.

Abstract: A method and apparatus for trellis coding of input data as phase point data for M-ary modulation and transmission upon a communication channel and a method and apparatus for decoding same. The trellis encoding is accomplished by an input encoder for receiving and encoding according to a first encoding format a set of input user data bits to provide a set of symbols; a precoder for encoding according to a second encoding format a first symbol of the set symbols to provide a second symbol; an output encoder for encoding the second symbol according to a third encoding format to provide a third symbol wherein the third encoding format has an inverse transfer function relationship with the second encoding format, encoding the second symbol according to a fourth encoding format to provide a fourth symbol; and wherein remaining symbols of the set of symbols and the third and fourth symbols collectively represent phase point data.

Abstract: A transmitting apparatus based on phase modulation including a data encoding circuit (100), a phase locus control circuit (200) and a modulator (300). The data encoding circuit (100) divides input data to be transmitted into a predetermined number of bits, and sequentially outputs them as segmented data. The phase locus control circuit (200) outputs a phase locus control signal representing each of the segmented data by three values of a positive direction, a negative direction and a non-rotation state of the phase rotation. The modulator (300) changes the phase of a transmission signal in response to the phase locus control signal. Using the phase rotation direction information of the three values makes it possible to reduce transmission bits, to increase transmission speed and transmission capacity.

Abstract: A method and apparatus for normalizing the I and Q components of a complex signal is provided which includes an iterative determination of the multiplier constant required for normalization. The I and Q components are squared and added together to create a digital word A constrained between certain limits. An iterative approach is implemented to arrive at a multiplier constant K which is equal to ##EQU1## without resorting to the use of multipliers. The constant K is then used to normalize the I and Q components.