Abstract: The invention discloses a novel equalization system for reducing the deleterious effects of crosstalk on signals received at a modem, with particular regard to QAM signals transmitted over copper twisted pairs. The equalization system employs the common combination of a linear equalizer followed by a decision-feedback equalizer (DFE). However, instead of aiming for perfect equalization of channel distortion, the overall frequency response of the channel plus the linear equalizer is skewed such that higher frequencies are attenuated relative to lower ones. More generally, the spectral regions where crosstalk is strongest are attenuated, which reduces the crosstalk noise present at the input to the DFE at the expense of introducing inter-symbol interference (ISI). Fortunately, most DFEs are capable of handling the added ISI, leading to data decisions that are relatively unaffected by crosstalk noise.

Abstract: A method for simple synchronization of a receiving device to a transmitting device for a transmission of a dispersed-energy QPSK signal. The signal is composed at the transmitting end of two mixed products, the mixed product of an I signal and a transmitted carrier and the mixed product of a Q signal and the transmitted carrier shifted through 90°. In order to synchronize the received carrier to the transmitted carrier without any problems, it is proposed that an amplitude of an SQ signal be measured at the time of the zero crossing of the rising flank of an SI signal, and that an amplitude of the SI signal be measured at the time of the zero crossing of the falling flank of the SQ signal. The measured values are a measure of a discrepancy from synchronicity between the received carrier and the transmitted carrier, and that the frequency of the received carrier be varied until the amplitude of an error signal obtained from this measurement is zero.

Abstract: A digitized quadrature detected output of a sampling rate R (=16Rs, where Rs is the symbol rate) from a quadrature detector is subjected to FFT processing and the frequency of the peak power spectrum of the FFT output is detected. Then, a frequency error &OHgr;01 between the frequency of the peak power spectrum and a standardized value is calculated and the frequency error &OHgr;01 of the detected output is corrected. The corrected output is decimated by a filter to a signal of a sampling rate 4Rs, which is input into an estimate part, wherein a clock phase is calculated which minimizes variance of the amplitude of the input sample data and a frequency error &OHgr;02 is computed from a deviation of the signal point of the input sample data from a standardized angle value of the signal.

Abstract: A method of estimating the DC offset and the phase offset for a radio receiver operable in a digital passband transmission system, the method comprising; sampling a received radio signal at the symbol rate of the transmission system to produce a set of data samples, processing each data sample in the set in order to determine a received signal point in signal space for each data sample, determining an associated constellation point in signal space for each received signal point, calculating the DC offset and the phase offset which minimises, for the set of data samples, the sum of the square of the random errors between each received signal point and its associated constellation point.

Abstract: At the transmitter side, carrier waves are modulated according to an input signal for producing relevant signal points in a signal space diagram. The input signal is divided into, two, first and second, data streams. The signal points are divided into signal point groups to which data of the first data stream are assigned. Also, data of the second data stream are assigned to the signal points of each signal point group. A difference in the transmission error rate between first and second data streams is developed by shifting the signal points to other positions in the space diagram. At the receiver side, the first and/or second data streams can be reconstructed from a received signal. In TV broadcast service, a TV signal is divided by a transmitter into, low and high, frequency band components which are designated as a first and a second data stream respectively.

Abstract: In a digital frequency phase locked loop (FPLL) for a grand alliance (GA) HDTV receiver using a vestigial sideband (VSB) modulation transmission system, the digital FPLL for a VSB transmission system having a VCO and a plurality of NTSC carrier eliminating filters for eliminating interference of NTSC adjacent channels includes a filter for eliminating high-frequency components by converting a digital signal output from one of the plurality of NTSC carrier eliminating filters, a delay for delaying the high-frequency-component-eliminated signal by a predetermined width so that its frequency-versus-phase characteristics are changed linearly, symbol inverter for inverting the symbol of the digital signal output from another of the plurality of NTSC-carrier eliminating filters, a switch for selectively outputting the symbol-inverted signal and the digital signal output from another filter, a second filter for limiting the selectively output signal to a predetermined frequency band, a digital-to-analog (D/A) conver

Abstract: An absolute phasing circuit having a simplified phase rotating means constituting a remapper. The phase rotation angle of a receiving phase for the signal point arrangement on the transmitting side is detected, and a phase rotation signal RT (3) based on the detected phase rotation angle is outputted from a frame synchronization circuit (2). Phases of baseband demodulated signals I and Q through a demodulator circuit (1) are rotated by 45° through a ROM (3) constituting the remapper. A logic conversion circuit (4), receiving the baseband demodulated signals I and Q through the demodulator circuit (1) and phase rotated baseband demodulated signals i and q from the ROM (3), performs inversion of code and exchange of the baseband demodulated signals selectively and delivers a baseband demodulated signal matched with the signal point arrangement on the transmitting side.

Abstract: In order to differentially detect a multiple-phase shift keying (MPSK) signal, a predetermined number of phase signals are stored at successive symbol time points. Next, a plurality of phase differences between the phase signals stored in the above are calculated. Subsequently, a symbol value of the MPSK signal is determined or estimated at a current symbol time point using the calculated phase differences and using symbol values already determined at a plurality of preceding symbol time points.

Abstract: An improved digital decision directed phase locked loop (DD-PLL) for use with short block codes using phase shifting keying (PSK) modulation. The improvement involves a conventional digital phase lock loop which is modified to base its loop corrections on the results obtained by decoding the short block code rather than on a symbol by symbol basis as is customary in conventional DD-PLLs. The improved method of loop corrections involves retaining the symbol data pending the decoder's decision, derotating the retained data in accordance with the decoded result, and integrating the derotated data to form a composite estimator upon which to base the loop correction. In its preferred embodiment, the invention uses an (8, 4) biorthogonal code with quatenary PSK.

Abstract: A direct-conversion receiver includes a local oscillator for generating a local oscillator signal, a converter circuit for converting a received radio signal into a pair of a baseband I signal and a baseband Q signal in response to the local oscillator signal, a demodulator for demodulating the pair of the baseband I signal and the baseband Q signal into a demodulation-resultant signal which is neither an I signal nor a Q signal, a detector circuit for detecting a difference between a frequency of the local oscillator signal and a frequency of a carrier of the received radio signal, a clock signal generator for generating a first clock signal providing a timing which corresponds to a center of a symbol period, a signal delay device for delaying the first clock signal to provide a second clock signal, and a symbol deciding circuit for deciding a logic state of the demodulation-resultant signal at a timing determined by the second clock signal.

Abstract: According to the invention, information from a differential decoder (1) receiving the MSB of the in-phase component and the MSB of the quadrature component is used to derotate the LSBs of the in-phase component and the LSBs of the quadrature component into the first quadrant with a rotator (2). Then only one quadrant is demapped by a single quadrant demapper (3). Thereby, the look-up table necessary for the demapping circuit is reduced considerably. The output signal of the QAM de-mapping circuit is build from the demapped LSBs of the in-phase and quadrature components output by the single quadrant demapper (3) and the outputs of the differential decoder (1).

Abstract: An improvement to a Reed Solomon (RS) coding scheme wherein the RS encoder and decoder is initiated based upon counting a number of timing, baud, or byte cycles from a known time stamp. The time stamp can be for example, a Tomlinson coefficient exchange frame whereby at the end of a Tomlinson coefficient exchange frame, a counter in both transmitter and receiver is actuated to begin counting a number of baud cycles. Alternatively, the counter may be initiated upon the receipt of a particular byte. Once the appropriate number of baud cycles or bytes have elapsed, the RS encoder and decoder will begin operation, thus ensuring that both RS encoding and decoding occur at the proper time, without the use of any additional framing bits.

Abstract: A circuit for demodulating a signal having a temporal mixture of different modulation schemes applied thereto includes a synchronization-word-detection unit which detects synchronization words included in the signal, and generates first and second position signals, based on the detected synchronization words, indicative of respective predetermined positions in the signal, a first selection unit which selects the first position signals during a first period, and selects the first position signals and the second position signals during a second period, and a carrier-reproduction unit which carries out frequency capturing during the first period by using the first position signals selected by the first selection unit, and carries out phase capturing during the second period by using the first position signals and the second position signals selected by the first selection unit, thereby reproducing a carrier.

Abstract: To control the oscillation frequency of a local oscillator, a digital broadcast receiver demodulates a phase-reference symbol contained in an orthogonal frequency-division multiplexed broadcast signal to obtain an array of complex values, selects several sets of values from the array, multiplies each selected value by the complex conjugate of a value offset by N positions in the array (where N is a fixed integer that may be equal to zero), averages the results in each set, takes differences between the average values, or between sums of these average values, thereby obtains two difference values, and calculates a frequency offset from the difference values. Each set of values is taken from positions at which the known reference-symbol values satisfy certain conditions in relation to the known values at adjacent positions.

Abstract: The efficient quadrature amplitude modulator of the present invention allows from 6 to 8 independent compressed channels to occupy a 6 MHz bandwidth while reducing processing power by 33 percent for 8 levels of modulation offered by 64-QAM and by 25 percent for 16 levels of modulation offered by 256-QAM. The modulator achieves this efficiency using an improved digital filter architecture combining the modulation and filtering with post filtering carrier combination. The QAM modulator presented is implemented with a reduction in the total number of binary parallel multipliers. To increase operational throughput, the speed of operation increases with the use of LUTs (look-up tables) storing precomputed filter weighting coefficients. The reduction in multipliers is also achieved by using post filtering carrier combination which similarly reduces the number of MAC operations performed during filtering.

Abstract: Circuits embodying the invention include a baseband amplifier to whose input is applied a baseband input signal (I or Q). The gain of the amplifier is controlled by sampling the output of the amplifier and supplying the sampled signals to a dynamic histogram control (DHC) circuit which includes a memory circuit for storing a histogram which contains a statistically expected response of the sampled baseband signal. The DHC circuit includes circuitry for comparing the sampled signals to the stored histogram for producing a gain control signal which is then used to control the gain of the amplifier. In some embodiments, the DHC circuit may also include circuitry for producing an offset adjustment signal to control the direct current (dc) level of the signal being sampled and hence its symmetry.

Abstract: A method and an apparatus for demodulating trellis coded direct sequence spread spectrum communication signals are provided. A transmitted QPSK signal is received. Binary phase-shift keyed (BPSK) despreading is performed on the QPSK signal. The BPSK despreading includes correlating the in-phase and the quadrature components of the received QPSK signal with independent PN sequences for the each of the in-phase and the quadrature components. The despread signal is then demultiplexed, and the pilot signal and the BPSK data signal are recovered. The recovered pilot signal is used to provide a channel phase estimate and a channel magnitude estimate. The recovered BPSK data signal is demodulated, despread, and decoded. The despreading and decoding includes determining a number of cross-correlation terms of the received signal using a number of transmitted biorthogonal Walsh sequences. The cross-correlation terms are used as the branch metrics in a maximum likelihood decoding algorithm.

Abstract: A method of demodulating voice or data and control information in systems that support multiple modulation schemes modulates voice or data using a first linear modulation scheme, such as 16QAM modulation scheme, and modulates control information using a second linear modulation scheme, for example, QPSK modulation scheme, that has the same symbol rate as that of the first modulation scheme. The first linear modulation scheme has a higher modulation level than the second linear modulation scheme. Information modulated using the second linear modulation scheme, which uses a reduced signal set of the first linear modulation scheme, are demodulated using the same demodulator that is used for demodulating information modulated using the first linear modulation scheme. Also, in-band signalling information within a traffic channel, such as stealing flags, are modulated using the second modulation scheme.

Abstract: A method of carrier tracking in a digital receiver includes adjusting the phase of an equalized signal by a phase correction to compensate for a carrier frequency offset. For a small carrier frequency offset the phase correction is based on a first estimate of phase error and phase velocity of the equalized signal. For a large carrier frequency offset the first phase velocity estimate is controlled by a second phase velocity estimate based on rotation of the data constellation.

Abstract: A receiving apparatus for receiving digital broadcasting of a first frequency band and frequency band has a local oscillation circuit for generating a first local oscillation signal, and a frequency conversion circuit for frequency-converting the first local oscillation signal to generate a second local oscillation signal. The received signal of the first frequency band is up-converted to a first intermediate frequency signal using one of the of first and second local oscillation signals, and the received signal of the frequency band is down-converted to the first intermediate frequency signal using the other of the first and second local oscillation signals.

Abstract: In a digital receiver, an equalizing unit includes a power controller adapted to scale received components of a quadrature amplitude modulated signal based on a constellation size of the quadrature amplitude modulated signal. Alternatively, a method of scaling components of a quadrature amplitude modulated signal includes the steps of searching the quadrature amplitude modulated signal to determine a constellation size, and scaling the components of the quadrature amplitude modulated signal based on the constellation size.

Abstract: A received signal obtained from an antenna is subjected to high-frequency amplification. The amplified signal is supplied to a first bandpass filter, which extracts only signals of all the channels of a communications system concerned while filtering out other radio signals. The extracted signals are frequency-converted by using a local oscillation frequency, and only a desired wave is passed by a second bandpass filter. The desired wave is supplied to a sample-and-hold circuit, which performs sampling according to the bandwidth-limiting sampling theorem. A resulting discrete signal is supplied to an I-axis-component and Q-axis-component separating circuits, where the polarity of sample values is inverted for every other clock pulse with respect to each of the I and Q axes to thereby effect Hilbert transform. Resulting two orthogonal components on a phase plane are supplied to a complex coefficient filter.

Abstract: A received signal obtained from an antenna is subjected to high-frequency amplification. The amplified signal is supplied to a first bandpass filter, which extracts only signals of all the channels of a communications system concerned while filtering out other radio signals. The extracted signals are frequency-converted by using a local oscillation frequency, and only a desired wave is passed by a second bandpass filter. The desired wave is supplied to a sample-and-hold circuit, which performs sampling according to the bandwidth-limiting sampling theorem. A resulting discrete signal is supplied to an I-axis-component and Q-axis-component separating circuits, where the polarity of sample values is inverted for every other clock pulse with respect to each of the I and Q axes to thereby effect Hilbert transform. Resulting two orthogonal components on a phase plane are supplied to a complex coefficient filter.

Abstract: A receiver for input signals generated using a phase-based modulation scheme such as bipolar-phase shift-keying (BPSK) modulation or quadrature-phase shift-keying (QPSK) modulation. The receiver can sample the input signal using one of at least two different sampling frequencies that are selected such that at least one of the sampling frequencies is not harmonically related to the carrier frequency of the input signal by a ratio of small numbers. In this way, the receiver can avoid interference patterns that can result when the sampling frequency and the carrier frequency are harmonically related. In one embodiment, the receivers are hard-limiting receivers that are suitable for use in the remote nodes of fiber-to-the-curb (FTTC) communication systems, where low-power receivers are desirable.

Abstract: A method and apparatus for determining initial carrier and symbol phase estimates in a burst mode digital communication system are described. In-phase and quadrature sample of a BPSK preamble are sampled to obtain correlation values. Next, sum and differences of the correlation values are obtained. Then the initial carrier phase estimate (THETAHAT) and the initial symbol phase estimate (TAUHAT) are obtained through application of an algorithm. The apparatus that implements the method consists of adders, inverters, arc tangent look-up tables and divide by 2 logic units.

Abstract: A Vestigal Sideband (VSB) demodulator having a clock generator for generating a clock signal based on a symbol frequency of the VSB signal; an A/D converter for converting the VSB signal into a digital signal based on the clock signal of the clock generator; a first multiplier for multiplying the digital signal by a first value sequence and generating a first multiplier output signal; a second multiplier for multiplying the digital signal by a second value sequence and generating a second multiplier output signal; a complex type filter for shaping and VSB demodulation of the multiplier output signals and generating Inphase and Quadrature data output signals; a decimating circuit for decimating the Inphase and Quadrature data output signals and generating decimated signals; a complex multiplier for multiplying the decimated signals by a predetermined value and generating multiplied output signals; an error detector for detecting a frequency deviation and a phase deviation from the multiplied output signals and

Abstract: A four-stage phase demodulation low frequency wireless mouse device is disclosed, improving a shortcoming of a conventional low frequency wireless mouse device which can not effectively overcome the signal interference and prevent the misoperations by only using I and Q axes or a quadrature demodulation method and the present invention installs a phase demodulation circuit on a receiving end for generating four sets of phase signals each having a phase of 0.degree., 90.degree., 180.degree. and 270.degree. respectively. Then, each of the quadrature signals is sent into a microprocessor for processing to become a computer interfacing signal after passing through a low pass filter, a detecting circuit and a voltage comparator respectively so that the signal interference is effectively eliminated, the misoperation is obviated and the reaction speed of the signal is enhanced due to a low error rate.

Abstract: A received signal obtained from an antenna is subjected to high-frequency amplification. The amplified signal is supplied to a first bandpass filter, which extracts only signals of all the channels of a communications system concerned while filtering out other radio signals. The extracted signals are frequency-converted by using a local oscillation frequency, and only a desired wave is passed by a second bandpass filter. The desired wave is supplied to a sample-and-hold circuit, which performs sampling according to the bandwidth-limiting sampling theorem. A resulting discrete signal is supplied to an I-axis-component and Q-axis-component separating circuits, where the polarity of sample values is inverted for every other clock pulse with respect to each of the I and Q axes to thereby effect Hilbert transform. Resulting two orthogonal components on a phase plane are supplied to a complex coefficient filter.

Abstract: A communication system where the data rate of a given transmission has been encoded by a transmitter and is then used to adjust a plurality of convolutional decoders sharing common memory. The system uses common processing resources to provide up to four discrete channels having multi-rate convolutional error correction decoding resulting in a reduced silicon area and low power operation. The system is capable of supporting data communication at 8 kbps up to 64 kbps for high rate ISDN communication in receivers of both base station and consumer unit locations.

Abstract: The transmitter QPSK-modulates the audio data, generates a transmission channel clock having a frequency 5/4 times the data clock based on the audio data, and outputs the modulated signal resulted from QPSK-modulation at the timing of the transmission channel clock. The infrared emitter emits infrared-rays based on the modulated signal. Digital data is thus efficiently transmitted by way of infrared-rays with suppressed complexity of data processing for modulation and demodulation.

Abstract: A demodulator and a demodulation method are designed so as to reduce the load of a CPU. A host CPU controls a digital demodulation circuit, an error correction circuit, a transport circuit and an MPEG decoder through a bus. The host CPU outputs a control signal to a format conversion circuit via a CPU interface when it instructs a tuner to perform tuning. The format conversion circuit converts the format of this control signal into a 3-wire format and outputs the converted signal to a frequency divider of the tuner.

Abstract: A symbol timing recovery (STR) error detector includes a complex multiplier and a Gardner-type symbol timing error estimator for operation with carrierless amplitude phase (CAP) signals. Quadrature Ir and Qr signals from the system are input to the complex multiplier, which also receives signals from a numerically controlled oscillator operating at the CAP center frequency. The output of the complex multiplier is provided to the input of the Gardner STR error estimator. An added frequency shift allows the Gardner error estimator to function with CAP signals. The output from the error estimator is provided to a loop filter the output of which is provided to an oscillator which generates the symbol timing information for a symbol sampling network.

Abstract: An object is to provide a digital quadrature detection circuit wherein, without making the circuit complicated and without lowering performance, the operating frequency can be lowered and power consumption can be reduced. There are provided: a quasi-synchronous detector that takes the exclusive logical sum of a binary-converted intermediate frequency signal and a carrier signal, sampling means that respectively sample the output of the quasi-synchronous detector at M phases (where M is an integer of 1 or more) for each symbol, a bit adder that generates an M-bit parallel signal from the output signals of these, and low-pass filters that extract the low frequency components from this output. Whereas conventionally a 100-times clock pulse was employed in order to obtain an M-bit parallel signal, in this case, a 20-times clock pulse is sufficient, due to the provision of five sampling means.

Abstract: An image-rejecting receiver comprises a tunable mixer stage, a time-share I-Q mixer stage, a complex filter, and an image rejector. The time-share I-Q mixer stage includes a switch assembly, inphase and quadrature polarity inverters, and a clock generator. The switch assembly generates pulses and distributes them in alternation to the polarity inverters. Performing distribution prior to polarity inversion preserves the orthogonality of the inphase and quadrature target signal components despite pulse-to-pulse bleeding. Charge accumulated at the distributor switch input is dumped between pulses to further minimize such bleeding. A current-mode field-effect-transistor implementation ensures unity gain across each polarity inverter so that they are gain-matched. Gain matching and preservation of orthogonality optimize the conditions for the complex filter to attenuate and for the image rejector to cancel an image signal.

Abstract: A communication system (10) includes a central terminal (12) and a subscriber terminal (14) that communicate information through an air interface (16). A receiver (22) suitable for deployment in either the central terminal (12) or the subscriber terminal (14) includes a parallel correlator (120), a weighting module (140), and a summer (180) that provide acquisition, equalization, and tracking functions.

Abstract: A frequency deviation measuring device is used in fields of digital mobile communication systems to measure frequency deviations with respect to .pi./4 QPSK modulation signals in accordance with the phase locus method. A center frequency is detected on the basis of a spectrum distribution measured with respect to a testing signal which corresponds to a digital modulation signal. A non-modulation signal is generated based on the center frequency detected from the testing signal. Quasi-synchronization wave detection is performed on the testing signal and non-modulation signal to produce an IQ base band signal. A first frequency deviation is detected based on the IQ base band signal in accordance with the phase locus method. A second frequency deviation is detected based on a difference between the center frequency and a testing frequency set value.

Abstract: A jitter suppressing circuit is provided for suppressing jitter generated in a multistate quadrature amplitude modulation type modulator or demodulator. Based on I- and Q-phase signals containing jitter, a signal point specified by the I- and Q-phase signals is obtained, and a phase difference between the signal point and an ideal signal point closest thereto is detected. Whether the ideal signal point belongs to a predetermined signal point group is then determined. When the result of determination is affirmative, the phase of the signal point specified by the I- and Q-phase signals containing jitter is corrected, on the basis of the detected phase difference.

Abstract: A .pi./n shift PSK demodulator of this invention is formed with a digital logical means through the following method. XOR4 calculates the ex-OR operation between the present sample through .pi./4 shift QPSK output from SH2 and the previous one output from SH1. Accumulating 1 among the outputs from XOR4 in the first operation means 5 and multiplying it by .pi./8 obtains the absolute phase difference between the present and the previous symbols. The former or latter four bits from SH1 are subtracted from the corresponding former or latter four bits from SH2, and the result of each bit is summed and its sign is added to the absolute phase data in sign addition means 10. After the phase offset is subtracted from the outputs from 10, it is demodulated into the original one in judgment circuit 13.

Abstract: An input quadrature modulation signal which is converted into a digital signal is converted into a complex baseband signal in a converter 7. A rough estimation of parameters of the signal is made in a rough signal correction unit 51. Using the estimates, the complex baseband signal is corrected. Utilizing a data detection of the corrected signal, a reference signal which corresponds to a transmitted signal is formed from the detected data in a generator 52. The reference signal and the corrected signal are used to estimate parameters in a fine parameter estimation unit 23.

Abstract: The invention relates to apparatus for synchronizing the phase of a digital signal constituted by two digital components to be corrected defining two samples of a received signal at each symbol time, said apparatus serving to feed a regenerator for regenerating the signal in baseband by sampling and threshold decision-taking, said apparatus including: a first phase-locked loop (31) driven by a first broadband phase-error integrator (37), said first loop (31) being fed with the input signal (30) of the apparatus, and supplying a first phase error estimate (36); and an auxiliary second phase-locked structure (32) driven by re-processing means (38) for re-processing said first phase error estimate (36) established by said first phase-locked loop (31), and outputting a phase synchronized signal fed to an output regenerator (34) for regenerating the signal in baseband; said auxiliary second phase-locked structure (32) being fed with said input signal (30) of the apparatus via delay means (35).

Abstract: A method for configuring the receiver with an IF delay value that indicates the timing of symbol transitions in a received signal processed by the receiver. The receiver recovers a timing that has the same period as the symbol period, but which is out of phase with the received symbols. The received symbols are members of a constellation with elements that have purely I or purely Q components. A symbol-quality signal is generated by constructing the quantity .vertline..vertline.I.vertline.-.vertline.Q.vertline..vertline.. This quantity is a maximum when the detected symbols are aligned with the expected points in the symbol constellation, and decreases if the detected symbols are rotated away from these constellation points. The method determines an optimal delay value by which the symbol clock should be shifted from the recovered timing by using the symbol-quality signal to evaluate test delays and to successively refine them until the optimal delay value is found.

Abstract: A fast algorithm for performing maximum likelihood detection of data symbols transmitted as phases of a carrier signal.

Abstract: A digital receiver includes a mixer stage receiving a carrier signal S(t) and delivering an intermediate frequency signal S.sub.FI (t) to a demodulation stage. The mixer stage is furnished with a PLL circuit for generating a signal at a given frequency. The digital receiver further includes a phase noise digital correction stage for tapping off a noise signal .phi..sub.n (t) generated by the PLL circuit in the mixer stage and for compensating the noise signal .phi..sub.n (t) in the demodulation stage.

Abstract: A receiving circuit mainly available in a digital modulation type communication system having a plurality of channels, which is capable of reducing power in a receiving system, simplifying the circuit and reducing the power consumption. Upside and downside frequencies corresponding to a central value between channels are separately supplied from a local frequency signal generating circuit 4 to first and second frequency converting circuits 2, 3 so that two output signals are developed with respect to one of a desired wave, upside channel and downside channel. The desired wave present in common in the first and second frequency converting circuits 2, 3 is extracted in a common wave extracting circuit 5, and a frequency offset of .omega.o existing in the output of the common wave extracting circuit 5 is removed a frequency offset circuit 6 and further an unnecessary frequency component is filtered by a filter 8.

Abstract: A phase demodulator (101) is used for sensing the phase.sub.-- angle of a phasor represented by the I and Q signals by first producing the analog I and Q signals in a direct conversion receiver (104). A phase generator (106) is used to approximate the angle of the phasor as represented by the I and Q signals by scaling and comparing the magnitudes of the I and Q signals and making decisions based on their relative magnitudes. The scaling includes successive alteration of the magnitude of the I and Q signals.sub.-- depending on their relative magnitudes. A DSP (108) is used to receive this bit stream representation (302) of the phasor and recover the information signal.

Abstract: A communication system (10) includes a rotationally invariant pragmatic trellis coded modulation (PTCM) encoder (18) and decoder (34). The PTCM encoder (18) partitions information bits (20) into primary (42) and secondary (44) data streams. A pilot bit (56) is inserted into the secondary data stream (44) during each frame (46). The secondary stream (44) then receives rate 1/2 convolutional encoding (60) that is punctured to a rate of 9/16. The primary data stream (42) is differentially encoded (50). The encoded primary and secondary streams are concurrently phase mapped (70) using an 8-PSK constellation so that an effective code rate of 5/6 results. The PTCM decoder (34) convolutionally decodes (84) the secondary stream, then re-encodes secondary stream estimates using a systematic, transparent convolutional encoder (88). The pilot bit is evaluated (92) in the re-encoded symbol estimates (90) to detect and correct any secondary stream inversion that may have occurred due to phase ambiguity.

Abstract: A carrier synchronizing unit for a coherent detection data communication system over non-frequency selective fading channels wherein the redundancy in estimation of a fading channel multiplicative distortion is reduced to improve the reliability of the estimation and compensate for an influence of a tracking delay in recursive least square estimation. The carrier synchronizing unit combines pilot symbols interpolation and recursive least square type phase and amplitude estimation.

Abstract: The present invention relates to a clock phase detecting circuit and a clock regenerating circuit each arranged in a receiving unit of multiplex radio equipment. The receiving unit of the multiplex radio equipment includes an identifying circuit for identifying a signal obtained by demodulating a multilevel orthogonal modulation signal; a clock regenerating circuit for regenerating a signal identification clock for the identifying circuit to supply the clock to the identifying circuit; an equalizing circuit for subjecting the signal obtained by demodulating a multilevel orthogonal modulation signal to an equalizing process. A clock phase detecting unit detects the phase component of the signal identification clock based on signals input to or output from the equalizing circuit and then supplies the phase component to the clock regenerating circuit.

Abstract: A receiver for decoding passband signal pulses transmitted in accordance with a M-ARY phase shift keying modulation scheme, comprises a multiphase sampler for sampling received passband signal pulses in the passband frequency range so as to generate a plurality of digital words corresponding to the sampled passband signal pulses, such that each digital word represents the phase of each sampled passband signal pulse. A phase reference register or other storage device is coupled to the multiphase sampler for storing one of the digital words as a phase reference such that other digital words generated by the multiphase sampler are compared with the digital word corresponding to the phase reference for decoding the passband signal pulses.

Abstract: A method and system for demodulating received signals in radio communication systems. Pi/4-DQPSK modulated signals can be demodulated to provide additional quality measurements and to facilitate diversity combination or selection. For example, a carrier is modulated with digital data using Pi/4-DQPSK to convey two bits of data by changing the radio carrier phase from the value at the end of the last symbol through an angle of either .+-.45 degrees or .+-.135 degrees, these four possibilities representing the bit pairs 00, 01, 11 or 10. The transitions of the radio signal are filtered in the complex (I,Q) plane to limit the spectrum. At the receiver, the received signal is downconverted, filtered and amplified using a hard-limiting intermediate frequency (IF) amplifier. The IF amplifier also produces an approximately logarithmic indication of the signal strength before limiting. The hard-limited IF signal containing phase information is fed to a direct phase digitizer.