Abstract: A non-coherent frequency shift keying detection scheme. The invention has been applied to the special case of capturing caller ID information when the voice-band modem is in the low power mode. The technique provides the capability for capturing and decoding enough of the caller ID information transmitted by the telephone company while the computer is in the sleep or low power mode, and upon awakening the computer can use this captured information to decode the actual caller ID information. Additionally, this invention automatically accommodates both the Bell 202 or V.23 transmission standards by utilizing a threshold concept in which the time that has elapsed between the zero crossings of an FSK tone half cycle are measured. The elapsed times may be used as an indication of which FSK tone has been transmitted thus allowing capture of caller ID information. The bit output of the caller ID capture circuit is output for storage by RAM thus allowing use by the computer when it wakes up.

Abstract: A highly reliable and high-speed data transmission is made by using an FH or MFSK mode as suitably selected according to the usage of channels. When a reception signal is entered into a receiver through a transmission line, (i) a signal processing unit supplies the spectrum intensity values of carrier frequencies, (ii) a channel detection unit controls the phase of a time slot based on the spectrum intensity values, selects the MFSK or FH modulation mode, and supplies reception code data corresponding to detected carrier frequencies, and (iii) a decoder supplies reception information data based on the reception code data.

Abstract: An error compensation circuit for compensating for a frequency error and a boost error of an IC chip having a filter and a boost circuit. The error compensation circuit includes a frequency compensation circuit, a boost compensation circuit, and a switch being switchable in response to a mode control signal. The frequency compensation circuit includes a first level detector to detect a level of a signal output from the filter; a first level comparator to compare an output level of the first level detector with a reference signal level; a first integrator to integrate an output of the first level comparator to generate a frequency error signal; and a first data converter and storage to convert the stored digital data into an analog frequency compensation signal in the normal signal processing mode, and provide the frequency compensation signal to the filter.

Abstract: A frequency shift keying device includes a reference oscillator which provides a reference signal, and a controlled oscillator having a control input and an output signal. A phase detector compares the output phase of the output signal with a reference phase of the reference signal to form an error signal on a detector output of the phase detector. The error signal provides phase locking of the output signal. A compensation circuit having a compensation input is connected to a modulation output of a modulation source which outputs a modulation signal. The compensation circuit also has a compensation output connected to the detector output. The compensation circuit provides a compensation signal which counteracts the error signal to form a modified error signal for attenuating the phase locking so that it becomes possible to modulate the controlled oscillator at a low rate without disturbing the sound spectrum which is also transmitted using a carrier generated by the controlled oscillator.

Abstract: A direct-conversion receiver includes a local oscillator for generating a local oscillator signal, a converter circuit for converting a received radio signal into a pair of a baseband I signal and a baseband Q signal in response to the local oscillator signal, a demodulator for demodulating the pair of the baseband I signal and the baseband Q signal into a demodulation-resultant signal which is neither an I signal nor a Q signal, a detector circuit for detecting a difference between a frequency of the local oscillator signal and a frequency of a carrier of the received radio signal, a clock signal generator for generating a first clock signal providing a timing which corresponds to a center of a symbol period, a signal delay device for delaying the first clock signal to provide a second clock signal, and a symbol deciding circuit for deciding a logic state of the demodulation-resultant signal at a timing determined by the second clock signal.

Abstract: A low power density radio system is provided using a simple FSK transmitter arranged to transmit very short bursts to a receiver at predetermined frequent intervals. Such a system can be used between a meter transponder and a reader in an AMR system to eliminate the need for a receiver in the transponder and still achieve extended battery life. The problems of detecting and demodulating the short burst are overcome by using a sample and hold circuit that detects a preamble signal of reversals to indicate the presence of the burst. The sample and hold circuit also provides the reference value to correct for the DC pedestal voltage that arises as a function of the transmitter and receiver frequency errors. The data signal that follows the preamble signal can then be detected, and is followed by a verifying signal as part of the signal burst. The burst signal is repeated at predetermined intervals and is preferably only {fraction (1/4000)} or less than the signal time interval.

Abstract: In the system according to the prior invention, in order to shape the demodulated base-band signal of an FSK signal from a frequency discriminator 1 into a rectangular waveform, a waveform shaping circuit which may comprise a comparator 2 is typically provided. Any error is detected by finding a difference between the input and output signal of this comparator after the amplitudes thereof were made equal and smoothing its result. The reason why with this system the above-mentioned disadvantage occurs is that in the case of a bit synchronization signal, for example, at the point of time when its center level becomes equal to the shaping circuit output level a zero output is provided by the operation of the subtraction.

Abstract: A frequency hopping transceiver having a protocol for selecting a clear channel for exchanging QAM payload data signals. An energy level in a current channel is sounded by to determine whether it is clear or busy. When the current channel is clear an outgoing frequency shift key (FSK) handshake signal is transmitted. When the current channel is busy or an incoming handshake signal is not received, the transceiver hops to the next channel without waiting until the dwell time has elapsed for the current channel. When a channel is clear and the FSK handshake signal is received the transceiver uses a differential synchronization time for exchanging QAM acquisition signals and payload data in unison.

Abstract: Disclosed is a frequency shift keying (FSK) signal demodulator which demodulates binary data encoded in FSK format. A square wave generator generates a continuously repeating square wave signal by detecting zero-crossings of an FSK-modulated signal having a first frequency and a second frequency. The square wave signal is sampled at a sampling rate. A counter and its control circuit counts the number of the sampled signals during 1 bit data transmission time slots. A comparator compares the count number with two predetermined reference values and outputs the binary data.

Abstract: A FSK demodulator which uses the combination of a digital phase comparator and a digital controlled oscillator (DCO) in the form of a state machine to demodulate an FSK signal. The phase comparator compares the phase of the FSK signal with the output of the DCO to provide a signal to the DCO having a level dependent on the phase relationship between the two signals at the input to the comparator. The demodulator also includes a filter to obtain the data from the signal at the output of the comparator.

Abstract: A system determines the time difference of arrival of a frequency shift kd signal (FSK) source at two separate receiver sites. The system includes a first receiver located at a first site for generating a first series of signal samples in response to detecting an FSK signal from a FSK signal source. A second receiver located at a second site generates a second series of signal samples in response to detecting the FSK signal. A first computer estimates first frequency shift times of the FSK signal in response to receiving the first series of signal samples and a time reference signal, and generates a first output signal representing the first frequency shift times.

Abstract: A frequency demodulator of the present invention includes: an amplification section for receiving a frequency-modulated signal and amplifying the frequency-modulated signal based on a gain so as to produce a digital signal having a predetermined level and an inverted signal of the digital signal; a digital demodulation section for receiving the digital signal and frequency-demodulating the digital signal; an amplitude detection section for receiving the digital signal and the inverted signal of the digital signal, and detecting maximum amplitude values of the digital signal and the inverted signal for a predetermined period of time so as to produce an amplitude signal in proportion to the maximum values; and a gain controlling section for varying the gain based on the amplitude signal.

Abstract: A method, system, and computer program product for spread spectrum communication is provided using circular waveform shift-keying (CWSK). Circular waveform shift-keying is a modulation technique for conveying data over a spread spectrum channel. Data symbols are encoded in a circular time shift and/or circular frequency shift of a spread spectrum waveform. In a receiver, a CWSK synchronization stage and demodulator stage can be combined on a single fast convolution ASIC chip. Using CWSK modulation and demodulation, a secure, low-cost terminal is realized that can process calls on multiple spread spectrum channels in a hubless wireless network linking large numbers of low data rate users.

Abstract: Circuit arrangement for generating a control signal. A circuit arrangement for generating a control signal for a controllable oscillator of a receiving device, is arranged to mix an FSK modulated input signal, having at least two predetermined input frequencies, with an oscillation, output by a controllable oscillator, so as to form an intermediate frequency signal, as well as to derive from the intermediate frequency signal a data signal whose instantaneous value is determined by the frequency of the intermediate frequency signal (intermediate frequency) and also a demodulator pulse signal whose frequency and/or phase is a measure of the frequency and/or phase of the intermediate frequency signal, from the intermediate frequency signal.

Abstract: A signal is processed for recognize an irregularity in the signal. First, an orthogonal imaginary signal corresponding to the signal to be processed is formed. This is followed by a transformation step, which is then followed by a differentiation step. The signal thus processed shows the irregularity particularly clearly, so that the irregularity can be isolated, selected and detected. Preferred fields of application for the present method and corresponding devices are in the medical field, information technology, and signal treatment in network engineering, in particular low, medium, and high voltage engineering.

Abstract: A swept frequency communication system includes a modulator that multiplies a frequency sweep signal with one or more underlying modulated communication signals to produce a swept frequency signal having a number of headerless tracks located directly adjacent one another in the swept frequency/time domain. A demodulator receives the swept frequency signal after that signal has been passed through a wireless channel, isolates a particular track of the received swept frequency signal to prevent a near/far problem, A/D converts the isolated track, resweeps the digitized isolated track, and then equalizes the isolated track using a blind channel equalizer to eliminate time-varying amplitude/phase impairments caused by transmission of that track through the wireless channel. The demodulator then removes the sweep signal from the equalized swept frequency track and decodes or demodulates the underlying modulated communication signal.

Abstract: A direct conversion receiver includes a reference clock signal generating section for generating reference clock signal. An amplifier section amplifies a received signal and extracts a desired signal from the amplified signal. An extraction reference clock signal generating section frequency-divides the reference clock signal based on a frequency division data to generate first and second extraction reference clock signals. An extracting section extracts a data from the desired signal and the first and second extraction reference clock signals. A control and processing section outputs the frequency division data to the extraction reference clock signal generating section and processes the data based on a control section clock signal corresponding to the reference clock signal.

Abstract: In this disclosure, a single combination of a multiplier and amplifier is utilized in a time-sharing manner for two-axis, in-phase an orthogonal phase components (I-axis and Q-axis components, respectively) so that the problem of a phase error relating to the use of the two separate circuits which are used for the respective two-axis components cannot be produced. Further, in this disclosure, this amplifier is constructed as a variable gain amplifier for the purpose of the application of AGC (automatic gain control) through the use of signal power obtained form the amplifier output, and any DC offset is automatically corrected using detecting and correcting means.

Abstract: A digital radio transmission and reception system capable of preventing shift of carrier by fading through receiving a modulated signal radio-transmitted, and then directly demodulating the signal.

Abstract: A method for demodulating digital frequency modulation (FM) signals is disclosed. A group of complex-valued discrete-time FM signal samples is initially received. A corresponding first complex product for each of the complex-valued discrete-time FM signal samples is computed, and a corresponding second complex product for each of the first complex values of the complex-valued discrete-time FM signal samples is computed. Subsequently, an inverse tangent of the second complex products are computed to yield an angle for each of the second complex values, wherein each of the angles represents a second-order difference of a phase of the complex-valued discrete-time FM signal samples. Finally, a digital integration is performed to obtain a first-order difference of the phase of the complex-valued discrete-time FM signal samples.

Abstract: A multi-level quadrature (I/Q) mixer for use in a communication system such as a paging device, where the mixer includes first and second I/Q downconversions followed by demodulation. The first I/Q downconversion converts an I/Q signal pair to a first IF, and the second I/Q downconversion converts an I/Q signal pair to a second IF. The first IF may or may not be the center frequency depending on the number of subchannels in the single channel being downconverted.

Abstract: In an FSK modulated signal receiving station a synchronization sub-system is arranged to sample the received signal and to select one sample per symbol within a detection window having a finite length, said samples being selected at predeterined instants. This produces a number of versions of the sampled signal and these different versions of the signal are then processed in parallel to determine the signal timing and the signal frequency offset.

Abstract: An M-ary FSK receiver in which a frequency down-converted signal is treated as an M-ary DPSK signal with symbol repetition coding. The output of a frequency demodulator (20) is integrated (22) over an optimally chosen time interval which is a fraction of the symbol interval to obtain N phase change estimates per symbol. These N sub-symbols are manipulated (24, 26) to obtain corresponding soft decisions which are then summed (32, 34) over a symbol period (or a substantial fraction thereof) to provide an overall soft decision for each bit comprising an M-ary symbol. These outputs may be used directly as soft decisions for forward error correction or applied to a threshold circuit to obtain hard decisions.

Abstract: A circuit is provided by which in the case of the transmission of a short packet signal through an FSK transmission channel having a frequency error for transmission and reception, directly from one shaped rectangular pulse of a frequency detected bit synchronization signal having a DC offset (this pulse including a bias distortion as it is) a clock signal can be generated indicating the points of time when the base-band signal passes through its center level and the point of time when it arrives its maximum or minimum value (data sampling points of time). This invention utilizes the fact that the bit synchronization signal is in the form of a sine wave because it has been band limited.

Abstract: A symbol detector for frequency modulated (FM) symbols includes a section determiner, a direction of movement determiner and a data symbol determiner. The section determiner receives a sample of in-phase and quadrature signals associated with a baseband transmitted FM symbol and determines the section value of a unit circle in an in-phase--quadrature coordinate system in which the sample lies. The direction of movement determiner receives the section value of a current sample and the section value of a neighboring sample and generates a positive direction of movement value if the direction of movement along the unit circle from the neighboring sample to the current sample is counterclockwise, a negative direction of movement value if the direction of movement is clockwise and 0 otherwise. The data symbol determiner receives the direction of movement values and decodes the transmitted FM symbol by masking N direction of movement values.

Abstract: A method for determining the best time to sample data bits of a data bit stream of a received information signal in a digital communication system includes the steps of determining the current derivative of a respective sample of the information signal, weighting the sample by a predetermined amount, determining an accumulated derivative value for the same sample number of a previous symbol of the information signal, weighting the previous accumulated derivative value by another predetermined amount, summing the two weighted values together and assigning this accumulated derivative value to the respective sample. The method further includes the step of comparing the accumulated derivative values of a predetermined number of consecutive samples to determine which sample has the greatest accumulated derivative value. The sample having the greatest accumulated derivative value substantially corresponds to the beginning of a symbol.

Abstract: An FSK signal receiver includes an amplifier which amplifies a first FSK signal at an adjustable gain. A frequency converter converts an output signal from the amplifier into a second FSK signal having a frequency lower than a frequency of the first FSK signal. A demodulator demodulates the second FSK signal into a baseband signal. A bit-state detector detects a bit state from the baseband signal in response to a threshold. A calculator calculates a number of times of occurrence of a fact that the baseband signal moves across the threshold during a given time. The gain of the amplifier is adjusted in response to the number of times which is calculated by the calculator.

Abstract: A method and apparatus for noise burst detection in a signal processor is provided. The method and apparatus is based on the zero-crossing rate (ZCR) of the received signal, which is defined as the number of times the magnitude of the received signal becomes zero during a specific counting period, to determine whether the received signal is a noise or a normal signal. The received signal is sampled at a specified sampling rate. Whether the signal waveform undergoes a zero-crossing is determined by comparing the polarity of the current sampled magnitude with that of the previous one. If the polarities are different, it indicates that the signal waveform has undergone a zero-crossing during the current sampling period; otherwise, it indicates that the signal waveform has not undergone a zero-crossing. The count of zero-crossing during each counting period is compared with a preset threshold value.

Abstract: A selective call receiver (800), including a receiver circuit (101) and a processor (810), is used for synchronizing an internal reference to symbol edges of a plurality of symbols in a multi-level radio signal transmitted by a radio communication system. To perform this function the processor (810) is adapted to cause the receiver circuit (101) to demodulate the multilevel radio signal to in-phase and quadrature signals (108, 106), convert the in-phase and quadrature signals (108, 106) to a sequence of state transitions representative of the plurality of symbols, detect at least one same state transition from the sequence of state transitions, and synchronize the internal reference to the at least one symbol edge of the plurality of symbols based on the at least one same state transition.

Abstract: A multivalued FSK demodulation window comparator includes an MSB comparator, an LSB comparator, a reception electric field strength detector, and a reference voltage generating circuit. The MSB comparator determines at least the polarity of a frequency shift of a radio frequency. The LSB comparator determines the absolute value of the frequency shift of the radio frequency. The reception electric field strength detector detects the strength of a radio signal and outputs a signal corresponding to the detected strength. The reference voltage generating circuit changes the reference voltages of the LSB comparator in accordance with an output voltage from the reception electric field strength detector. When the output voltage from the reception electric field strength detector is not higher than a predetermined level, a reference voltage from the reference voltage generating circuit changes.

Abstract: A data capture system includes a data early latch, a data on-time latch, and a data late latch each coupled to receive an input data signal and a first, second, and third data strobe signal, respectively. When the respective data strobe signal is triggered the respective data latch captures, or latches, the input data signal at three intervals resulting in oversampled input data signals. The on-time data latch generates the latched data signal. The latched data signal is compared with the data early signal latched by the data early latch as well the data late signal latched by the data late latch. If the latched data signal and the data early signal are not equal, a delay controller increases the delays of the data strobe signals. If the latched data signal and the data late signal are not equal, the delay controller decreases the delays of the data strobe signals.

Abstract: In a direct conversion receiver with an AFC function comprising a local oscillation circuit constituted by a synthesizer, the local oscillation frequency is prevented from radiating as an interfere wave against the receiver per se so as not to reduce the reception characteristic, and it is made possible to reduce the value of the multiplication factor N of a multiplier in the synthesizer without making the frequency of a VCO per se high. Specifically, a first local oscillation signal 12 obtained by multiplying an output frequency F.sub.X of a reference crystal oscillation circuit portion 8 of a synthesizer circuit section 7 by M by a multiplier 11 is mixed with an FSK modulation signal 1 in a first mixer 4. In a second mixer 5, the thus mixed signal is further mixed with a second local oscillation signal 13 obtained by multiplying an output frequency F.sub.V of a synthesizer 9 by N by a multiplier 10.

Abstract: A demodulated baseband signal of a bit synchronization signal which has been FSK modulated, because it was transmitted with a narrow frequency band, is usually in the form of a sine wave on which a DC drift is superposed. Since this DC offset will cause bias distortion for transmission codes, it is needed to detect this offset component at higher speed and with a simpler manner as soon as signal incoming occurs and to correct this. This invention attains this by providing a center error detecting circuit for an FSK signal receiver comprising: sampling means for sampling the bit synchronization signal of a demodulated FSK baseband signal by two sampling pulses separated mutually by the reciprocal of the transmission rate in bits per second; and means for finding the mean value of the two samples thus obtained, so as thereby to provide the DC center level of the baseband signal.

Abstract: A direct conversion receiver for a radio system has an antenna and blocking filter connected to an amplifier. The input signal is split and mixed with an in-phase signal and a quadrature phase signal generated by an oscillator in a mixer circuit. An output from each mixer circuit is applied to a low pass filter and to an input of a limiting circuit. The output from each low pass filter is applied to respective circuits, a first of which is arranged to sum the in-phase and quadrature phase signals, and the second of which is arranged to subtract the in-phase and quadrature phase signals to generate a respective output signal having an axis intermediate the in-phase and quadrature phase signal axes. These signals, together with the in-phase and quadrature phase signals are passed through a limiting circuit respectively, to a decoder circuit for recovering the data. The output of the limiting circuits represent signals quantized to eight possible phase states separated by 45.degree..

Abstract: In an FSK receiving apparatus, a quadrature FSK-modulated signal is received at an I/F unit and demodulated, the state of the frequency eccentricity is detected at a comparator, and the signal as the result thereof is input to a decoder.

Abstract: A transceiver with an antenna oscillating circuit generates a magnetic field which inductively charges a charge capacitor of a transponder through a transponder oscillating circuit. A frequency-modulated oscillation is thereupon generated in the transponder and that oscillation is transmitted back to the transceiver. In order to ensure that the transceiver will receive the highest possible amplitudes of the frequency-modulated oscillation, the resonant frequency of the antenna oscillating circuit is adapted to the oscillation frequencies of the transponder oscillating circuit. To that end, an impedance is connected, automatically weighted, to the antenna oscillating circuit.

Abstract: A direct conversion receiver has: an I-low-pass filter 9 which has cut-off frequency switching device, switches over the cut-off frequency in accordance with the transmission rate, and eliminates high-frequency components from a modulated signal mixed with a first local signal; a Q-low-pass filter 10 which eliminates high-frequency components from a modulated signal mixed with the first local signal phase-shifted by 90 degrees; transmission rate detecting device 13 for detecting transmission rate information from transmission data detected by transmission data detecting device 12; and I- and Q-low-pass filter cut-off frequency controlling device 15 and 16 for generating I- and Q-control signals which control the cut-off frequency switching device, from the detected transmission rate. The cut-off frequencies of the low-pass filters are switched over in accordance with the transmission rate of reception.

Abstract: A communication device (1) for computer local networks of the cordless type uses a modulator (MOD) able to perform FSK modulation on the data (DDI) to be transmitted, with optimum characteristics thanks to a digital switch (SW) controlled by the data (DDI) which commutes during transmission between two fixed frequencies received from a quartz oscillator, in association with a filter of the surface acoustic wave type (SAW). The device (1) permits a significant improvement in circuit integration and is simple and of low cost.

Abstract: A digital communication system is disclosed which is unique in that it modulates a sinusoidal carrier with a discrete cosine segment, a zero slope level segment, and combinations thereof. The discrete cosine segments may contain different time and amplitude values. The discrete cosine segments may be combined with each other or with zero slope level segments in order to effectively modulate the sinusoidal carrier. Rather than employing the use of filters for controlling instantaneous voltage changes, the present communication system forces the bit edges of the discrete cosine segments to occur at the zero slope points of a cosine wave, where no voltage changes occur. The communication system utilizes direct digital synthesis in order to create a carrier signal which closely represents sinusoidal carrier signal. The present communication system may be used in conjunction with various conventional methods such as phase-shift keying and amplitude-shift keying.

Abstract: A method and apparatus for encoding and convolutionally decoding a data word of a data word sequence. For a data word having k bits, a 2.sup.k subset of signal points from a square set of M by M signal points having X coordinates and Y coordinates is selected using a trellis encoding algorithm and a previous data word. The square set of M by M signal points includes a constellation of 2.sup.k+1 signal points. A signal point from the selected subset of signal points is selected using the n.sup.th data word. A modulator generates a first FSK signal and a second FSK signal from the selected signal point. A demodulator demodulates the first FSK signal as a received X coordinate and the second FSK signal as a received Y coordinate. A 2.sup.k received subset of signal points is estimated by using the convolutionally decoding algorithm and a previously received data word. An n.sup.

Abstract: A system for demodulating a FSK digital signal comprising: first and second frequency detectors connected to detect the frequency of the digital signal, the first frequency detector producing an output signal whenever the digital signal is detected to have a first frequency and the second frequency detector producing an output signal whenever the digital signal is detected to have a second frequency; first and second low pass filters each having an input connected to receive the output signal produced by a respective frequency detector and an output for providing a smoothed version of the signal at the respective filter input; and signal combining circuitry connected to the outputs of the first and second filters for providing a demodulated output signal representing the FSK digital signal.

Abstract: A VMWI (Visual Message Waiting Indicator) multisense detection device solves both the problem of long CLASS VMWI signal retransmission delays and unreliable CLASS VMWI signal transmission by simultaneously enabling both stutter dial tone detection and CLASS VMWI signal detection. The multisense device samples the line each time the phone is placed on-hook or after the phone goes unanswered after a ring. If a valid CLASS VMWI signal is detected before the scheduled dial tone test, the dial tone test will be canceled. If no CLASS VMWI signal is detected, after a given amount of time, the VMWI device automatically enables stutter dial tone detection. The detection circuitry periodically polls for a preamble field of the CLASS signal to determine whether a valid CLASS signal is about to be transmitted. If the preamble indicates a CLASS signal is being transmitted, the detection circuitry remains on and the CLASS signal is received and processed.

Abstract: Known is a receiver having a demodulator for intermediate frequency modulated frequency shift keyed signals. The known demodulator applies absolute period time measurements expressing the period of a divided IF-signal into clock pulses of a relatively high frequency reference clock to detect data from a received signal. Such a demodulator is sensitive to frequency drift of the reference clock and has a relatively large power consumption. A receiver is proposed having a demodulator that is arranged to transform the intermediate frequency modulated frequency shift keyed signal into a lower frequency modulated frequency shift keyed signal so that the relative frequency deviation representing the data becomes substantially larger.

Abstract: A digital frequency demodulator includes a first counter and a second counter measuring the instantaneous and mean values of the period of a frequency modulated signal. A comparator compares the values measured and creates a binary signal of the same frequency as the modulation signal. The measurement of the instantaneous value of the frequency modulated signal is effected by counting the number of reference clock pulses during a period of the modulated signal, and the measurement of the mean value is effected by counting the number of pulses of a clock signal of frequency N times lower than the reference clock during N periods of the modulated signal.

Abstract: A frequency shift keyed demodulator system employs a first bandpass filter having a passband centered at a first frequency; a second bandpass filter having a passband centered at a second frequency; a first Goertzel's discrete Fourier transform processor coupled to an output of the first bandpass filter; a second Goertzel's discrete Fourier transform processor coupled to an output of the second bandpass filter; and an adder coupled to an output of the first Goertzel's discrete Fourier transform processor, and to an output of the second Goertzel's discrete Fourier transform processor.

Abstract: A selective call unit (800) comprising a receiver (100) and a processor (810) is used for decoding a 2-level radio signal. The processor (810) is adapted to convert in-phase and quadrature signals generated by the receiver (100) to a sequence of state transitions representative of the plurality of symbols. For each symbol in the plurality of symbols, the processor (810) counts the sequence of state transitions during a symbol period, and compares the recorded count to a predetermined threshold, thereby generating a comparison result. The processor (810) then calculates a bit decision threshold level based on an average of the comparison result for each symbol in the plurality of symbols. For each symbol in a plurality of subsequent symbols, the processor (810) then compares the bit decision threshold level to the sequence of state transitions counted during a symbol period to decode a digital logic level therefrom.

Abstract: A C-Band or Ku-Band satellite communication system uses a relatively small receiving antenna while operating within current FCC designated bandwidth and using existing satellite configurations. Aperture synthesis techniques create nulls in orbit locations from which potential interference is expected. Bandwidth inefficient modulation techniques reduce transmission power flux density. Video compression reduces the power necessary to transmit video information. These three features make possible a receiving antenna with a receiving area equivalent to that of a three foot diameter dish, at C-Band frequencies. Comparable reductions are possible for Ku-, Ka-, S- and L-Band systems. Compressing the data reduces the required transmitted power by a factor of ten. Spreading the bandwidth reduces the power density below the FCC limitation.

Abstract: A signal FSK-modulated with a binary data signal has first signal portions representing first logical level data contained in the binary data signal and second signal portions representing second logical level data contained in the binary data signal. Each of the first signal portions has a first frequency and lasts for a first time period and each of the second signal portions has a second frequency and lasts for a second time period. These first and second time periods are determined such that a number of cycles of the FSK-modulated signal appearing in each of the first time periods is equal to a number of cycles of the FSK-modulated signal appearing in each of the second time periods.

Abstract: A miniaturized FSK demodulation circuit for accurately demodulating a signal having a small modulation index comprises a multiplier for multiplying a FSK modulated input signal by 4, an oscillator for generating a first signal having the same frequency and phase as the input signal, a phase shifter for producing a second signal by phase shifting the first signal by 90.degree.

Abstract: A microcontroller (100) for processing caller information received from a telephone line to display on a display panel of a telecommunication device. The microcontroller (100) includes a central processing unit (160), a display control unit (110) for controlling the display panel, a ring detector (140), a carrier detector (150) for detecting the caller information, memory (120) for storing a plurality of predetermined control parameters, and a caller identification unit (130) for providing the caller information to the display control unit (110). Within the caller identification unit (130), a power management (134) unit controls a power supply (170) to a signal demodulator (132), based on the plurality of predetermined control parameters, to process the caller information. Of the plurality of predetermined control parameters, a first control parameter enables the power supply and a second control parameter disables the power supply (170) to the signal demodulator (132).