Abstract: A remote signaling receiver system includes a receiver that operates in two different modes of demodulation to accommodate different types of signals from different types of transmitting devices. A first demodulator, preferably an ASK demodulator, is adapted to process signals from a signal transmitter that generates a first type of signal. A second demodulator, preferably one that is not sensitive to amplitude modulation such as a FSK demodulator, is adapted to process signals received from at least one other type of device, which provides a second type of signal. A system designed according to this invention is particularly useful as a remote keyless entry system for a vehicle where one or more sensors are provided on the vehicle to provide an indication of a chosen condition of one or more of the vehicle components.

Abstract: In demodulation of a FSK signal, a circuit for detecting a center level of said signal and correcting an error thereof is provided. Said circuit can accomplish the detection of the center level correctly always even if there exist cords with various lengths in a length of “1” or “0” of a synchronizing signal at beginning of communication and during communication, and yet frequency variation happens at that time. Said circuit has sample hold circuits SH1 and SH2 each of which are provided so as to correspond to “1” and “0” of an input demodulated data signal. In said circuit a center level value is an average value of voltages held in said sample hold circuits when said signal changes from “1” to “0” or “0” to “1” and a center level value is obtained by adding or subtracting a voltage of ½ of difference between two hold voltages held in another sample hold circuit SH3 to or from a hold voltage in a receiving side at present time when said signal keeps “1” or “0” continuously.

Abstract: A system and method are disclosed for providing a FSK demodulator using DLL and a demodulating method which detects a time order of the rising edges of square waves that correspond to two modulation frequencies and an in-between frequency and demodulates the relevant frequencies into data. The FSK demodulator includes a band-pass filter, an amplitude limiter for converting a waveform of the frequency filtered into a square wave, a delay line for receiving the square wave from the amplitude limiter and delaying the square wave for a delay time, a delayed flip-flop (DFF) for receiving an output signal from the amplitude limiter and an output signal from the delay line, determining which rising edge of the two input signals is earlier at a given time, and outputting the result of the determination as data, and a DLL circuit that locks the delay time of the delay line.

Abstract: In response to a first signal having modulation representing information and a modulation index, embodiments of the present invention generate a second signal that differs from the first signal in its modulation index, and demodulate the second signal. In one embodiment, an arrangement having a signal processor is adapted to receive a first signal having modulation representing information and having a first modulation index and to generate, in response to the first signal, a second signal having frequency modulation representing the information and having a second modulation index different from the first modulation index, and a demodulator coupled to the signal processor so as to receive and demodulate the second signal.

Abstract: A method is disclosed for optimally adjusting the received bit detection threshold in a digital communication system, such as a TDMA system that is characterized by very short duration burst transmissions. In one embodiment of the invention, a half-duplex radio modem is used for transmission and receipt of messages for airborne and ground-based Automatic Dependent Surveillance-Broadcast (ADS-B) service. A feedback path is provided for in the transmission/receiver unit to provide the transmission signal to the receiver path. A bit detection threshold adjustment circuit receives the transmission signal. The circuit digitizes the analog baseband signal, detects the positive and negative peak values and calculates a peak-to-peak deviation value to define the bit detection threshold value.

Abstract: One embodiment of the present invention enables a low performance and low cost microprocessor (or microcontroller) to perform binary demodulation of analog communication signals. Within the present embodiment, three techniques may be utilized to enable this functionality. For example, an analog-to-digital converter sampling rate technique is utilized with an incoming modulated analog communication signal. This sampling rate technique is able to eliminate the need for any reference sine and/or cosine waves during the demodulation process. Next, utilizing sample values produced by the sampling rate technique, a continuous-time sum of products calculation is performed by a central processing unit (CPU) of the microprocessor or microcontroller. The results of the continuous-time calculation then enables the present embodiment to demodulate the binary modulated analog signal.

Abstract: A technique for down converting signals from an Intermediate Frequency (IF) input signal to Inphase (I) and Quadrature (Q) signal samples at baseband replaces power-consuming A/D converters and AGC circuits with a low-cost zero-crossing comparator. The comparator converts the IF signal to a hard-limited signal having one value when the IF signal is positive and another value when the IF signal is negative. I and Q samples are generated by performing the equivalent of multiplication of the hard-limited signal by cos(2?fo*t) and sin(2?fo*t). By sampling the hard-limited signal at a rate that is an integer multiple of the intermediate frequency and an even number greater than or equal to four, multiplication by cos(2?fo*t) and sin(2?fo*t) required to generate I and Q baseband signal components is greatly reduced. The I and Q samples are summed (or integrated) by binary up/down counters over one bit duration and then dumped.

Abstract: A demodulation arrangement for a radio signal is disclosed wherein an I/Q mixer converts the radio signal to a real and an imaginary component and supplies the components to a limiting circuit. The limiting circuit limits the amplitude of the signals applied to its inputs. A demodulator circuit receives the output of the limiting circuit and converts the signal components to a demodulated signal including a sequence of pulses. A pulse shaper circuit converts the pulses having pulse amplitudes that are greater than a first threshold value to output pulses having a predetermined first amplitude. This reduces fluctuations in the pulse amplitudes, thus leading to a reduction in low-frequency interference and jitter in the data signal.

Abstract: This invention provides a method for bit detection of the GFSK signals at the receiver end. The bit detection is done digitally after the carrier is removed. It employs differential detection incorporated with decision feedback, which uses previous one (so-called on-bit differential detection), or two (so-called two-bit differential detection) bits as correcting information. In addition, synchronization for bit timing and frequency offset resulted from clocks between the transmitter and receiver are also performed with or without preamble as prior information. If preamble is available, the bit timing and frequency-offset bias are estimated from the preamble, which is the case of this present invention. If preamble is not available, this information is estimated directly from the unknown received signals. Once the information about the bit timing and frequency offset is obtained, it is used for the following bit detection.

Abstract: A signal detection circuit for receiving a digital baseband signal comprising an amplitude modulated symbol stream of Logic 0 symbols and Logic 1 symbols, each of the Logic 0 and Logic 1 symbols comprising S sequential samples, wherein the amplitude modulated symbol stream contains a preamble of N known symbols preceding a plurality of user data symbols. The signal detection circuit comprises: A) a signal mean determination circuit that receives G samples from the digital baseband signal and determines an amplitude mean value associated with the amplitude modulated symbol stream; and B) a correlation circuit that detects the preamble.

Abstract: A method for multi-user detection includes receiving a complex input signal due to a superposition of waveforms encoding symbols in a real-valued constellation, which are transmitted respectively by a plurality of transmitters in a common frequency band. The complex input signal is sampled at sampling intervals over the duration of an observation period to provide a sequence of complex samples. The sequence of complex samples is processed to determine soft decision values corresponding to the symbols transmitted by the plurality of the transmitters in the observation period, while constraining the soft decision values to be real values. The soft decision values are then projected onto the constellation to estimate the transmitted symbols.

Abstract: A non-coherent frequency shift key demodulator comprising an oversampling device, a chain of registers, and a threshold device is disclosed. The oversampling device receives an input digital non-coherent frequency shift signal, and examines for transitions therein, and thereby generating data bit signals in the form of logic high level ‘1’ or logic low level ‘0’ accordingly. The chain of registers receives, counts and stores the number of 1's data bit signals. Following, the threshold device compares the stored number of 1's in the chain of registers with a predetermined threshold value to extract the digital signal of the input digital non-coherent frequency shift signal. The non-coherent frequency shift key demodulator, by the use of a simple circuit and implementation, combats miscellaneous system impairments, such as frequency offset, and further support multi-rate transmission.

Abstract: A receiver circuit of a cordless communication system has an analog signal processing section with a channel selection filter and a digital signal processing section which is connected downstream of the latter and has a group delay equalizer. The group delay equalizer is used to equalize the digital distortion caused by the channel selection filter.

Abstract: In a method for estimating a sequence of input data symbols of a CPFSK-modulated data signal transmitted via a faulty channel, in the course of an ACS operation for calculating a transition metric value, an estimated value is determined for the replacement symbol occurring during the linear approximation of the CPFSK. That estimated value is considered in calculating the transition metric value.

Abstract: All-digital FSK demodulation can be accomplished by producing in response to a received IF signal digital information (22) indicative of a frequency of the IF signal. A symbol represented by the IF signal can then be determined (28, 44) in response to the digital information.

Abstract: A BFSK demodulator comprises a three-channel frequency-to-voltage converter, an information signal inputting the first-channel frequency-to-voltage converter, a converted information signal inputting the second-channel frequency-to-voltage converter, wherein outputs of first and second channel frequency-to-voltage converter are connected with a capacitor, a output voltage signal produced by the first and second frequency-to-voltage converters and the capacitor, inputting into a positive terminal of the comparator after high frequency noise filtering through a first low-pass filter, a carrier signal inputs into the third-channel frequency-to-voltage converter; and an output from the third-channel frequency-to-voltage converter connected to a capacitor; and a reference voltage signal is produced after high frequency noise filtering through a second low-pass filter, producing a demodulated signal after comparing the information voltage signal with the reference voltage.

Abstract: A data recovery algorithm for implementation in a radio transmitter or receiver that includes a direct current level setting circuit with a preamble detector which will establish a threshold for a simplified decision simplified equalizer slicer that improves receiver performance in a feedback manner by utilizing an analog comparator, a one symbol long one bit resolution delay line and a summing junction.

Abstract: A method and arrangement for receiving a frequency modulated signal, includes mixing the frequency modulated signal into a low-frequency signal, detecting the falling and rising edges of said low-frequency signal and forming a second signal on the basis of the edge detection, where the frequency of the second signal is twice the frequency of the low-frequency signal, and frequency detecting the second signal to form a demodulated signal.

Abstract: A radio receiver is configurable to operate in both low-IF and zero-IF modes with maximum re-use of of analogue and digital circuitry between modes. The receiver comprises a quadrature down-converter for generating in-phase (I) and quadrature (Q) signals at an intermediate frequency and a complex filter for performing image rejection filtering. In the low-IF mode, one of the outputs (Q) of the filter is terminated, the other (I) is digitised by a non-complex ADC then the digital signal is filtered and decimated. Quadrature-related IF signals are then re-generated before down-conversion and demodulation. In the zero-IF mode, both outputs of the filter are digitised and processed in parallel before demodulation. By enabling analogue-to-digital conversion and channel filtering to be performed at low-IF on non-complex signals, use of just two non-complex ADCs is possible, thereby avoiding duplication of circuitry and providing significant power savings.

Abstract: An apparatus and method for estimating a frequency and/or a phase of a digital input signal by determining phase values of the input signal. The phase values are then added over a predetermined summation length N/B. The sampling rate of the added-up phase values are reduced by a factor N/B in comparison with the sampling rate of the phase values. The added-up phase values are delayed in a chain of at least B?1 delay elements. The differently-delayed added-up phase values are then added or subtracted to create a resulting. pulse response of the frequency such that the resulting pulse response of the frequency is constant positive in a first interval, is zero in a second interval and is constant negative in a third interval, so that a resulting pulse response of the phase is constant in at least a middle interval or is otherwise zero.

Abstract: A circuit for detecting and correcting a center level is constituted for when the length of a code of “1” or “0” in an FSK signal is extremely long and superimposed with a frequency fluctuation of a transmitter/receiver. This circuit has sample value holding circuits exclusive to “1” and “0” of an input demodulation data signal. After a difference voltage between both sample values is once converted to a digital code in an ADA converter, the converted code is re-converted to an analog value, thereby holding the value digitally. When “1” s repeat, the hold voltage to “1” is updated to new values and simultaneously a voltage obtained by subtracting the difference voltage from the above-described voltage is applied to the holding circuit for “0” to update the value in the holding circuit. Also, when “0”s repeat, the processing proceeds in reverse and the holding circuit for “1” is updated with a voltage obtained by adding the difference voltage to the hold voltage.

Abstract: There is provided a signal demodulating method of a two-phase frequency shift keying (FSK) digital demodulator. The method utilizes at least a detect circuit respectively detecting and collecting a positive edge signal and a negative edge signal of an intermediate frequency signal. Then, two n-bit ripple counters are utilized to refer to a threshold value and then receiving the positive and negative edge signal as a switch signal to reset the threshold value as an initial value of counters so as to start to count and compare to output a positive edge data bit and a negative edge data bit. Last, a hard decision logic circuit is used to perform a frequency-descending decision in accordance with the positive and negative edge data bit so as to send a base frequency signal. The method can decrease the logic gate counts, shorten the signal delay time, and increase the resolution of the demodulation.

Abstract: A phase-locked loop includes a phase detector which receives an input signal and a first internal periodic signal and provides a phase signal indicative of a phase difference between the input signal and the internal signal. A rotator then receives the phase signal and provides first and second periodic signals each having a frequency that is a function of the phase difference, the first and second periodic signals being 90 degrees out of phase with each other. An interpolator circuit then linearly combines the first and second periodic signals with third and fourth periodic signals to provide the first internal periodic signal. The interpolator circuit may provide a second internal periodic signal that is 90 degrees out of phase relative to the first internal periodic signal. The phase-locked loop may further include a low-pass filter provided between the phase detector and the rotator.

Abstract: In known telephone subscriber end stations a caller_ID IC detects a tone alerting signal TAS alerting that successive caller_ID information can be received for displaying on a display of the phone. The known station applies narrow frequency band filters to detect tones indicating the end of TAS. Such a detection is not flexible as it can only be used for a specific caller_ID signal protocol. A flexible detector is proposed which can easily be adapted to widely varying protocols and which can also be used for other purposes such as the detection of power drops in an FSK signal. The detector comprises means for determining a time-domain signal representing the signal energy of a signal on the subscriber line in a predetermined time interval.

Abstract: This invention is regarding a frequency shifting circuit suitable for a digital demodulator in a multi-carrier communications system. After converting analog signal vectors to the input signal vectors according to a predetermined sampling clock, control data is generated from a frequency difference between sub-carrier bands and center carrier band. A signal vector rotator is provided corresponding to each of the sub-carrier bands and rotates the input signal vectors on the I-Q plane by an angle determined depending on corresponding control data to shift the sub-carrier bands of the input signal vectors to the center carrier band. A band-pass filter passes an output signal vector of the center carrier band.

Abstract: A digitally implemented demodulator. A frequency-modulated signal is applied to a limiting amplifier such that the signal amplitude is fixed at a constant level. The signal is undersampled and quadrature demodulated. The demodulator generates the cross-product of the baseband complex envelope to recover the original modulating signal. A digital Frequency Shift Keyed signal can be further recovered by applying the recovered signal to a data slicer to square-up the signal, and a matched filter for improved error resistance.

Abstract: A demodulator includes a count section, a synchronization timing setting section, and a code judgment section. The count section has four counters that count a number of waves of an FSK-modulated digital signal at different timing within a bit time width. The synchronization timing setting section designates a synchronized timing signal based on the count value of the count section. Then, the code judgment section compares the count value with a threshold value to judge the signal level, thereby decoding the digital signal.

Abstract: A receiver section recovers the in-phase and quadrature components of a linear modulated data signal. The in-phase signal is sampled and quantized producing an in-phase sample stream, and the quadrature phase signal is sampled and quantized producing a quadrature sample stream. The in-phase sample stream and the quadrature sample stream are both over-sampled at a rate of N times a symbol rate of the data signal. A decimation section filters the quantized in-phase sample stream and the quantized quadrature sample stream to produce a reduced in-phase sample stream and a reduced quadrature sample stream at a rate of M times the symbol rate, wherein M is less than or equal to N.

Abstract: An FSK receiver comprising: 1) demodulation circuitry for receiving an incoming FSK signal and generating a baseband signal comprising an amplitude modulated symbol stream of Logic 0 symbols and Logic 1 symbols having a data rate, R; 2) auto-correlation circuitry for sampling the baseband signal S times during each symbol and generating an auto-correlation function comprising a sample stream of N-bit samples having a data rate, S×R, and having positive-going peaks approximately coinciding with the center of the Logic 1 symbol in a 010 sequence in the baseband signal and negative-going peaks approximately coinciding with the center of the Logic 0 symbols in a 101 sequence in the baseband signal; and 3) decision circuitry for receiving the auto-correlation function and deciding a logic level of a first symbol as a function of: 1) a comparison of a signal level of a center sample of the first symbol and a mean signal level of the auto-correlation function and 2) a comparison of the signal level of the center sam

Abstract: A wireless transceiver comprises a digital to analog converter having an input for receiving a digital representation of a direct sequence spread spectrum signal and having an analog output. A filter has an input coupled to the analog output of the digital to analog converter. An adder has a first input coupled to the filtered output and a second input coupled to a loop control voltage generated by a phase lock loop. A VCO integrated into the phase lock loop has a control input coupled to the summed output. An RF output of the VCO produces a continuous phase frequency shift keyed spread spectrum signal in response to the digital representation of the direct sequence spread spectrums signal. A receiver converts received RF signal to baseband in-phase and quadrature that are in turn converted to digitized signals. A demodulator produces chip data that is despread using a matched filter.

Abstract: A method of, and terminal for, detecting the presence of a 2-FSK signal, the method comprising receiving (10) a 2-FSK signal, quadrature frequency down-converting (34,35,36) the received signal to produce quadrature related outputs, oversampling (42,43) the quadrature related outputs to produce digital samples, differentially decoding (44) the digital samples to produce real and imaginary components, integrating (56,58) the imaginary components and comparing (26) the integrated value with a fixed threshold value (24) and determining a signal to be present if the threshold is exceeded.

Abstract: A digital demodulator employing a digital differential detection mechanism based on extracting phase differences directly from the I and Q signals after downconversion to zero-IF and image rejection are performed. The phase of the input I and Q signals is determined using the principle that the phase is equivalent to arctan 1 ( Q I ) .

Abstract: A direct-sequence-spread-spectrum (DSSS) optical-frequency-shift-keying (OFSK) code-division-multiple-access (CDMA) communication system is adapted with optical transmitters and receivers for preferred use fiber optical communication systems where modulated data and pseudorandom noise (PRN) codes are encoded in the optical domain and communicated over optical paths for increasing system capacity in wide area optical networks.

Abstract: The invention provides a method and apparatus for achieving timing synchronization during signal acquisition and for achieving frequency synchronization in a digital communication receiver after signal acquisition.

Abstract: A data slicer for an FSK demodulator employs a peak and valley detector, each of which has a discharge path with selectable decay rates. One of the decay rates is significantly faster than another. The data slicer employs a decay rate selector that selects between the faster and slower decay rates. The data slicer is fed with a frequency-to-voltage converted FSK modulated signal. The faster decay rate for the peak and valley detector outputs is selected when the difference between the current peak and valley voltages exceeds a predetermined percentage (e.g. 75%) of the expected swing of the voltage input (i.e., when there is a DC offset present due to an offset in the carrier frequency of the transmitter). In this mode, the faster decay rate permits faster acquisition of packet data in the presence of DC offset, as it permits the data slicer to converge on an appropriate switching point more quickly.

Abstract: A wireless receiver 200 and corresponding method 500 is arranged to mitigate the effects of non-ideal receiver processing and comprises: a signal source 202 for providing an injection signal that is controlled to have a unique frequency at each of a plurality of time periods; and a non-ideal receiver device 208 constructed to use the injection signal for down converting a received signal having a known frequency to collect a plurality of waveform samples, each having a desired characteristic that varies with the unique frequency and an undesired characteristic, wherein one of the plurality of waveform samples with the undesired characteristic removed will retain the desired characteristic of the received signal.

Abstract: A spread spectrum radio receiver configurable for use in both a quadrature phase shift keying (QPSK) and a frequency shift keying (FSK) environment. The receiver may include a programmably selectable zero crossing detector unit for use when the receiver is configured for the FSK environment and/or programmable low pass filters having variable cut-off frequencies. A common local oscillator may be used regardless of whether the receiver is configured for use in the QPSK or FSK environment.

Abstract: A non-coherent frequency shift key demodulator, which includes a digital limiter and a decision logic circuit is disclosed. The digital limiter is used for receiving a baseband signal with a digital signal conveyed therein and comparing the baseband signal with a reference level in order to output a frequency-modulated rectangular pulse. The decision logic circuit, coupled to the digital limiter, is used for receiving the rectangular pulse and counting the transformation of the rectangular pulse to obtain a cycle period, wherein the cycle period is compared with a threshold value to determine the digital signal carried in the baseband signal.

Abstract: Disclosed is a method and apparatus for receiving FSK signals using estimation theory. A received signal is filtered to obtain energy estimates for a first frequency corresponding to a binary “0” and a second frequency corresponding to a binary “1”. The energy estimates are subtracted to obtain a difference value and an odd number of samples of a series of difference values is smooth filtered in order to produce a series of average values. A sliding window is applied to the series of average values that detects a clear majority of sample corresponding to either the binary “0” frequency or the binary “1” frequency in order to produce a binary output signal that corresponds to the received signal.

Abstract: In a method for demodulating a CPFSK-modulated signal, the n−1-th substitute symbol an−1 which occurs in the linear approximation of the CPFSK is estimated in order to determine an n-th input data symbol dn on which the CPFSK modulation is based. The n−1-th substitute symbol an−1 is in this case estimated on the basis of the previously determined n−1-th input data symbol {circumflex over (d)}n−1.

Abstract: An algorithm for bit synchronization in a frequency shift keying (FSK) receiver. In the algorithm, a training sequence is received from a transmitter. The training sequence has a plurality of bits. A starting point of a next bit received by the FSK receiver after the training sequence is determined according to peak values of the bits of the training sequence.

Abstract: An algorithm for time recovery in a digital frequency shift keying (FSK) receiver. The receiver correlated a training sequence with predetermined reference signals to generate corresponding correlation values. According to the generated correlation values, status of timing in the FSK receiver is determined. If the FSK receiver is in a timing-inaccurate status, an adjustment for the timing of the FSK receiver is determined in according to the correlation value.

Abstract: A method and apparatus for frequency shift-keying (FSK) demodulation includes processing that begins by generating a charge signal, a data acquisition signal, and a reset signal from an I component and a Q component of an FSK modulated signal. The processing continues by generating a delta frequency signal based on the charge signal, the data acquisition signal, and the reset signal. The delta frequency signal is representative of the frequency difference used within the FSK modulation to indicate a logic 1 and a logic 0. The processing then continues by demodulating the delta frequency signal to recapture a stream of data.

Abstract: Systems and methods are described for providing connectivity to portable electronic devices, such as a cordless telephone, for the purpose of upgrading software features. In a preferred embodiment, portable electronic devices can receive incoming data at the PSTN jack from a personal computer that is also connected to the PSTN via a PSTN modem. In this manner, upgrades can be accomplished without requiring users to disconnect the telephone or to connect additional cables or components. The telephone is temporarily disabled from service only during the downloading of the upgrade software from the personal computer to the telephone. Upgrade software can be received at the personal computer from downloads or from other sources.

Abstract: Tones that are generated by a telephone or PC (such as DTMF tones) and subject to loss or noise during generation or during transmission along a medium are detected and replaced with substantially noise-free and distortionless digital signals. In one embodiment, the replacement of the tones is done in a modem embodied in an Internet telephony Gateway/Terminal, such as in a network access server coupling a time division multiplexed telephone line to a packet-switched network. The replacement of the tones may also be performed in any suitable device that provides an interface between a time division multiplexed transmission medium and a packet switched data network, such as in the modems of a cellular telephone network to Internet network access server.

Abstract: A data demodulating technique for binary data defined by a pulse code modulated signal. The technique involves digitizing the data signal read by a magnetic head from the stripe of a magnetic card. The time interval between peaks in the digitized signal is determined to provide peak interval values. The peak interval values form the basis for determining the end of a character and also by a pattern matching technique against idealized data form the basis for determining the character itself.

Abstract: An apparatus for compensating a channel distortion in a Bluetooth system to process a received signal having access codes comprises a multiplier for multiplying the received signal by a previously obtained channel distortion compensation signal to thereby provide a multiplied signal; a demodulator for demodulating access codes of the multiplied signal to thereby output demodulated received access codes as a demodulated signal; a correlation detection circuit for detecting correlation values between the demodulated received access codes and the access codes of the received signal previously stored therein to detect a start point of the received signal, thereby providing detected access codes having corresponding correlation values greater than a predetermined threshold and providing an enable signal if there are one or more correlation values greater than the predetermined threshold; and a channel distortion compensation circuit for performing a channel distortion compensation based on the detected access code

Abstract: A receiver for frequency shift keyed data transmission implemented using degenerate digital signal processing techniques, whereby complex circuitry can be avoided in favor of low cost, readily manufactuable logic gates.

Abstract: An apparatus and method of detecting signals transmitted via frequency-shift keying techniques. An observation window encompassing a frequency band is defined and searched for received tones, the frequency spacing between received tones is calculated and compared to known FSK modulation techniques to determine whether at least part of a transmission is potentially present. The transmission may be an automatic link establishment signal. A histogram can store data on received tones. The observation window can be shifted to center a potential FSK transmission for parallel modem processing that will attempt to demodulate and decode it.

Abstract: In a method for demodulating an analog FSK signal (FSKin), a current sample (Id(k);Idi) of the downconverted and digital inphase component is multiplied with a previous sample (Qd(k−1);Qdi−1) of the downconverted an digital orthogonal phase component. The product thereof is subtracted from the product obtained by multiplying a current sample of said orthogonal phase component (Qd(k); Qdi) with a previous sample (Id(k−1); Idi−1) of said inphase component. Said current and said previous samples of said inphase and said orthogonal phase components are spaced apart by the digital baseband signal period. In a variant method said current sample and said previous sample of said inphase and orthogonal phase component are spaced apart by an integer fraction (n) of said digital baseband signal period,whereby the steps of said method are repeated, thereby further adding consecutive values of the result Ri).