Abstract: An ultra low-power transmission system for use with a battery-operated device. The ultra-low power transmission system comprises an encoded transmitter and an addressable ultra -low power receiver. The ultra low-power receiver comprises an RF front-end block for receiving and demodulating an incoming RF signal. The RF front-end block includes an amplifier for amplifying the received RF signal and a frequency discriminator for demodulating the amplified RF signal to produce a baseband signal. The amplifier and the frequency discriminator are each comprised of enhancement mode, high-mobility electron transistors (E-HEMTs). The ultra low-power further receiver comprises a correlator for receiving the baseband signal from the frequency discriminator and detecting a codeword therein. The correlator comprises a plurality of switched capacitors for storing samples of the baseband signal. The correlator is operable to couple the plurality of switched capacitors in order to integrate the samples stored thereon.

Abstract: A receiver includes a band-pass filter that limits a passband of an IF (Intermediate Frequency) signal, an FSK detector that detects the IF signal passing through the band-pass filter to generate a detection signal, and a control block that controls a modulation sensitivity of the FSK detector and a pass bandwidth of the band-pass filter, in which the control block controls the modulation sensitivity of the FSK detector according to the pass bandwidth of the band-pass filter.

Abstract: There are provided a transmission and reception device having a function for correcting a data error in a communication path. In the transmission device, a redundant bit addition unit adds a redundant bit to each data bit which has been divided by one bit by a division unit; and an interleaver performs interleave. The transmission device transmits a signal which has been subjected to FM modulation by an FM modulation unit. In the reception device, a symbol decision unit performs a symbol decision at a Nyquist point for a signal which has been FM-demodulated by an FM demodulation unit; a bit conversion unit performs bit conversion according to the result of symbol decision; and a frame recovery unit deletes the redundant bit added by the redundant bit addition unit of the transmission device, from the bit string de-interleaved by a de-interleaver. Thus, it is possible to surely perform an error correction with a simple configuration even when the communication state is not in a preferable environment.

Abstract: The invention relates to a radio receiver for the reception of a data burst which is transmitted by a transmitter, in which case the data burst includes a first section which has been modulated using a first modulation method at the transmitter end, and a second section which is transmitted after the first section and has been modulated using a second modulation method at the transmitter end. The radio receiver has a first reception path for processing of the first section and a second reception path for processing of the second section.

Abstract: There is provided a detector for extracting binary data frequency-modulated on a carrier signal. An axes generator produces M pairs of logic signals, the logic signals of the same pair being in quadrature. The decoder includes M asynchronous logic zero-crossing detectors producing first pulses and second pulses. An up-counter/down-counter has first, second and third values, and when it has the second value, passing to the first value during a first pulse, and passing to the third value during a second pulse, and a binary decoder generates binary data whose state is not modified when the up-counter/down-counter passes from the first value to the second value or from the third value to the second value. No external time base is required and the decoder has a reduced bit error ratio.

Abstract: A frequency shift keying digital signal receiving apparatus includes a detecting portion detecting a new signal on the basis of a signal, from which a correlated ambient noise is filtered out by an adaptive filter, a holding portion holding a first electric power for the signal received before a new signal is detected, a calculating portion calculating a second electric power for the signal received after the new signal is detected, a comparing portion comparing levels of the first and second electric powers, a selector selecting the signal, from which the correlated ambient noise is filtered out, when the first electric power is higher than the second electric power and selecting the signal bypassing the adaptive filter when the first electric power is lower than the second electric power, and a demodulating portion demodulating a desired signal on the basis of the signal selected by the selecting portion.

Abstract: A receiver circuit, application of a first proportional element and a second proportional element of a digital PLL structure, and method for receiving a frequency-shift keyed signal are provided. A phase signal is calculated from an in-phase signal and a quadrature signal. A feedback signal is subtracted from the phase signal to form a difference signal. An output signal is determined from the difference signal by a nonlinear transfer function. The output signal is evaluated with an evaluation circuit. A first signal and a second signal are added to form a summation signal. The first signal is produced by multiplication of the output signal or the difference signal by a first proportionality factor. The second signal is produced by multiplication of the output signal or the first signal or the difference signal by a second proportionality factor, followed by integration, and the feedback signal is produced by integration of the summation signal.

Abstract: A system communicates data and includes an encoder for encoding communications data with a forward error correction code. A data randomizer randomizes the communications data with a random bit sequence and a combining circuit combines the communications data with known symbols into frames. A modulator maps the communications data into minimum shift keying or Gaussian minimum shift keying (MSK or GMSK) symbols based on a specific mapping algorithm to form a communications signal having an MSK or GMSK waveform over which the communications data can be transmitted.

Abstract: An FSK receiver comprising: 1) demodulation circuitry for receiving an incoming FSK signal and generating a baseband signal comprising an amplitude modulated symbol stream, of Logic 0 symbols and Logic 1 symbols having a data rate, R; 2) auto-correlation circuitry for sampling the baseband signal S times during each symbol and generating an auto-correlation function comprising a sample stream of N-bit samples having a data rate, S×R, and having positive-going peaks approximately coinciding with the center of the Logic 1 symbol in a 010 sequence in the baseband signal and negative-going peaks approximately coinciding with the center of the Logic 0 symbols in a 101 sequence in the baseband signal; and 3) decision circuitry for receiving the auto-correlation function and deciding a logic level of a first symbol as a function of: 1) a comparison of a signal level of a center sample of the first symbol and a mean signal level of the auto-correlation function and 2) a comparison of the signal level of the center sa

Abstract: When a first half of a transmission packet is sent by an FSK modulating signal, and a latter half thereof is sent by a PSK modulating signal, a received signal is converted into an intermediate frequency signal by a mixer. The converted intermediate frequency signal is switched to an FSK demodulation unit and a PSK demodulation unit by a received signal changeover switch. A frequency error detection circuit is provided in the FSK demodulation unit to detect a frequency error detection value. A demodulation circuit of a phase locked loop type of the PSK demodulation unit includes a loop filter. The frequency error detection value detected by the frequency error detection circuit is set as an initial value of this loop filter, whereby a time until lockup of a phase locked loop is reduced at the time when reception of a PSK modulating signal is started.

Abstract: A demodulation circuit and method are provided. The demodulation circuit includes a transformation circuit which is configured to transform the received signal into a modified signal representation in which both amplitude-varying information and frequency-varying information are converted to a uniform representation; and a processing circuit which is configured to process the modified signal representation to demodulate the received signal based on the uniform representation. The method includes transforming the signal into a modified signal representation in which both amplitude-varying information and frequency-varying information are converted to a uniform representation; and processing the modified signal representation to demodulate the signal based on the uniform representation.

Abstract: A simplified spread spectrum demodulator uses a frequency detector to demodulate a modulated spread spectrum signal to obtain successive chip values. A correlation unit correlates the successive chip values with fixed sequences of correlation coefficients to generate correlation values. A decision circuit selects one of the correlation values to decide what symbol the spread spectrum signal represents. The correlation coefficients are obtained by applying the same modulation method as used to modulate the spread spectrum signal, and then the same demodulation method as used by the frequency detector, to the sequences of chips representing different symbols. Since synchronous detection is not employed, no carrier recovery circuit is needed.

Abstract: A method and apparatus for a frequency shift keying (FSK) demodulator use a configuration to improve the autocorrelation for better receiver performance. The demodulator uses parallel first and second lines connected to the same input signal, the first line having a delay element to provide an integer-delay of M, the second parallel line having a filter for causing a group delay of ?+M where ? is fractional, and a multiplier for receiving the signals from said first and second lines and generating a resultant signal from which a base band signal can be recovered. The resultant signal is passed through a low pass base band filter to recover the base band signal. ? may have a value of 3.25 and M may be 6. The demodulator may selectively be implemented in caller ID service and in low end modems chosen from a group comprising V.21, Bell 103, V.23 and Bell 202A modems.

Abstract: The present invention relates generally to communication systems, both wired and wireless, employing a continuous phase modulation (“CPM”) waveform with a minimum shift keying (“MSK”) preamble. The present inventive system and method uses information from contiguous Fourier Transforms taken on contiguous data blocks to determine baud rate, phase, frequency offset, and bit timing of the CPM waveform or can be used to determine the frequency of continuous wave waveform. More particularly, the inventive system and method is applicable to the military satellite communications UHF frequency band for deciding whether a signal of interest is.

Abstract: A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. An interpolator circuit is coupled in the feedback path of the phase locked loop circuit. An interpolator control circuit generates an interpolator control word that specifies a variable time delay for the interpolator circuit. The interpolator circuit receives the output clock, and generates the feedback clock by introducing a variable time delay in the output clock in accordance with the interpolator control word. The time variable delay varies the frequency of the output circuit. Embodiments for frequency synthesis circuits that include a spread spectrum frequency clock generator, frequency modulators, and a fixed frequency clock generator circuit are disclosed.

Abstract: A receiver architecture for receiving an FSK signal having a predetermined number of modulation levels includes a selectivity filter (206) for selectively passing a wanted channel and rejecting unwanted channels. The selectivity filter has a filter bandwidth of about one-half the bandwidth of a pre-modulation filter in a transmitter sending the FSK signal. A discriminator (208) is coupled to the selectivity filter for demodulating the signal. A symbol recovery processor (210) is coupled to the discriminator for recovering the symbols through a maximum likelihood sequence estimation (MLSE) technique utilizing N states for each symbol time, wherein N equals the predetermined number of modulation levels, and wherein templates used in the MLSE for symbol transitions are optimized with a bandwidth substantially less than the bandwidth of the pre-modulation filter.

Abstract: A frequency shift keying demodulator robust for frequency offset is provided. The demodulator is used to enable the signal to be received correctly when the frequency offset occurs. A microprocessor of demodulator controls a frequency mixer and a phase difference generator according to the duty cycle of the preamble when receiving the preamble of the demodulated signal. Therefore, the duty cycle of the preamble of the demodulated signal can be close to 50%, and the data from a transmitter is received correctly.

Abstract: A method of detecting an abnormal modulation signal, and a receiver for compensating for an abnormal modulation signal are provided. The method includes demodulating an analog input signal, which has been modulated according to modulation parameters, using demodulation parameters corresponding to the modulation parameters to generate a baseband signal; sampling the baseband signal at a sampling rate; counting a number of samples having an amplitude greater than a threshold level during a detection window; and determining whether the analog input signal has been abnormally modulated, based on the number of samples counted. The receiver includes a baseband signal generator; a sampler; an abnormal modulation detector which counts a number of samples and determines whether the analog input signal has been abnormally modulated; a demodulation parameter modifier which modifies the demodulation parameters according to the determination result.

Abstract: A receiver of a frequency-modulated signal representing a digital signal includes a down conversion unit or frequency translation unit to lower the frequency of the frequency-modulated signal and a digital demodulator to regenerate the digital signal from the lowered-frequency signal. The receiver furthermore includes a counter circuit to determine the number of periods of a reference signal from the frequency translation unit during a period of the lowered-frequency signal. The digital demodulator includes a computer unit to compute the period of the lowered-frequency signal from the number of periods of the reference signal.

Abstract: A communication apparatus including a noise eliminator performing noise reduction processing to cancel a digitized signal received via a receiving antenna, a code decoder, connected to the last stage of the noise eliminator, that decodes the digitized signal that has been subjected to noise reduction processing, a desired-signal detector that limits the noise reduction processing by the noise eliminator when a digitized signal corresponding to a known form of modulation of a desired signal is received by the code decoder, a code interpreter, connected to the last stage of the code decoder, that interprets a decoded signal obtained from decoding by the code decoder, and a controller that disables limitation of the noise reduction processing when a decoded signal not corresponding to a known form of encoding of a desired signal is received by the code interpreter.

Abstract: A wireless voice communication circuit includes an AD converter generating a first digital variable density signal from voice signal, and a first speed change circuit storing the first signal temporally in a first buffer and reading out it at a burst, a sending frame processing circuit generating a sending frame from the first signal, a modulator modulating and sending a frequency carrier in response to the sending frame, a demodulator demodulating a radio frequency signal received and outputting a receiving frame, a receiving frame processing circuit extracting a second digital variable density signal and outputting it together with a writing timing signal, a second speed change circuit writing the second signal in a second buffer temporally and reading out the signal stored in the second buffer at constant speed.

Abstract: Methods and apparatus demodulate and decode a plurality of AM and FM arriving signals, which permit, for example, a utility data-collecting unit to concurrently receive and decode transmitted signals of legacy transmitters as well as more recent FM based transmitters, or signals arriving from hybrid systems configured to transmit both AM and FM.

Abstract: An FSK demodulator system with tunable spectral shaping including a pair of quadri-correlators responsive to first and second quadrature signals, one of the pair deriving first and second signals representative of the frequency deviation of the quadrature signals at even integer multiples of the frequency deviation and for resolving the modulated FSK data represented by the quadrature signals and the other of the pair deriving first and second signals representative of the frequency deviation of the quadrature signals at odd integer multiples of the deviation frequency and for resolving the modulated FSK data represented by the quadrature signals, and a delay control circuit for setting a delay to each of the pair of quadri-correlators to control the first and second signals representative of the frequency deviation of the quadrature signals derived by each of the pair of quadri-correlators and generate a tuned spectral response at both even and odd integer multiples of the frequency deviation.

Abstract: A voltage controlled oscillator (VCO), suitable for use in a frequency shift keying (FSK) system. The VCO device comprises a switching varactor unit, having a first terminal and a second terminal, wherein the switching varactor unit produces a capacitance, according to a frequency-selection voltage. A VCO core has a first output terminal, a second output terminal complementary to the first output terminal, and an input terminal. Wherein, the switching varactor unit is coupled in parallel with the VCO core at the first output terminal and the second output terminal to produce a capacitance effect with respect to the capacitance, so as to adjust a frequency constant ?{square root over (LC)} of the VCO core.

Abstract: A receiver architecture for receiving an FSK signal having a predetermined number of modulation levels includes a selectivity filter (206) for selectively passing a wanted channel and rejecting unwanted channels. The selectivity filter has a filter bandwidth of about one-half the bandwidth of a pre-modulation filter in a transmitter sending the FSK signal. A discriminator (208) is coupled to the selectivity filter for demodulating the signal. A symbol recovery processor (210) is coupled to the discriminator for recovering the symbols through a maximum likelihood sequence estimation (MLSE) technique utilizing N states for each symbol time, wherein N equals the predetermined number of modulation levels, and wherein templates used in the MLSE for symbol transitions are optimized with a bandwidth substantially less than the bandwidth of the pre-modulation filter.

Abstract: A demodulation circuit for demodulating an FSK signal comprising a long bit having a long bit period and a short bit having a short bit period comprises a bit boundary detection section for detecting a bit boundary timing of each bit, and a bit determination section for making determination for each bit such that a particular bit is determined to be a long bit when a threshold time period has passed during a period from a bit boundary timing at a leading end of the bit to a bit boundary timing at a trailing end of the bit, and a particular bit is determined to be a short bit when the threshold time period has not passed during a period from a bit boundary timing at a leading end of the bit to a bit boundary timing at a trailing end of the bit.

Abstract: A method for the decoding of a signal in an interrogation/response type of communications system, the received signal being formed by a video signal and a signal containing the data, wherein the method comprises at least the following steps: 1) transposing the received data signal to an intermediate frequency Fl to obtain the signal Sdh(Fl), Sdb(Fl), 2) converting the intermediate frequency analog signal into a digital signal, 3) sampling the digital signal Sdh(Fl), Sdb(Fl) at a given frequency Fe to obtain the signal Seh, Seb, 4) transmitting the sampled signal Seh, Seb as well as the video signal Svh, Svb to a processing step so as to determine the initially received signal. The method can be applied to the demodulation of MSK, FSK, DPSK type waveforms.

Abstract: Method for iterative multi-stage adaptive filtering of angle modulated passband and baseband signals based on varying of current value of instantaneous frequency to reach powerful noise canceling, by means of calculation and estimation of current value of instantaneous frequency by using demodulation and reversed modulation calculation process to estimate and calculate the current value of the said estimated instantaneous frequency, and applying narrower sub-bandwidth adaptive filtering, which follows in real-time after the said estimated instantaneous frequency, where the said instantaneous frequency is the central filtering frequency of the said sub-bandwidth filter.

Abstract: A demodulator with a phase-adjusting function including a detector including a delay detector delaying an input signal in delaying stages using a first clock obtained by frequency-dividing a sampling-clock at a first-ratio to output a delayed modulated signal, the sampling-clock having a predetermined frequency and a predetermined clock number, and a phase-adjustor which, when the stage number of the delaying stages obtained by dividing the predetermined clock number at the first-ratio does not become an integer, delays the input modulated signal using a second clock, the second clock obtained by frequency-dividing the sampling clock at a second-ratio, a ratio between the second-ratio and the first-ratio corresponding to a shortage in a final delaying stage to produce a phase-adjusted modulated signal that has been adjusted to cause the phase of the input modulated signal to coincide with the phase of the delayed modulated signal.

Abstract: Apparatus and methods for data demodulation in FM-FSK communication systems may include comparing the power spectral density (PSD) of the received frequency spectrum with that of the previously received samples using digital signal processing on a multi-sample message. A narrow band FM-FSK receiver may include a filter configured to pass FM signal components of a predetermined signal band, a memory configured to store the filtered signal component, and a DSP operably connected to the filter and the memory. The DSP may be configured to output a digital signal based upon a comparison of successive DSP calculated frequencies associated with a peak power of a power spectrum density (PSD) of successive samples of the filtered multi-sample message.

Abstract: A communication system including a first device transmitting a modulated signal and a second device receiving the modulated signal. The second device can include a first demodulator and a second demodulator. The first demodulator can receive the modulated signal, produce a first demodulated output, and implement a first demodulation technique. The second demodulator can receive the modulated signal, produce a second demodulated output, and implement a second demodulation technique. The second demodulation technique can differ from the first demodulation technique. The second device can also include an error detection module that can perform bit error detection based on the first demodulated output and the second demodulated output.

Abstract: An FSK demodulator which outputs an enable signal in response to the detection of a data change point in a detected signal of an amplitude associated with the received frequency of an input FSK signal, outputs an average signal of the detected signal for each predetermined time period, acquires the average signal in response to the enable signal to output as an offset signal an average value of M average signals, and subtracts the offset signal from the detected signal to output the resulting signal.

Abstract: A detector includes a binarizer for binarizing the amplitude of an input FSK signal; a 2n-stage shift register having 2n registers for sequentially shifting the FSK signal binarized by the binarizer in response to a clock; and an adder for calculating a sum of a total number of FSK signals having the value of “1” or “0” among FSK signals stored in a first to an n-th register of the 2n-stage shift register and a total number of FSK signals having the value of “0” or “1” among FSK signals stored in an (n+1)th to a 2n-th register.

Abstract: A receiver and a method for receiving a signal including a carrier modulated with a known training sequence is described in which an estimate a carrier frequency offset is obtained from an autocorrelation signal by autocorrelation of the part of the received signal containing a known training sequence. The received signal is compensated with the frequency offset obtained to form a compensated received signal, and a timing reference for the received signal is obtained by cross-correlation of the compensated received signal with a known training sequence.

Abstract: A frequency shift keying (FSK) demodulator includes a band-pass filter, an auto-calibration loop, a phase comparator, and an analog-to-digital converter. The band-pass filter is used for shifting phase of an FSK signal to generate a revised FSK signal. The auto-calibration loop is coupled to the band-pass filter for adjusting a center frequency of the band-pass filter. The first input end of the phase comparator is coupled to an output end of the band-pass filter, and the second input end of the phase comparator is used for receiving the FSK signal. The phase comparator is used for comparing the FSK signal with the revised FSK signal and outputting a comparison result. The analog-to-digital converter is coupled to the phase comparator for converting the results of the phase comparator into digital data. Similarly, a frequency modulation (FM) demodulator includes a band-pass filter, an auto-calibration loop, and a phase comparator.

Abstract: An algorithm for bit synchronization in a frequency shift keying (FSK) receiver. In the algorithm, a training sequence is received from a transmitter. The training sequence has a plurality of bits. A starting point of a next bit received by the FSK receiver after the training sequence is determined according to peak values of the bits of the training sequence.

Abstract: A data slicer for an FSK demodulator employs a peak and valley detector, each of which has a discharge path with selectable decay rates. The faster decay rate for the peak and valley detector outputs is selected when the difference between the current peak and valley voltages exceeds a predetermined percentage of the expected swing of the voltage input and when a packet has not been detected. When a packet is detected, a slower decay rate is selected. In this mode, the faster decay rate permits faster acquisition of packet data in the presence of DC offset, as it permits the data slicer to converge on an appropriate switching point more quickly.

Abstract: A multivalued FSK modulation system is provided in which when data to be transmitted is multivalued and transmitted/received, the detection level is different every symbol. When a two-valued signal is transmitted as one symbol, data (11), (01), (00) and (10) are previously set to be, for example, a shift of ?6, a shift of +6, a shift of +2, and a shift of ?2, respectively. When data to be input next is (00), mapping is performed so as to provide a sign weight of +2 from the sign weight at the position of current data. When the data to be input next is (10), mapping is performed so as to provide a sign weight of ?2 from the position of the current sign weight. Thus, even if data of the same level is input, signals can be always detected in different levels, so that the sign detection point is not specified erroneously.

Abstract: The radio demodulation circuit of the present invention demodulates a multi-valued FSK signal with a digital demodulator, performs threshold value judgment on the demodulated output of the digital demodulator with a data judging device, and keeps the threshold value obtained by the data judging device in a threshold value holding device.

Abstract: A frequency-shift keying (FSK) signal detector includes a binarizing circuit for receiving an FSK signal and expressing amplitude of the FSK signal in binary; a correlator for receiving the FSK signal expressed in binary and acquiring a correlation of the FSK signal; and an arithmetic unit for performing an arithmetic operation on the output of the correlator to detect and output the FSK signal. The correlator includes plural stages of shift register for sequentially shifting the FSK signal in response to a clock signal; a correlation filter for obtaining the correlation by a correlation signal sequence and a window function signal sequence which obtain a correlation value at one of two frequency components generated by frequency-shift keying; and another correlation filter for obtaining the correlation by a correlation signal sequence and a window function signal sequence which obtain a correlation value at the other of the two frequency components.

Abstract: A method for reducing the cost of demand control ventilation applications deploys wireless CO2 sensors inclusive of relative humidity and temperature throughout an indoor space without the need for wiring while utilizing the license-free 902-908 MHz ISM band by use of a Sequential Transmission Asynchronous Reception System (“STARS”) that is software controlled.

Abstract: A method for synchronizing a receiver to a stream of transmitted symbols that includes a known synchronization word. The method includes receiving a signal in which the symbols, including the synchronization word, are encoded by frequency shift keying. The signal is sampled and digitized to generate a sequence of input samples. For each of the input samples, a phase difference is determined relative to a preceding input sample in the sequence, thereby generating a sequence of differential samples corresponding respectively to the input samples. The differential samples are then matched to the synchronization word.

Abstract: An FSK signal modulator is provided in a transmitter which receives desired information to be transmitted on its input and which modulates the information to be transmitted to transmit a binary FSK signal. A counter counts a value of addition with the value of addition modified in accordance with a predetermined rule, depending on the value specified by the information to be transmitted, and for holding the counted value. The count value is determined by a threshold value decision circuit with respect to a threshold value. The result from the decision is output in the form of binary FSK signal. An FSK signal modulator will be provided which is simplified in circuit constitution.

Abstract: The invention relates to a method and device for estimating an estimated value (U2max) dependent on the maximum (Umax) of a single-frequency signal sampled via a succession of sampled values (d(n)), wherein each of a predetermined number (N) of sampled values (d(n)) is squared and the predetermined number (N) of squared sampled values (d2(n)) is summated.

Abstract: Data of the packet header is digitalized by a slicer circuit of a floating slice level mode, which follows DC voltage fluctuation, and packet data other than the packet header is digitalized by a slicer circuit of a fixed slice level mode, which does not follow DC voltage fluctuation. A default slice level of the fixed slice level mode is created by using demodulated data in a packet header section so as to accurately carry out switching of slicing methods. Obtained is a data slicer capable of accurately carrying out digitalization with respect to a signal, which is demodulated after being received.

Abstract: The invention provides a method and apparatus for achieving timing synchronization during signal acquisition and for achieving frequency synchronization in a digital communication receiver after signal acquisition. The invention operates by performing multiple correlations of a received signal, each correlation performed over an symbol interval and correlating the received signal in the symbol interval with a sinusoid of an expected frequency. The correlations are combined to determine a peak and energy, and if the peak to energy ratio is above a threshold, the symbol timing and frequency offset is estimated.

Abstract: An RFID reader accessible thorough a personal computer and includes a PC card interface and a controller both operating according to clock signals from a crystal oscillator. The RFID reader further includes a linearized power amplifier modulator in a transmit path, a receive chain capable of demodulating EPCglobal Class_1 and Class_0 signals from RFID tags, and an integrated switching device for selecting one of a plurality of antenna for transmitting or receiving RF signals.

Abstract: An OFDM receiver detects FSK symbols in a communications network. An FFT has an input connected to receive temporal samples of a received, frequency-hopped FSK signal. Outputs of the FFT represent the FSK signal in a frequency domain. The outputs are grouped according to predetermined frequencies assigned by a transmitter of the FSK signal. An energy for each group of outputs is determined, and the energies of each group are then compared to recover a data stream from the FSK signal.

Abstract: A frequency shift key decoding apparatus, having a frequency divider, a signal frequency splitter, and a demodulator. The signal frequency splitter has a frequency synthesizer, (n?1) first mixers, n second mixers, and n filters, where n is an integer equal to or larger than 2. The present invention can be applied to a multi-function wireless receiver that supports multiple peripherals. Since a plurality of local carrier signals is generated by only (n?1) mixers, the frequency of the local carrier signals can be randomly changed. As the mixers occupy a very small area of the integrated circuit chip, the fabrication cost is low. Further, since the mixers are easily implemented using a digital circuit, the frequency shift key decoding apparatus, and even the whole wireless receiver can be implemented in a single chip.

Abstract: A digital demodulator employing a digital differential detection mechanism based on extracting phase differences directly from the I and Q signals after downconversion to zero-IF and image rejection are performed. The phase of the input I and Q signals is determined using the principle that the phase is equivalent to arctan ( Q I ) . A lookup table stores the values of the arctan function preferably in a reduced size format. The size of the lookup table can be reduced significantly by storing arctan values for the first quadrant only (i.e. 0 to 90°) and taking advantage of the fact that the phase values for the other three quadrants can be derived from those of the first with some correction applied depending on the signs of the I and Q input samples. Phase extraction logic is provided that is operative to map the phase into the entire 0 to 360° range of phase values (i.e. ?? to +? radians) based on the signs of the I and Q signals.