Abstract: A digital broadcast receiver for determining the actual transmission mode of a Digital Audio Broadcast (DAB) signal with a delay circuit for delaying a received DAB signal is provided. With a correlation circuit for correlating a delay output of the delay circuit with the received DAB signal a moving average circuit for calculating a moving average of a correlation output of the correlation circuit. A transmission mode is assumed to be one of a plurality of transmission modes. The delay time of the delay circuit is set at a time corresponding to a symbol time length of the assumed transmission mode. The number of times that the output of the moving average circuit exceeds a prescribed value is counted. Based on counting results, the actual transmission mode is identified based on the maximum number of times that the output of the moving average circuit exceeds the prescribed value.

Abstract: A device for detecting a predetermined waveform in a received signal and synchronizing the detected waveform to the predetermined waveform is disclosed. The device includes a memory element for storing a reference set of encoded values. The reference set representing an encoded version of the predetermined waveform. An encoder is used to PCM encode the signal to obtain sets of encoded values representing the received signal. A processor calculates the statistical correlation coefficient of the reference set and the signal sets. The processor then determines the maximum statistical correlation coefficient. The predetermined waveform is detected in the signal if the maximum statistical correlation coefficient is greater than or equal to a predetermined threshold value. The device provides a compact, inexpensive, and fast method for detecting a known reference waveform in a received signal.

Abstract: Interface apparatus for interfacing data to a plurality of different clock domains where the clock signals in the different domains are phase locked together and respective clock signals have different frequencies includes a plurality of cascade connected first and second latches coupled between respective clock domains. One of the latches is a clocked Data Latch and the other is a clocked and Enabled Data Latch. A timing generator provides respective domain clock signals, wherein a domain clock signal of a domain providing a data signal is applied to the clock input connection of the first latch of a respective cascade connected set of latches and a domain clock signal of a domain receiving said data signal is applied to the second latch. The timing generator also provides a common Enable Signal phase locked to the domain clocked signals. The common Enable Signal is applied to the enable input terminal of one of the latches of each set of cascade connected latches.

Abstract: After a pseudo synchronizing information is detected and a synchronization is lost, an arithmetic operation unit adds a random number outputted from a random number generator to a frame length information calculated. The detection of a synchronizing information is again executed in a stream counter to a bit stream of a plurality of continuous transmission data, from a bit located in delay for the bit of output information being a calculation result by the arithmetic operation unit. The frame synchronous circuit thus constructed achieves a synchronization setup securely in a high speed, if a transmission data containing a pseudo synchronizing information is transmitted.

Abstract: A timing recovery apparatus for use in a receiver in a multicarrier transmission system is provided. The apparatus includes a receive signal buffer, a pointer register containing an address to a location within the receive signal buffer, a time to frequency domain signal converter, a digital filter, and a control circuit. The signal converter accepts data from the receive signal buffer. The samples that are fed into the converter are determined by an address stored in the pointer register. The digital filter is connected to the converter, and is essentially a bank of single-tap filters. One of the converter outputs corresponds to a pilot tone, and thus the digital filter provides a filtered pilot tone. The phase of the pilot is also examined, preferably by examining the filter tap corresponding to the pilot. The control circuit accepts the pilot phase signal and responsively updates the pointer register.

Abstract: A method of synchronizing a clock signal to a data signal, comprising the steps of (A) detecting a first edge of the data signal, (B) determining a first value indicating a position of the first edge, (C) adding the first value to a second value, wherein the second value indicates a position of a second edge of the data signal and (D) adjusting the clock signal based on the result of step (C).

Abstract: A method for improving the performance of a random access communications system in a variable radio environment is disclosed, whereby at least one valid set of burst signatures is used for transmission by one or more mobile stations. Each set includes at least one signature with a different signature-length than the signatures in other sets. The different signature-lengths can be optimized for the operational environments involved (e.g., longer signatures for slower-moving mobile stations, and shorter signatures for high-speed mobile stations). Alternatively, at least one differentially-encoded signature is used for random access transmissions, in order to reduce the radio channel's sensitivity to large doppler spreads and frequency errors.

Abstract: A method of estimating SNR for a plurality of carriers modulated with digital information, wherein the digital information includes data baud and training baud, comprising the steps of: receiving the plurality of carriers; determining a first SNR for the data baud; determining a second SNR for the training baud; comparing at least one of the first and second SNRs to predetermined selection criteria; and selecting one of the first and said second SNRs based on the comparison step. In the preferred embodiment, the carriers are processed to produce an equalizer output for each of the carriers, and the equalizer output is processed to produce a symbol decision for each of the carriers. The equalizer output is subtracted from the symbol decision when a data baud is received to produce a first difference value, and the first difference value is squared to produce a first signal to noise estimate.

Abstract: A sleep control system and method are provided that permit a reference clock and the direct sequence spread spectrum (DSSS) modem in a mobile station receiver to be turned off and turned back on at arbitrary points in time while still maintaining accurate base station system time. Accurate timing is made possible through a number of techniques including precise initial calibration using a rising edge/falling edge averaging system, determining the sleep clock and reference clock frequencies, and the determination of the frequency drift of the sleep clock that occurred during the previous sleep interval.

Abstract: A transmitter transmits, and a receiver receives, a data frame is transmitted into an 8 MHZ channel. The data frame contains a plurality of data segments, where each of the data segments contain DS symbols. The DS symbols include data symbols, priming symbols, and segment synchronization symbols. The transmitter trellis encodes the data symbols, priming symbols, and segment synchronization symbols. The receiver trellis decodes the 10 data symbols, priming symbols, and segment synchronization symbols. The data frame also contains a mode control ID which the receiver uses in trellis decoding the data symbols, priming symbols, and segment synchronization symbols.

Abstract: A digital television signal receiver includes a bin amplitude comparator for symbol decoding and match filtering to recover data synchronizing information from selected bin amplitude comparator responses generated during data slicing. The bin amplitude comparator concurrently supplies bin occupancy results for an amplitude slice including a value +S and for an amplitude slice including a value −S, which values +S and −S define the positive and negative excursions respectively of a binary data synchronization signal, current bin occupancy results being grouped together as two-parallel-bit serial input signal to a shift register clocked at symbol rate. Match filtering to detect data segment synchronization symbol code sequences is provided in accordance with an aspect of the invention by an AND gate supplied bits from selected storage locations in the shift register as wired input signals.

Abstract: A modem system includes a programmable synchronization signal format that can be configured at a first modem in response to a request received from a second modem. The synchronization signal format may define a number of parameters of the synchronization signal, such as the sign pattern for symbols transmitted by the first modem during a training sequence. The specific parameters of the synchronization signal format may be associated with the design and operation of the second modem. For example, the particular timing recovery and automatic gain control schemes used by the receiver portion of the second modem may be optimally initialized with a synchronization signal having a specific length, amplitude, or spectrum. In one embodiment, a synchronization signal is configured to convey a single frequency tone for use during a synchronization routine. The modem system may also employ similar techniques to generate, transmit, and analyze a programmable line impairment learning signal.

Abstract: An apparatus and method for detecting a vertical synchronizing signal in a digital TV receiver using a VSB system is disclosed. The present invention includes a vertical obtaining the correlation between a received signal and a previously set vertical synchronizing signal, detecting the position of a symbol having a maximum correlation in every field to output the detected position, and checking the reliability of the output of the maximum value position detector.

Abstract: A clock smoothing circuit generates a smoothed clock signal from a gapped clock signal having unevenly spaced pulses separated by gaps that result from the removal of data bits and from a reference clock signal having evenly spaced pulses that create a predetermined reference frequency. A smoothing element is coupled to the input elements to receive the gapped clock signal and the reference clock signal. In one embodiment, the smoothing element generates a smoothed clock signal having one pulse for each of the pulses in the gapped clock signal and having a frequency that is greater than one-half of the predetermined reference frequency. Each pulse in the smoothed clock signal is synchronized with a pulse in the reference clock signal.

Abstract: An orthogonal frequency division multiplexed wideband communication system provides improved time and frequency synchronization by inserting an unevenly spaced pilot sequence within the constellation data. A receive correlates the received data using the unevenly spaced pilot sequence. The pilot sequence is generated with a maximum length pseudo random noise code and inserted into frequency bins having prime numbers.

Abstract: A data sync signal detecting device for detecting a sync signal having sync signal detection errors. The detecting device applies the output data of a most-likelihood decoder to shift register bit cells. The data is sequentially shifted and held in the bit cells of the shift register. The bit cell outputs are separated into odd-numbered and even-numbered bit string and applied to first and second pattern matching circuits. The odd-numbered bit string is matched with “01001” by a first pattern matching circuit. The even-numbered bit string is matched with “01011” by a second pattern matching circuit. First and second matching results are applied to a coincidence number adder/majority decision circuit. When coincidence occurs, the matching result is “1”, and when non-coincidence occurs, the matching result is “0”.

Abstract: Burst transmissions in a burst-type communication system include a preamble synchronization sequence which allows detection and synchronization a burst transmission while at the same time providing information to a receiver, for example, on the subsequent burst payload data. Each burst transmission includes a preamble synchronization sequence which is one of a plurality of predetermined allowed preamble sequences in the system, according to the information desired to be transmitted. The system may also use differential encoding and decoding to eliminate the effects of frequency uncertainty. In that case, the allowed preamble sequences may be such that, after differential decoding, they differ from one another only by a polarity inversion such that a single matched filter may be used to detect two preamble sequences.

Abstract: A digital television signal receiver includes a bin amplitude comparator for symbol decoding and match filtering to recover data synchronizing information from selected bin amplitude comparator responses generated during data slicing. The bin amplitude comparator concurrently supplies bin occupancy results for an amplitude slice including a value +S and for an amplitude slice including a value −S, which values +S and −S define the positive and negative excursions respectively of a binary data synchronization signal, current bin occupancy results being grouped together as two-parallel-bit serial input signal to a shift register clocked at symbol rate. Match filtering to detect data segment synchronization symbol code sequences is provided in accordance with an aspect of the invention by an AND gate supplied bits from selected storage locations in the shift register as wired input signals.

Abstract: A method and apparatus for synchronization of an audio/visual bitstream is transmitted by an encoder and received by a decoder by employing duplication or elimination of audio samples and video pixels. The invention enables clock synchronization between the encoder and a decoder with an unregulated clock oscillator so as to control the data reader by skipping ahead (eliminating a data element) or to pause (duplicating a data element) depending on whether the encoder clock is faster or slower than the decoder clock.

Abstract: In a multi-directional orthogonal frequency division modulation (OFDM) communication system, for example, on a digital subscriber line, an uplink channel is provided by a first group of the OFDM sub-channels (sub-carriers), and a downlink channel is provided by a second group of the OFDM sub-channels (sub-carriers). In one aspect, communication efficiency is improved by controlling the relative number of sub-channels allocated to each group, and hence controlling the capacity of the channels dynamically. Preferably, the relative capacities are controlled in response to demand for channel capacity. In another aspect, the orthogonality of the sub-carriers generated by different transmitters is improved by providing a frequency and/or time synchronizing signal for providing reference frequency and timing.

Abstract: A processor (306) is assigned a predetermined synchronization signal for use in communicating in a wireless communication system (100) The processor calculates (402) a total energy of the predetermined synchronization signal. A receiver front end (302) coupled to the processor receives (404) a signal which may include the predetermined synchronization signal, and calculates (406) a plurality of cross-correlation values between the received signal and the predetermined synchronization signal to locate a correlation peak. The processor also calculates (408) a plurality of detection metrics as a function of the plurality of cross-correlation values, the received signal, and the predetermined synchronization signal.

Abstract: A scalable pattern methodology defining positions of synchronization symbols, pilot symbols and data symbols for various numbers of sub-channels in a multi-carrier communication system. A base pattern (510) is defined identifying positions of data symbols, synchronization symbols and pilot symbols for a first number of sub-channels corresponding to a first bandwidth. The base pattern is replicated or scaled to form an expanded pattern (512, 514) identifying positions of data symbols, synchronization symbols and pilot symbols for an expanded number (M) of sub-channels corresponding to a second bandwidth. The pattern methodology may be implemented by a transmitter (100) having subdivided an original information signal into M bit streams and having encoded each of the M bit streams to 16QAM symbols to form M symbol streams, by inserting synchronization and pilot symbols into each of the M symbol streams at positions determined by the expanded pattern.

Abstract: A receiver in a communications system is operated by receiving a radio communications signal transmitted by a station of the communications system and generating a correlation output representing a correlation of the received radio communications signal and a subsequence of a modulation sequence that is selected based on a correlation between the selected subsequence and the modulation sequence. The receiver is then synchronized based on the generated correlation output. The selected subsequence preferably has an optimal out-of-phase correlation with the modulation sequence. According to an aspect of the present invention, the selected subsequence has a minimum out of phase correlation with the modulation sequence in comparison to other subsequences of the modulation sequence. For example, the selected subsequence may have a “minimum maximum” out-of-phase correlation value, a “minimum aggregate” out-of-phase correlation metric, or a combination thereof.

Abstract: A waveform to be transmitted as a burst within a channel that is used for the synchronization of unsynchronized wireless communications terminals in a wireless communications system, and a method of synchronization involving the waveform, that consists of a composite waveform. The composite waveform comprises two or more component waveforms, wherein each of the two or more component waveforms has a known frequency variation throughout the burst. The composite waveform has a composite bandwidth on an order of an available channel bandwidth and each of said two or more component waveforms have a component bandwidth on the order of the available channel bandwidth. Furthermore, a range of values for the differences between the instantaneous frequencies of two of said two or more component waveforms is on an order of twice of said available channel bandwidth.

Abstract: A method is disclosed for receiving a transmitted signal in a communication system employing CDMA techniques wherein the transmitted signal includes a plurality of short codes, each of which is transmitted repetitively over a fixed period of time and where the received signal has CW interference in addition to the transmitted signal. The method includes using a Sequential Ratio Probability Test (SPRT) for detecting the presence of the short code in a plurality of time phases of the received signal by calculating a likelihood ratio for each phase. A likelihood ratio is a comparison of the signal's Probability Distribution Function (PDF) with a background noise PDF. The background noise PDF is calculated by combining in the RAKE the current short code with the input signal.

Abstract: An arrangement for capturing data from a data stream of a predetermined data transfer rate by means of a flip-flop, comprises a symmetrical multi-phase clock generator that is adapted to be locked to a reference clock which in turn is adapted to generate a reference clock signal at the data transfer rate or at a fraction thereof, the multi-phase clock generator being adapted to generate n clock signals mutually shifted in phase 360°/n from each other, and a selector that is connected to the clock generator to receive the n clock signals, the selector being adapted to select one of these n clock signals as the system clock signal in response to a control signal from a clock phase counter, the clock phase counter being controlled to count up or down in response to the phase of the system clock signal when a predetermined number of data transitions have occurred in the data stream, said flip-flop being adapted to be controlled by the opposite phase of the system clock signal to capture said data from the dat

Abstract: Methods and systems are provided which utilize pilots in an information sequence to periodically retrain a channel estimator. Thus, a channel tracker may be synchronized using a synchronization sequence and then periodically retrained using known pilot symbols. Furthermore, the utilization of pilots may allow for the detection of errors in previous channel estimates. When errors are detected, a new channel estimate may be used based on the retraining using the pilot symbols and, optionally, previous errors in symbol estimation may be corrected. Thus, by retraining based on pilot symbols, the propagation of errors may be reduced.

Abstract: A method is provided for identifying a training baud in a digital audio broadcasting signal. The method includes the steps of receiving a plurality of carrier signals modulated by a plurality of data baud, wherein the data baud include normal baud and training baud. The data baud received on the carriers are compared with predetermined data signals to produce a plurality of difference signals. The difference signals are then used to produce a plurality of distance signals, which are combined to produce group distance signals. One of the group distance signals is selected and used to determine if the data baud corresponding to the selected group distance signal is a training baud or a normal baud. This determination is performed by storing successive selected group distance signals until at least one training baud has been received, and using the stored group distance signals to determine normal/training synchronization.

Abstract: A method identifies a pulse sequence having known values and a known length in a signal. According to this method, the mathematical sign of the phase difference between samples of the signal is used to estimate whether the transmitted pulse is a 1 or a 0. Undersampling, carried out to a selectable extent, produces a relatively insensitive response to adjacent channel interference. The sum of the pulses in a window which is proportional to the length of the pulse sequence and to the extent of the undersampling is determined, with the pulse sequence being regarded as being identified at the point in time at which the sum of the pulses in this search window exceeds a threshold value.

Abstract: A digital data transmission system for transmitting digital data, a frame pulse signal, and a clock using a required minimum number of signal lines and with a simple circuit structure is provided. A signal separation circuit (46) that receives a multiple clock (CKFP) which is a frame pulse signal (FP) multiplexed with a clock (CK) includes a clock recovery circuit (47) for reproducing a recovered clock (RCK) by synchronization with the multiple clock (CKFP) using a synchronization loop, and a frame pulse signal separation circuit (48) for separating a recovered frame pulse signal (RFP) from the multiple clock (CKFP) on the basis of the recovered clock (RCK).

Abstract: A pulse train with known values and a known length contained in a signal is identified. The mathematical sign of the phase difference between successive samples of the signal is used to assess whether the transmitted pulse is a 1 or a 0, and with the sum of the pulses being determined in a window which is proportional to the length of the pulse train. The pulse train is considered as being identified at the time when the sum of the pulses in the search window exceeds a given threshold value.

Abstract: A microcontroller includes a direct memory access unit that compresses and decompresses data and transfers from one block of memory to another. Specifically, word size data can be read, one byte discarded, and stored as consecutive, byte size data. This can be used in conjunction with an extended read and extended write asynchronous serial port that stores status information along with data. Once the status information is processed, the status is stripped by performing the “compressive” DMA.

Abstract: An apparatus for generating a precision frequency includes a receiver that tracks a CDMA pilot signal and extracts frequency and phase information. This information is then used by a processor to control a precision oscillator. The precision oscillator generates a precise frequency based on the CDMA pilot signal. Time of day information is also extracted by the receiver and processor.

Abstract: A multi-carrier transmission system, for example a DMT system. Channel information is transmitted between two transceivers using a plurality of subcarriers. Each subcarrier, or symbol, has a parameter associated with it. The transceivers are adapted to transmit the channel information as a sequence of n groups in which each of the n groups contains information concerning the number of adjacent subcarriers which have the same value as the parameter, together with the actual value of the parameter. The parameter which may have a plurality of discrete values, may be a bit-loading value, or a QAM constellation identifier.

Abstract: Control information is processed in synchronism with audio and video data according to a protocol such as RTP (Real-time Transfer Protocol). In one embodiment, a payload handler receives incoming data packets and forwards them to either a data control filter or an audio packet handler. The data control filter determines whether the data payload contains video data or control information and forwards video data to a video data packet handler and data control information to a data handler. The data control information can include an action identifier field (e.g., containing a “display” command) and a data object field (e.g., identifying a file location in a memory) so that the data control filter can display the identified file with the presentation of the other video and audio data.

Abstract: A method and apparatus utilizing a data processing system are disclosed for multi-level data communication providing self-clocking. A first digital signal is input which includes a series of digital bits. One of a plurality of output levels is associated with each group of data bits for each of the plurality of the digital bits included within the first digital signal. A particular output level is associated with a clock output level. An output signal is generate which includes a transmission of the output level for each of the groups of digital bits and includes multiple transmissions of the clock output level, where a clock output level is transmitted after each transmission of an output level for each of the groups of digital bits.

Abstract: A communication system and method for transmitting relatively short data messages in the communication system. A dedicated frequency is sequentially switched into each of a plurality of satellite beams or traffic channels to transmit data messages at an increased power level to provide an increased signal margin. The increased power level of the dedicated frequency can be combined with coding and bit and message repetition to further increase the signal margin.

Abstract: A data processing device uses a portion of a random access memory as an output buffer for holding a frame of PCM sample data which is being output after being processed by a processing unit within the processing device. Fine grained synchronization between a reference clock and a stream of PCM data frames is provided by transferring only a portion of selected frame of PCM sample data PCM(n+1), in response to a time difference 971. A breakpoint address is determined to delineate the portion of the selected frame that is to be transferred. A sorted list of the addresses of the discontinuities is maintained in breakpoint queue. Since the buffer is managed in a FIFO manner, a single breakpoint register is sufficient to monitor addresses as they are provided by an address register for accessing the random access memory. When a breakpoint is detected, the breakpoint queue and the breakpoint register is updated by an update task 802.

Abstract: A receiver receives a received signal containing a pilot up chirp and a pilot down chirp. The pilot up chirp has a frequency which increases from a time reference zero to a time reference tN, and the pilot down chirp has a frequency which decreases from the time reference tN to a time reference 2ttN. A sampler of the receiver is arranged to sample the received signal. A detector is arranged to correlate the received signal samples with a reference up chirp and a reference down chirp. The reference up chirp has a varying frequency substantially matching the pilot up chirp, and the reference down chirp has a varying frequency substantially matching the pilot down chirp. A sample adjuster is arranged to synchronize the received signal samples in response to the detector.

Abstract: A clock recovery circuit enables a time for obtaining synchronized state of one pair of gate voltage-controlled oscillator to be shortened in a phase locked loop (PLL). In the clock recovery circuit, data is inputted to a pulse-duration generating circuit, before generating pulse width less than ¼ minimum data cycle from H of pulse, L of pulse, or both edges of H and L, thus the pulse is outputted both to a latched-circuit and a synchronous delay circuit. The synchronous delay circuit causes a delay time in proportion to data cycle to be generated at both edges of pulse or edge of two pulses, thus the delay time is maintained. An output pulse from a delay circuit is outputted both to a delay circuit and a latched-circuit by way of clock from the pulse synthesis circuit. The latched-circuit causes the data as an input to be latched by the clock from the pulse synthesis circuit, thus outputting regenerative data in company with the clock.

Abstract: A road side communication equipment is provided crossing over lanes of an expressway, so that a communication processing for toll collection is executed between the road side equipment and an on-board equipment passing a communication area. The road side equipment sends signals using a 32-bit synchronizing signal for the start slot of each frame and a 16-bit synchronizing signal for subsequent slots of the frame. The on-board equipment receives this to perform signal receiving processing. The received communication signals are then digital-demodulated and entered to a shift register, so that the bit pattern is compared in two comparators to detect the synchronizing signal. According to the output from AND circuits, the synchronizing signal is distinguished from the synchronizing signal to determine the received data and receive subsequent data.

Abstract: The base stations of a wireless multi-cell telecommunication system receive a time signal radio message sent by a time transmitter, with which the base station-specific function executions of the base stations oriented to a telecommunication standard for the wireless telecommunication in the multi-cell telecommunication system can be controlled synchronized in time.

Abstract: A data sync signal detecting device with a simple configuration for detecting a sync signal having a few sync signal detection errors is disclosed. The detecting device is configured such that the output data of a most-likelihood decoder constituting a data discriminator is applied to a shift register bit cell and sequentially shifted and held in the bit cells of shift registers. The outputs of these bit cells are separated into an odd-numbered bit string and an even-numbered bit string and applied to first and second pattern matching circuits. The odd-numbered bit string is matched with “01001” as a predetermined sync signal pattern by a first pattern matching circuit which produces a first matching result. The even-numbered bit string is matched with “01011” as a predetermined sync signal pattern by a second pattern matching circuit which produces a second matching result. The first and second matching results are applied to a coincidence number adder/majority decision circuit.

Abstract: A method and apparatus for detecting framing alignment sequence within a received bit stream. A stream state memory is assigned for each possible location of the framing alignment sequence. Bits of a particular stream are loaded into the respective stream state memory. If the bits do not match an acceptable subsequence of the framing alignment sequence then the stream is eliminated from consideration by writing an exile state to the respective stream state memory. Then subsequently received bits are used to transition either to the next state if the next bit is a correct bit in the framing alignment sequence, or to the exile state if the bit is not the correct bit. After all of the streams have been exiled but one, the remaining stream may contain the framing alignment sequence. However, it may be that a certain number of correctly received bits are required to declare in-frame with sufficient certainty in which case incoming bits will continue to be processed until this is satisfied.

Abstract: A data transmission apparatus using a digital modulation system wherein a transmitting side inserts a group of predetermined synchronization symbols into a transmission signal at predetermined intervals to be transmitted. A receiving side calculates an electric power value of a received transmission signal. When a no-signal period (null section) in the synchronization symbol group is to be detected and decided from a magnitude of the received signal electric power value, a threshold for reference of decision for detecting the null section is calculated on the basis of an average electric power value for a predetermined period in the received signal electric power value and the threshold calculated in accordance with the received signal level of the transmission signal is used to detect synchronization stably.

Abstract: A subscriber unit of a time division multiple access (TDMA) radiotelephone system is, from a power consumption standpoint, reconfigured in each time slot of a TDMA frame to a power consumption tessellation in which subscriber unit circuit components not needed for communication signal processing in that time slot are powered down, and other components are powered up. Some circuit components are powered down by switching their power supply circuits. In order to minimize the extent of circuitry that must be provided to distribute power consumption control signals, other techniques (which utilize circuitry provided for other purposes), such as clock frequency control or power down commands, also are utilized to modify controlled circuit component power consumption without actually controlling power supply circuits.

Abstract: A receiver for processing a VSB modulated signal containing terrestrial broadcast high definition television information and a pilot component includes an input analog-to-digital converter (19) for producing a datastream which is oversampled at twice the received symbol rate, and a digital demodulator (22; FIG. 3) with a data reduction network (330, 332) in a phase control loop. A segment sync detector (24; FIGS. 4, 5) uses an abbreviated correlation reference pattern to recover a twice symbol rate sampling clock for the digital converter (19). A DC offset associated with the pilot component is removed (26; FIG. 6) from the demodulated signal before it is applied to an NTSC interference detection network (30; FIG. 7). The interference detection network includes a comb filter network (710, 718) responsive to a twice symbol rate sampled data datastream, and exhibits a sample delay dimensioned to avoid aliasing in the combed frequency spectrum (FIG.

Abstract: In a communication system including at least one transmitter and at least one receiver, a frequency synchronization signal transmitted from the transmitter to the receiver is detected. An in-phase component of a signal received by the receiver is delayed, and the delayed in-phase component is multiplied by a quadrature component of the received signal. The steps of delaying and multiplying are repeated for a predetermined number of samples of the received signal to produce an estimated cross-correlation value. A determination is made whether the estimated cross-correlation value is at least as great as a predetermined threshold, indicating that the transmitted signal is a frequency synchronization signal.

Abstract: In a synchronizing system, a CRC bit end judging circuit judges an end of a CRC bit of the demodulated signal from the demodulating circuit to produce a CRC bit end signal. A RSSI detecting circuit detects a RSSI level of the received signal to produce a RSSI level signal. An edge detecting circuit compares the RSSI level with a predetermined threshold level to produce a level compared result signal when the RSSI level is greater than the predetermined threshold level. The edge detecting circuit masks, in a predetermined time interval, the level compared result signal in response to both of the CRC bit end signal and the level compared result signal. The edge detecting circuit produces a trigger signal in response to the level compared result signal after the predetermined time interval. A bit synchronous circuit produces, in response to the trigger signal, the bit synchronous signal.

Abstract: A technique has been devised which may be used to synchronize a receiver clock to a transmitter clock at either end of a transmission network having jitter intrinsic therein. The technique is characterized by a modified least squares linear regressive approach which takes advantage of assumptions particular to such transmission networks. The technique finds advantages in comparison to commonly used phase-locked loop techniques which have long startup phase delays where clocks are not in sync. The modified least squares linear regressive technique of the invention provides excellent isolation of jitter and other timing variations while simultaneously providing for quick startup.