Plurality Of Synchronization Words Patents (Class 375/366)
  • Patent number: 6658072
    Abstract: In the transmission device, a synchronization pattern made by arranging a predetermined basic pattern consisting of a combination of a predetermined number of symbols and a reversal basic pattern made by reversing a polarity of each symbol of the basic pattern, in the order according to a reversal pattern, is generated, and transmission data obtained by adding thus obtained synchronization pattern at predetermined timing is transmitted. In the reception device, the basic pattern and reversal basic pattern in the synchronization pattern are correlated with each other by a matched filter (11) corresponding to the basic pattern, and the correlation of the reversal pattern which appears in a signal obtained as a result, is taken by a matched filter consisting of delay portions (12), multipliers (13) and an adder (14).
    Type: Grant
    Filed: April 25, 2000
    Date of Patent: December 2, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yutaka Asanuma
  • Patent number: 6643341
    Abstract: A method employing multisignal encoded start pulses and end pulses for data transmission by use of radio waves, carries out encoding so that a very large number of kinds of patterns (not less than 1014 kinds are possible) can be effected with one frequency. In the binary system, encoding needs a large number of signal pulses and high frequency, and the frequency of the carrier wave becomes very high also. The multisignal method of this invention makes it possible to reduce the encoding bits and the carrier wave frequency by using level sensing and width comparison techniques. This method also removes noise owing to its level sensing and width comparison techniques which have not been used in conventional digital communication systems. Therefore, the reception of erroneous information, the occurrence of unclear audio-visual images, and noise trouble are prevented in the use of radio waves.
    Type: Grant
    Filed: October 22, 1999
    Date of Patent: November 4, 2003
    Inventor: Hirosi Fukuda
  • Patent number: 6636832
    Abstract: A data file having a plurality of frames is received, with each frame having a syncword located at a first predefined length from a known data value that is inconsistent with a data pattern of the syncword. A data string including a plurality of potential syncwords is identified. A first portion of the data string in excess of a second predefined length is skipped from syncword verification processing. The second predefined length includes the first predefined length plus the length of the syncword. A second remaining portion of the data string is processed for syncword verification.
    Type: Grant
    Filed: December 15, 1999
    Date of Patent: October 21, 2003
    Assignee: Texas Instruments Incorporated
    Inventor: Hsiao Yi Li
  • Patent number: 6628697
    Abstract: A chirp waveform is employed in establishing timing synchronization between nodes of a data communication network. In one embodiment, the chirp waveform is combined with a waveform modulated with data to form a synchronization waveform. The receiver of the synchronization waveform determines an alignment of the chirp waveform to a template chirp waveform to synchronize timing between nodes.
    Type: Grant
    Filed: October 21, 1999
    Date of Patent: September 30, 2003
    Assignee: Cisco Technology, Inc.
    Inventors: Bretton Douglas, Derek Gerlach, Santosh Anikhindi, Vincent K. Jones, IV
  • Patent number: 6625240
    Abstract: In an alignment/frame synchronization apparatus, a RSB frequency-dividing circuit generates a second clock. A data width extension circuit extends eight input data into 16 output data. A byte alignment circuit generates byte signals, and byte-aligns the output signals in accordance with a byte alignment control signal. A control circuit outputs byte alignment control signals to the byte alignment circuit in correspondence with the byte signals in accordance with detection of A1A1 and A2A2 patterns, and outputs an A1/A2 consecutive pattern signal indicating the reception of a predetermined number of consecutive A1 and A2 frame patterns. A frame pulse generating circuit generates a frame pulse signal when an A2 frame pattern is received following an A1 frame pattern. A frame sync detection circuit generates a frame sync signal when the frame pulse signal output is consecutively received a first predetermined number of times.
    Type: Grant
    Filed: May 2, 2000
    Date of Patent: September 23, 2003
    Assignee: NEC Electronics Corporation
    Inventor: Yasuhiro Miyahara
  • Patent number: 6618458
    Abstract: A synchronization method for received sign and its apparatus capable of increasing accuracy of detection of a receiving signal, of estimating a frequency and of improving reliability in the synchronization of received signal are provided. A signal intensity detecting section is used to detect some peak values and timing values of signals obtained in a first frame and to store them into a memory. A signal extracting section is used to estimate timing, in a second frame, by obtaining a largest synthesized peak value in both frames from the peak value and timing value supplied by a timing estimating section. In a frame following the second frame, frequency data estimated based on a frequency estimating signal with an estimated timing and frequency data estimated based on a frequency estimating signal corresponding to the estimated timing in the frame following the second frame are synthesized and an estimated frequency error is obtained from the synthesized frequency data.
    Type: Grant
    Filed: January 26, 2000
    Date of Patent: September 9, 2003
    Assignee: NEC Corporation
    Inventor: Osami Nishimura
  • Patent number: 6603777
    Abstract: The present invention provides a frame synchronous circuit wherein the number of devices handling a high-speed digital signal is limited to the minimum without deteriorating frame pull-in time and an erroneous synchronization rate. For the sake of it, synchronous word decision devices decide frame synchronization from four lines of low-speed digital signals into which the high-speed digital signal is converted by a serial-parallel converter. An OR circuit synthesizes respective outputs of the synchronous word decision devices, and an aperture circuit applies an aperture to the output synthesized. A selection circuit fetches only one output corresponding to the change of the apparent synchronous word after establishment of synchronization. A frame counter circuit estimates a predetermined position of the next frame at the time of applying a narrow aperture. A leading-edge positioning/column change circuit performs leading-edge positioning and column change of data to the output of the selection circuit.
    Type: Grant
    Filed: May 12, 1999
    Date of Patent: August 5, 2003
    Assignee: NEC Corporation
    Inventor: Atsuhiro Kubota
  • Patent number: 6587695
    Abstract: A method is disclosed to distinguish a first type of control channel from a second type of control channel. The method includes steps of (a) transmitting a carrier of the first type of control channel so as to include a first symbol sequence that results, when demodulated, in a sine wave having a frequency with a first offset from the carrier; (b) transmitting a carrier of the second type of control channel so as to include a second symbol sequence that results, when demodulated, in a sine wave having a frequency with a second offset from the carrier; and (c) demodulating a received carrier and detecting whether the carrier includes the first type of control channel of the second type of control channel. In the preferred embodiment of this invention the first symbol sequence is an all zeroes sequence, and the second type of symbol sequence is an alternating ones and zeroes sequence, which results in the first offset being a positive offset, and the second offset being a negative offset.
    Type: Grant
    Filed: September 25, 2000
    Date of Patent: July 1, 2003
    Assignee: Nokia Mobile Phones Limited
    Inventors: Kari Jyrkka, Harri Jokinen
  • Patent number: 6570935
    Abstract: In this demodulation method, a receive signal is demodulated estimating the fading distortion of data by detecting the fading distortion of unique word as pilot signal inserted into multiple sections of the receive signal. The method has the steps of: comparing a unique word in the multiple sections of receive signal and a known unique word and thereby detecting the fading distortion of unique word in the multiple sections; calculating a spline interpolation curve based on the fading distortion of unique word in the multiple sections; estimating the fading distortion of data in the receive signal from the spline interpolation curve; and demodulating the data in the receive signal based on the fading distortion of the data.
    Type: Grant
    Filed: May 24, 1999
    Date of Patent: May 27, 2003
    Assignee: NEC Corporation
    Inventor: Naohiko Sugita
  • Patent number: 6556639
    Abstract: A method is provided for transmitting control information in a digital audio broadcasting system. The method comprises the steps of transmitting a plurality of control bits in each of a plurality of control frames, wherein a first sequence of the control bits represents a transmission mode, and a second sequence of the control bits represents a control data synchronization word. The plurality of control bits can further include a third sequence of bits representative of an interleaver synchronization word. A method performed in a radio receiver for determining transmission mode and synchronization for a digital audio broadcasting signal is also provided. The method comprises the steps of receiving a plurality of interleaver frames containing digital information, wherein each of the interleaver frames includes a plurality of control frames.
    Type: Grant
    Filed: June 24, 1999
    Date of Patent: April 29, 2003
    Assignee: Ibiquity Digital Corporation
    Inventors: Don Roy Goldston, Marcus Matherne
  • Patent number: 6542563
    Abstract: In order to obtain a digital radio communication receiver having a preferable frame-structure decision probability, a frame synchronization state is decided in accordance with separately detected frame-synchronization synchronous words and a frame-structure is decided in accordance with a frame-structure synchronous word and to output the frame synchronization state and the frame structure.
    Type: Grant
    Filed: November 20, 1998
    Date of Patent: April 1, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Takanori Shoji
  • Patent number: 6535547
    Abstract: A method for improving the performance of a random access communications system in a variable radio environment is disclosed, whereby at least one valid set of burst signatures is used for transmission by one or more mobile stations. Each set includes at least one signature with a different signature-length than the signatures in other sets. The different signature-lengths can be optimized for the operational environments involved (e.g., longer signatures for slower-moving mobile stations, and shorter signatures for high-speed mobile stations). Alternatively, at least one differentially-encoded signature is used for random access transmissions, in order to reduce the radio channel's sensitivity to large doppler spreads and frequency errors.
    Type: Grant
    Filed: June 2, 1999
    Date of Patent: March 18, 2003
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Bo Lyckegård, Riaz Esmailzadeh, Johan Nyström, Erik Dahlman, Sandeep Chennakeshu, Karim Jamal
  • Patent number: 6483885
    Abstract: A frame synchronizer for use in a receiver that receives an encoded signal from a transmitter includes a conjugation unit, a delay unit and multiplier coupled together to process the encoded signal. The multiplier multiplies either the received encoded signal by a conjugated, delayed version of the received encoded signal or multiplies a conjugated version of the received encoded signal by a delayed version of the received encoded signal to produce a first product signal. A further multiplier multiplies the first product signal with a locally-stored signal to generate a second product signal. An accumulator accumulates the second product signal over a plurality of bit times to generate an accumulated signal having a magnitude representing a time synchronization offset between the receiver and the transmitter and phase representing a frequency synchronization offset between the receiver and the transmitter.
    Type: Grant
    Filed: September 3, 1999
    Date of Patent: November 19, 2002
    Assignee: PrairieComm, Inc.
    Inventors: Wayne H. Bradley, James L. Porter
  • Patent number: 6480558
    Abstract: A received communications signal is correlated with a common synchronization code to produce a synchronization detection signal. A component of the synchronization detection signal associated with a known synchronization signal is canceled from the synchronization detection signal to produce an interference-canceled synchronization detection signal. Timing of a synchronization signal is determined from the interference-canceled synchronization detection signal. According to one aspect, interference cancellation is achieved by generating a correlation of an estimated received known synchronization signal with the common synchronization code, canceling the correlation of the estimated received known synchronization signal with the common synchronization code from the synchronization detection signal to produce the interference-canceled synchronization detection signal.
    Type: Grant
    Filed: March 17, 1999
    Date of Patent: November 12, 2002
    Assignee: Ericsson Inc.
    Inventors: Tony Ottosson, Yi-Pin Eric Wang
  • Patent number: 6470142
    Abstract: A data recording and reproducing apparatus for recording and reproducing video signals in a plurality of formats with different rates to/from a record medium is disclosed. In the data recording and reproducing apparatus, a video signal in a selected format is converted into video data packets and audio data packets whose lengths are optimally designated corresponding to the selected format. With a video data packet and an audio data packet, a video sync block and an audio sync block whose lengths are different are formed, respectively. The video sync block and the audio sync block are encoded with respective error correction codes. The resultant data is recorded as record data to a record medium. Corresponding to the data rate of the video signal, at least one data packet is placed in one video sync block. A synchronization detecting apparatus automatically and accurately detects sync blocks with different lengths from a data sequence of record data reproduced from a record medium.
    Type: Grant
    Filed: November 8, 1999
    Date of Patent: October 22, 2002
    Assignee: Sony Corporation
    Inventors: Masaaki Isozaki, Yoshio Oyone
  • Patent number: 6438175
    Abstract: In transmitting ten-bit word string data including synchronous word data converted, at a transmitting side, from eight-bit word string data, representing signal information data synchronization required for reproducing the signal information is reliably established at a receiving side. An additional word data group containing eight-bit synchronous word data is inserted between words of the eight-bit word string data. Then, 8B-10B conversion is performed on the eight-bit word string data, thereby obtaining ten-bit word string data. In this case, the additional word data group is selected so that a running disparity of the ten-bit synchronous word data contained in the additional word data group of the composite ten-bit synchronous word data is consistently positive or negative.
    Type: Grant
    Filed: December 16, 1999
    Date of Patent: August 20, 2002
    Assignee: Sony Corporation
    Inventor: Shigeyuki Yamashita
  • Patent number: 6424689
    Abstract: In a mobile radio communication system, a transmitter of a base station transmits broadcast information to receivers of mobile stations in the form of frames. The transmitter produces a long frame composed of a plurality of frames each including a first bit sequence and part of the broadcast information following the first bit sequence, and a second bit sequence located at the head of the long frame. Each of the first bit sequences and the second bit sequence is used for establishing synchronization between the transmitter and each of the receivers. Upon receipt of the long frame from the transmitter, the receiver establishes synchronization of the long frame based on the foregoing second bit sequence.
    Type: Grant
    Filed: November 24, 1998
    Date of Patent: July 23, 2002
    Assignee: Oki Electric Industry CO, Ltd.
    Inventor: Masami Abe
  • Patent number: 6421647
    Abstract: A data file (22) having a plurality of frames is received, with each frame having a syncword. A data string (52) including at least one potential syncword (54) is identified in the data file (22). A subsequent potential syncword address for the potential syncword (54) is determined. A pointer address corresponding to a potential syncword following the data string (52) in the data file (22) is identified. The pointer address is compared to the subsequent potential syncword address. The data file (22) is decoded based on the potential syncword following the data string in response to the pointer address corresponding to the subsequent potential syncword address.
    Type: Grant
    Filed: December 15, 1999
    Date of Patent: July 16, 2002
    Assignee: Texas Instruments Incorporated
    Inventor: Hsiao Yi Li
  • Patent number: 6414951
    Abstract: A method is disclosed for receiving a transmitted signal in a communication system employing CDMA techniques wherein the transmitted signal includes a plurality of short codes, each of which is transmitted repetitively over a fixed period of time and where the received signal has CW interference in addition to the transmitted signal. The method includes using a Sequential Ratio Probability Test (SPRT) for detecting the presence of the short code in a plurality of time phases of the received signal by calculating a likelihood ratio for each phase. A likelihood ratio is a comparison of the signal's Probability Distribution Function (PDF) with a background noise PDF. The background noise PDF is calculated by combining in the RAKE the current short code with the input signal.
    Type: Grant
    Filed: October 8, 1999
    Date of Patent: July 2, 2002
    Assignee: InterDigital Technology Corporation
    Inventors: Faith M. Ozluturk, Alexander M. Jacques
  • Patent number: 6413773
    Abstract: This invention pertains to the discovery that inhibition of phosphatidylinositol 3-kinase (PI3K) in human fetal undifferentiated cells induces morphological and functional endocrine differentiation. This is associated with an increase in mRNA levels of insulin, glucagon, and somatostatin, as well as an increase in the insulin protein content and secretion response to secretagogues. Blockade of PI3K also increases the proportion of pluripotent precursor cells coexpressing multiple hormones and the total number of terminally differentiated cells originating from these precursor cells.
    Type: Grant
    Filed: May 26, 1999
    Date of Patent: July 2, 2002
    Assignee: The Regents of the University of California
    Inventors: Andrezej Ptasznik, Alberti Hayek, Gillian M. Beattie
  • Patent number: 6404758
    Abstract: A system and method are provided for achieving slot synchronization in a Wideband CDMA system in the presence of large initial frequency errors. A FSC matched filter having a reduced coherence window is provided for reducing degradation of a symbol due to carrier phase rotation resulting from oscillator error, thereby preventing severe loss of signal energy at the peaks of the FSC matched filter output. Additionally, a circular sliding integrator is provided to combine the accumulated disbursed signal energies due to the oscillator error and multipath interference, thereby allowing easier identification of the time index representing the time slot boundary. Further, a sorter is provided for determining a predetermined number of time index candidates representing the time slot boundary, thereby increasing the possibility that the true time index boundary is sent to the second stage of synchronization.
    Type: Grant
    Filed: April 19, 1999
    Date of Patent: June 11, 2002
    Assignee: Ericsson, Inc.
    Inventor: Yi-Pin Eric Wang
  • Patent number: 6363130
    Abstract: The timing of an access burst received in a base station of a wireless communications system is determined by detecting one or more zero bit fields, constituting predetermined sequences of identical consecutive symbols in the access burst. For each possible timing of the access burst, whether a predetermined sequence is present in the respective position in the access burst is detected by predicting a sample of the received signal in the current symbol period from a sample of the received signal in the preceding symbol period assuming identity of symbols in the current and preceding symbol periods, producing a squared distance between predicted and received samples for the current symbol period, producing a threshold in dependence upon a power of the received signal for the preceding symbol period to accommodate fading, and comparing the squared distance with the threshold, continuing for successive current symbol periods until the end of the sequence or until the respective threshold is exceeded.
    Type: Grant
    Filed: February 26, 1998
    Date of Patent: March 26, 2002
    Assignee: Nortel Networks Limited
    Inventors: Chandra Sekhar Bontu, Yonghai Gu
  • Patent number: 6359656
    Abstract: Control information is processed in synchronism with audio and video data according to a protocol such as RTP (Real-time Transfer Protocol). In one embodiment, a payload handler receives incoming data packets and forwards them to either a data control filter or an audio packet handler. The data control filter determines whether the data payload contains video data or control information and forwards video data to a video data packet handler and data control information to a data handler. The data control information can include an action identifier field (e.g., containing a “display” command) and a data object field (e.g., identifying a file location in a memory) so that the data control filter can display the identified file with the presentation of the other video and audio data.
    Type: Grant
    Filed: December 20, 1996
    Date of Patent: March 19, 2002
    Assignee: Intel Corporation
    Inventor: Jeffrey L. Huckins
  • Patent number: 6339627
    Abstract: A synchronization detector has three registers to memorize individual patterns of three successive frames. A decoder produces a frame location signal on the basis of the individual patterns. A pointer circuit counts the number of the frame location signal to produce a pointer signal. The decoder produces a count-up signal when it can decode the individual patterns. The decoder produces a reset signal when it can not decode the individual patterns. A counter counts the count-up signal and is reset by the reset signal. A register holds a predetermined value. A comparator compares the count value of the counter with the predetermined value. The comparator produces a comparing order signal when the predetermined value is less than the count value. A comparing circuit compares the frame location signal with the pointer signal. If the frame location signal is not equal to the pointer signal, it happens that an optical head skips a few frames or slips to a next truck.
    Type: Grant
    Filed: June 12, 1998
    Date of Patent: January 15, 2002
    Assignee: NEC Corporation
    Inventor: Tetsuo Ashizawa
  • Patent number: 6330293
    Abstract: Coarse symbol synchronization is carried out during reception, for tuning, the signal being correlated in the time domain with various copies of itself which are shifted in time and correspond to the possible transmission modes. The present mode, the present guard interval and a sampling window are derived from this.
    Type: Grant
    Filed: July 2, 1998
    Date of Patent: December 11, 2001
    Assignee: DeutscheThomson-Brandt GmbH
    Inventors: Otto Klank, Wolfgang Klausberger, Jürgen Laabs
  • Patent number: 6317455
    Abstract: A system and method for user information transfer before modem connection. The invention makes high-speed modems more efficient, particularly for transaction and Internet applications, by providing for transmission of pre-connection user data during modem training. A training sequence for a modem in accordance with the invention may be summarized as follows: beginning training of the modem at a first data rate using a defined training sequence; after a selected amount of training, transmitting pre-connection user data from the modem at up to the first data rate while continuing training of the modem; ending training; and enabling transmission of user data at a full connected data rate of the modem.
    Type: Grant
    Filed: December 16, 1997
    Date of Patent: November 13, 2001
    Assignee: 3Com Corporation
    Inventors: Richard G. C. Williams, John Rosenlof
  • Publication number: 20010021236
    Abstract: Method for synchronizing frames by using pilot patterns in a compressed mode. In a case a W-CDMA mobile communication system is operated in a compressed mode, the present invention permits to restore perfect frame synchronization words in frames by using dedicated pilot sequence pattern, and achieve frame synchronization by using correlation of the restored frame synchronization words, even if all the 15 slots of one frame are not transmitted.
    Type: Application
    Filed: February 15, 2001
    Publication date: September 13, 2001
    Applicant: LG Electronics Inc.
    Inventor: Young Joon Song
  • Patent number: 6272186
    Abstract: The invention is a novel method enabling a base station receiver to quickly and accurately validate a coded digital verification color code (CDVCC) vector received from a mobile station against a locally stored CDVCC vector identifying the cell to which it belongs. At the base station receiver, the received signal is sampled at twice the transmitted symbol rate, producing complex-valued samples of the received symbol envelope. These contain the received CDVCC vector and a known SYNC vector, and are assumed to have undergone dispersion characterized by several dispersion coefficients. The SYNC vector is detected with relative ease, allowing the establishment of a reference sample time. This is followed by the receiver determining a plurality of possible starting times (or “shifts”) for the CDVCC vector relative to the reference sample time.
    Type: Grant
    Filed: December 22, 1998
    Date of Patent: August 7, 2001
    Assignee: Nortel Networks Limited
    Inventors: Chandra Sekhar Bontu, Abdulbaset Atweri Zurgani, Yonghai Gu
  • Patent number: 6212205
    Abstract: The present invention provides a method of generating a data stream comprising: generating a first slot having a first data field; generating a second slot; and providing the second slot within the first data field of the first slot. The present invention additionally provides methods of validating an integrated circuit and communicating a data stream.
    Type: Grant
    Filed: February 25, 1997
    Date of Patent: April 3, 2001
    Assignee: VLSI Technology, Inc.
    Inventor: Michel Eftimakis
  • Patent number: 6134285
    Abstract: In accordance with this invention, a data capture circuit of a data receiver captures data from a data stream of a data transmitter operating at a different phase or frequency from the system clock of the data receiver. In one embodiment, the data receiver determines the number of clock periods of a clock signal in a data period of the data stream. Specifically, a signal detection circuit receives a signal having a periodic and distinctive feature. The period of the periodic and distinctive feature is related to the data period by a fixed scaling factor. A counter counts the number of clock periods of the clock signal between a first occurrence of the periodic and distinctive feature and a second occurrence of the periodic and distinctive feature. A multiplier/divider circuit divides or multiples the content of the first counter by the scaling factor to determine the integer clock period count. The results of the multiply or divide is stored in a count register.
    Type: Grant
    Filed: May 28, 1997
    Date of Patent: October 17, 2000
    Assignee: Integrated Memory Logic, Inc.
    Inventor: Wei-Chi Lo
  • Patent number: 6134287
    Abstract: A method and system for time aligning a frame (60) in a communication network (10) involves the steps of; i) determining if a frame needs to be advanced at a BTS (14), and ii) sending a shortened synchronization pattern from the BSC (12). The BTS (14) then determines if a short or long synchronization pattern has been sent by determining (256) if the received data stream matches a long synchronization pattern and setting a first flag when they do match. If the received data stream does not match the long synchronization pattern and the first flag is set (264), the data stream is compared (266) to the short synchronization pattern. When they match a second flag is set (268).
    Type: Grant
    Filed: November 30, 1998
    Date of Patent: October 17, 2000
    Assignee: Motorola, Inc.
    Inventors: Lee Michael Proctor, Quoc Vinh Nguyen, Gino Anthony Scribano, Gregory Keith Wheeler
  • Patent number: 6128358
    Abstract: A bit shift value of a synchronizing signal is detected. That is, after respective hamming distances between data from the first part of the synchronization signal and the respective pre-detects words, which are calculated by hamming distance calculators, are respectively compared with a predetermined value by comparators, the compared results are encoded by an encoder and the results are output as the bit shift value. Such bit shift value may be utilized to shift positions of the synchronizing signals of synchronizing blocks.
    Type: Grant
    Filed: October 25, 1996
    Date of Patent: October 3, 2000
    Assignee: Sony Corporation
    Inventor: Kaoru Urata
  • Patent number: 6118833
    Abstract: A fast acquisition method is described that combines timing, gain and, if required, equalizer acquisition in one go with word synchronization. At the heart of the method is a preamble that begins with a repetition of identical words P whose length matches the code-word length. Preferably the method ends with a frame-sync word based on the bit-by-bit inverse of P. Main attractions of the technique are simplicity, speed, and robustness.
    Type: Grant
    Filed: August 27, 1997
    Date of Patent: September 12, 2000
    Assignee: U.S. Philips Corporation
    Inventors: Johannes W. M. Bergmans, Ho W. Wong-Lam, Johannes O. Voorman
  • Patent number: 6111924
    Abstract: A de-framer (72) in a communications gateway (22) translates videoconferencing information from a circuit-switched format to a packet-switched format. A demultiplexor (78) extracts a bitstream containing video information that includes error-correction-code fields disposed at predetermined locations with respect to synchronization bits spaced by a synchronization interval and forming a predetermined synchronization sequence. A frame checker (88) for checking the error-correction code finds codeword boundaries by comparing the predetermined synchronization sequence with sequences of synchronization-interval-spaced video-bitstream bits until it finds a match. To do so, the frame checker (88) takes a group of video-bitstream words offset from each other by the synchronization interval. It compares each word in the group with a respective synchronization word consisting of a word-width replication of a respective synchronization bit.
    Type: Grant
    Filed: February 3, 1998
    Date of Patent: August 29, 2000
    Assignee: VideoServer, Inc.
    Inventor: Brittain S. McKinley
  • Patent number: 6104730
    Abstract: A method, apparatus and article of manufacture are described. In particular two network interface devices that are connected over apath that includes a digital trunk using robbed-bit signaling use a technique to identify the presence of robbed-bit signaling. The network interface devices synchronize to bytes that are subject to robbed-bit signaling. The network interface devices must synchronize to the robbed-bit signaling to avoid transmitting information or receiving information in these signaling positions. The network interface devices then take advantage of the least significant bit positions of frames that are not used for robbed-bit signaling. This results in an increase in data carrying capacity from 56 kps to 62.7 kps.
    Type: Grant
    Filed: November 25, 1997
    Date of Patent: August 15, 2000
    Assignee: International Business Machines Corporation
    Inventor: Laurence Victor Marks
  • Patent number: 6104770
    Abstract: There is provided an apparatus for detecting a synchronizing signal, including a first circuit for extracting bit clocks from serial data received, a shift register for shifting the serial data bit by bit on the basis of the bit clocks, and latching the thus shifted serial data, a second circuit for counting the bit clocks, and generating word clocks in accordance with the number of count of the bit clocks for outputting parallel data, a third circuit for detecting a synchronization pattern from the serial data stored in the shift register, and generating a first synchronization-detecting signal, a fourth circuit for detecting a synchronization pattern from the parallel data, and generating a second synchronization-detecting signal, and a fifth circuit for determining whether frame synchronization is made, by the first and second synchronization-detecting signals, and generating a frame synchronization indication signal indicative of whether frame synchronization is made or not.
    Type: Grant
    Filed: January 9, 1998
    Date of Patent: August 15, 2000
    Assignee: NEC Corporation
    Inventor: Takayuki Yama
  • Patent number: 6097776
    Abstract: The present invention describes a method of estimating the symbol time offset in a received signal of a data modem using only one received synchronization symbol. This estimate of the offset is used for a rapid synchronization during the starting phase or for resynchronization during a micro-interruption. The method estimates the offset by comparing the frequency domain constellation obtained by transforming the received synchronization symbol using the current sample pointer setting with the frequency domain constellations stored as templates. (A constellation point for a channel is phase and magnitude values in frequency domain for the channel). It chooses the template which is closest to the received constellation and declares the offset corresponding to the chosen template as the estimated offset for the received symbol. The templates are obtained by the following process.
    Type: Grant
    Filed: February 12, 1998
    Date of Patent: August 1, 2000
    Assignee: Cirrus Logic, Inc.
    Inventor: Hakim M. Mesiwala
  • Patent number: 6094443
    Abstract: A network interface in a workstation computer includes a pattern matching circuit to enable the workstation computer to wake up to perform prescribed operations requested by a remote workstation. The pattern recognition circuit includes a pattern memory configured for storing a pattern entry for at least a portion of a predetermined pattern. The pattern entry includes a pattern data field and a second field specifying a number of bytes in the input data stream to be ignored prior to comparison with the pattern data field. The pattern matching circuit also includes a comparator for comparing the pattern data field with a selected group of bytes from the data stream. Pattern match logic determines whether the received data packet includes the predetermined pattern based on the comparison result.
    Type: Grant
    Filed: October 30, 1997
    Date of Patent: July 25, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Jeffrey Roy Dwork
  • Patent number: 6081549
    Abstract: Phases of the spread spectrum signal are corrected with a high degree of accuracy by a minimum of circuitry. One of phase correction circuits 31-34 of the receiver corresponds to each path. The I-component and Q-component of a despread output are supplied to the phase correction circuits 31-34. A phase error extractor 1 extracts the first phase error from a received pilot block. A phase corrector 2 corrects the phase error of a received information symbol using a correction vector that has been calculated based on the first phase error. The RAKE synthesizer 25 synthesizes the corrected received signal with outputs of the phase correction A circuits of other paths and outputs the synthesized signal to a temporary determiner 3 which temporarily determines an information symbol to be processed. The phase error is modified in a correction vector modifier 4 using the temporary determination result. A new correction vector is calculated based on the modified phase error.
    Type: Grant
    Filed: January 8, 1998
    Date of Patent: June 27, 2000
    Assignee: Yozan Inc.
    Inventors: Guoliang Shou, Changming Zhou, Xuping Zhou
  • Patent number: 6069928
    Abstract: Synchronization words, contained within a data transmission are detected by oversampling the incoming data transmission by a factor of M. Each of M samples are stored in a respective register on an ongoing basis and a receiver is activated to monitor the contents of all registers to determine if they contain a synchronization word. Commonly a plurality of registers may detect the presence of a synchronization word simultaneously. The one having the largest amplitude bit samples is selected and the receiver changes mode to monitor the output of that register while another receiver is activated to monitor all registers. This is particularly useful in detecting synchronization words or flags in data packets, particularly in modem to modem communications.
    Type: Grant
    Filed: June 30, 1997
    Date of Patent: May 30, 2000
    Assignee: Cirrus Logic, Inc.
    Inventor: Sanjay Gupta
  • Patent number: 6069667
    Abstract: In a Sync signal detection circuit for detecting a Sync signal included in a television signal transmitted in a digital mode, pattern check means 2 checks a pattern of a Sync signal which is super imposed on a series of input data with a reference pattern. Based on a check result, Sync detection determination means 5 outputs a Sync detected signal or a Sync non-detected signal. Sync detection initialization means is further provided to this detection circuit for outputting forcibly a Sync non-detected signal when a signal of a series of input data is switched over. As a result, a Sync signal can be detected within a shorter period than the conventional circuit structure.
    Type: Grant
    Filed: October 13, 1998
    Date of Patent: May 30, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazuya Ueda, Takaaki Konishi
  • Patent number: 6058149
    Abstract: There is provided a method of transmitting and receiving a frame including unique pattern information indicative of a starting point of digital information. Step (a) performs a receive synchronizing process in which the frame is pulled in a given phase of a machine cycle equal to m which is equal to (1/N).times.L where L denotes the number of bits forming the frame, N is a positive integer and m is a positive integer larger than 2. Step (b) performs, in a receive process executing phase forming part of a same machine cycle as that of the step (a), a receive process in which receive control channel data contained in a received frame is written into a shared memory in accordance with first m-bit stream program information which defines the receive process and is stored in the shared memory.
    Type: Grant
    Filed: December 20, 1996
    Date of Patent: May 2, 2000
    Assignee: Fujitsu Limited
    Inventor: Kazuhiro Sato
  • Patent number: 6049576
    Abstract: A Kronecker product code structure for a synchronization word is presented which permits the use of dual-mode sequential matched filter. This matched filter permits a large reduction in acquisition time since the number of frequency bins that must be searched is greatly reduced when there is a large frequency uncertainty. In the first mode of operation the output of a filter matched to the high rate code is non-coherently integrated in a post-detection integrator to obtain reliable but ambiguous acquisition of the synchronization word. In the second mode of operation the ambiguity is resolved.
    Type: Grant
    Filed: October 29, 1996
    Date of Patent: April 11, 2000
    Assignee: Stanford Telecommunications, Inc.
    Inventor: David T. Magill
  • Patent number: 5982830
    Abstract: An audio decoder decodes audio frames included in a Motion Picture Experts Group (MPEG) bitstream for presentation or playing. Each audio frame includes a synchronization code and a frame header, followed by audio data. The synchronization codes are detected, and it is determined that the decoder is synchronized to the bitstream after a first predetermined number, for example three, of successive valid audio frames have been detected. It is similarly determined that the decoder is unsynchronized to the bitstream after a second predetermined number, which can also be three, of successive invalid audio frames have been detected. Each and every frame is determined to be valid if its header parameters are valid, it passes the CRC error check (optional), no syntax errors are detected and its frame length (interval) is as expected.
    Type: Grant
    Filed: April 14, 1997
    Date of Patent: November 9, 1999
    Assignee: LSI Logic Corporation
    Inventors: Greg Maturi, Gregg Dierke
  • Patent number: 5960048
    Abstract: The invention relates to synchronizing in communication systems by using a sequential correlation technique. A digital sequence known to the receiver, a so-called signature, is allocated a plurality of segments. The segments are correlated, segment for segment, in a correlator (300) which is equally as long as the segment. The segments may have the same or different bit patterns. When a first segment is received in the correlator (300) and the correlation value of this segment exceeds an associated threshold value, the segment is accepted as received and is saved in a memory (308) in response to a signal from the control unit (311). A timer (319) is set to a time point that corresponds to the length of the segments. There is then correlated a second segment whose correlation value on the signal from the timer (319) is added (304) to the value stored in the memory (308). If the sum exceeds an associated threshold value, the sum is stored in the memory (308). Detection continues in this way.
    Type: Grant
    Filed: March 25, 1997
    Date of Patent: September 28, 1999
    Assignee: Telefonaktiebolaget LM Ericsson
    Inventor: Jacobus Cornelis Haartsen
  • Patent number: 5923220
    Abstract: The clock reproducing device includes a control device which generates a control signal for decreasing a clock frequency difference between a transmitter and a receiver according to a clock information difference between the transmitting clock information and reproduced clock information and a receiving interval of the transmitting clock information, thereby the clock reproducing device controls a reproduced clock frequency of a reproduced clock output device. The clock reproducing device carries out appropriate frequency control regardless of the transmitting interval of the transmitting clock information received from the transmitter.
    Type: Grant
    Filed: December 23, 1996
    Date of Patent: July 13, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Hiroshi Honma
  • Patent number: 5914992
    Abstract: In a synchronizing system searching for k sub-frame patterns respectively distributed in k sub-frames in one frame of data transmitted via a transmission line where k is an integer, a frame pattern detection unit sequentially detects one of the k sub-frame patterns with a predetermined period. A control unit causes the pattern detection unit to detect an (i+1)th sub-frame pattern at the predetermined frame period after the pattern detection unit detects an ith sub-frame pattern where i=1, 2, . . . , k.
    Type: Grant
    Filed: March 26, 1997
    Date of Patent: June 22, 1999
    Assignee: Fujitsu Limited
    Inventor: Tadayuki Takada
  • Patent number: 5907587
    Abstract: A data clock signal for data in an incoming signal is generated by means of a clock recovery module. The incoming signal consists of a data burst having a periodic preamble followed by a data sequence. The clock recovery module comprises a first clock generator, a sampling device, a correlator, a control unit and a time registration device. The clock generator generates a clock signal having a first clock frequency which is a factor N higher than the frequency of the preamble. The sampling device samples the incoming signal at the first clock frequency. The correlator correlates the sampled signal with a predefined correlation word, the correlation between the incoming signal and the correlation word being represented as a correlation signal in the form of a series of discrete correlation signal values. The control unit detects local extreme values for the correlation signal.
    Type: Grant
    Filed: February 7, 1997
    Date of Patent: May 25, 1999
    Assignee: Nokia PHones Limited
    Inventor: Izydor Sokoler
  • Patent number: 5905762
    Abstract: A receiver carrier synchronization apparatus and method for carrier synchronization with a received signal having a known data pattern preamble uses a "punctured" preamble for making carrier synchronization estimates thereby reducing the number of receivers required. The known data pattern preamble of the received signal is processed with a local reference signal and a differentiated replica of the known data pattern preamble to generate an error signal. The error signal is selectively sampled in the time domain in accordance with a puncture scheme, and the sampled error signal is used to generate the local reference signal in a closed loop. The received signal is processed with the local reference signal and a replica of the known data pattern preamble to generate a synchronization estimate signal.
    Type: Grant
    Filed: January 21, 1998
    Date of Patent: May 18, 1999
    Assignee: Raytheon Company
    Inventor: Donald R. Stephens
  • Patent number: 5903619
    Abstract: A method is provided for detecting a synchronization word in frames of serially transmitted data. The synchronization word consists of l synchronization bits, which are transmitted one bit per frame at a known position in each frame. The method comprises the steps of: storing each incoming bit in a memory organized as groups of words, each having at least l bits, so that each group of words contains bits from a same position in consecutive frames; rotating each group of words; comparing the group of words, at each rotation, to the synchronization word.
    Type: Grant
    Filed: August 21, 1997
    Date of Patent: May 11, 1999
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Philippe Chaisemartin