Abstract: Various embodiments are described to provide for the transmission and reception of data in an improved manner. Data transmission is improved by including in a transmitter a null generator (110) to generate an output data symbol sequence that exhibits nulls in the frequency domain at particular frequencies that an input data symbol sequence does not. A pilot inserter (120) then adds a pilot symbol sequence to this output data symbol sequence to create a combined symbol sequence. Since the pilot symbol sequence exhibits pilot signals corresponding to the nulls of the output data symbol sequence in the frequency domain, the combined symbol sequence exhibits pilots that are orthogonal to the data in the frequency domain.

Abstract: A DSRC communication technology that prevents unique word detection errors even when the frame changes in data reception and the timing of the unique word detection window and the timing of the received data do not match, and that adjusts the data transmission timing in a flexible fashion when the slot timing deviates from the frame timing. In this technology, bit counter 111 generates the frame timing from the frame synchronization signal, and bit counter 112 generates the sot timing in response to the slot synchronization signal. The unique word detection window is generated from the frame timing and the received data operation timing and the data reception timing are generated from the slot timing. In addition, the data transmission timing and the transmission data operation timing are generated based on one of the frame timing and the slot timing chosen in selector 123.

Abstract: A cell searching apparatus and method in an asynchronous mobile communication system allocates an adjacent SCG to each base station according to adjacent degrees. When a mobile terminal is powered on, the mobile terminal receives PSCs and SSCs from the base stations. Multiple searching of SSCs is then performed based on each slot synchronization followed by a frame synchronization and SCG detection through the first searched SSC. If the detected SCG is not an SCG of a base station to which the mobile terminal belongs, the cell searching apparatus detects an SCG with a large size among the adjacent SCGs and detects an SC by using the greatest SCG. Frame synchronization and SCG detection are therefore quickly performed in a cell searching, resulting in a quick search searching.

Abstract: A system and method for asynchronous data communication over a cellular communications network that allows the transmission of different types of data frames over a voice channel using a vocoder. The data frames include a synchronization signal and data segment, with the synchronization signal being selected in accordance with an attribute of the data segment so that, upon receipt of the data frame, the synchronization signal can be used by the demodulating modem to determine not only where the data segment begins, but also to identify what type of data segment is in the received data frame. The synchronization signals used have low cross-correlation and an auto-correlation function that approximates a unit impulse function to provide reliable transmission through the vocoder.

Abstract: Technologies for scheduling the dispatch of multi-channel isochronous constant-rate data, such as real-time and/or streaming audio data, video data, or the like. The technologies include systems and methods that provide for the independent dispatch of such data from each of multiple channels such that data delays in one channel have no adverse affect on the dispatch of data from another channel.

Abstract: An asynchronous data transmitting apparatus includes data signal transmission lines; two control transmission lines having a minimum delay and maximum delay respectively; a transmitter; and a receiver. The transmitter includes a data transmitting unit that transmits a data signal through the data signal transmission lines, depending on a transmit clock; and control transmitting units that transmit control signals through the control transmission lines, depending on the transmit clock. The receiver includes a receive clock generator that generates a read clock from the control signals; and a data receiving unit that receives the data signal through the data signal transmission line, depending on the read clock.

Abstract: A decoding method is carried out in a receiver configured to accept format information relating to sequences of input data, to use format information in the decoding of each input sequence, and to issue an acknowledgement signal in the event that an input sequence is successfully decoded. The method involves receiving a format message pertaining to a new input sequence, searching a candidate set of format indices an index best satisfying a criterion for matching to the format message, and selecting the index giving the best match. Before searching, the receiver reads the acknowledgement signals issued in response to the decoding or attempted decoding of recent input sequences. If the acknowledgement signals satisfy an appropriate condition, the search is limited to fewer than all the indices in the candidate set. The format information that corresponds to the selected index is used in decoding the new input sequence.

Abstract: A counter value of a divider counter 3 that determines a communication speed is compared by a comparator 4 with a value calculated from a difference between fall delay and rise delay, and data is received with a matching signal serving as a data reception shift clock (S201), thereby acquiring receive data on the optimum position. Further, with the data reception shift clock (S201) serving as a data transmission shift clock (S201), the transmission control circuit 5 transmits serial data (S203) from the data transmission shift register 7 as data with a duty ratio reversed from a varied duty ratio of the communication system. Thus, it is possible to transmit data with a normal duty ratio to another communication device.

Abstract: In an auto baud system and method, the baud rates between two communicating devices are synchronized by timing the transmission of a plurality of bits by counting the cycles of a reference clock. The number of cycles counted is then divided by the number of bits counted over and any remaining cycles are distributed evenly across the data being transmitted or received. The interface of the circuit is preferably implemented as a single pin, open drain interface which can be connected to an RS-232 communications link using external hardware.

Abstract: A method and circuit capable of handling skew between a clock and data signal up to +/? one half bit on a random input data pattern. A digital algorithm cycles through each data bit and individually deskews that bit by detecting data transitions in a first sampling region and in a second sampling region and determining a difference between a number of transitions in the first sampling region and a number of transitions in the second sampling region. The sampling regions and a deskew timing signal may then be incremented or decremented based on a comparison of the computed difference to a predetermined constant. If no transitions occur on a particular bit, the algorithm times out leaving the deskew timing signal in the original position. When analysis of a final bit of a channel is completed, the algorithm begins monitoring and analyzing the first bit of another channel.

Abstract: In a DSRC communications controller equipped with a plurality of reception means for DSRC communications according to the invention, a reception reservation storage section 104 comprises means for detecting a communications frame start signal (unique word 1) of DSRC communications by using reception means not engaged in communications among the plurality of reception means and means for storing the control information of DSRC communications where the communications frame start signal is detected. On completion of DSRC communications by way of reception means, a controller uses the control information stored in the reception reservation storage section to establish next communications. This allows continuous reception of information from a plurality of roadside machines to be made efficiently even in case a plurality of communications areas overlap one another.

Abstract: Additional information on the phase of an external clock signal is obtained by using clock signals to determine if a phase difference between an external clock signal and a first internal sampling clock signal is less than a pre-selected value. If the system determines that the phase difference is less than a pre-selected value, one embodiment samples the incoming data with a second internal sampling clock signal, having a selected phase relationship to the first internal sampling clock signal, such as ½ a clock period out of phase. By maintaining sufficient phase difference between the active edge of the external clock and the active edge of the internal sampling clock, the embodiment provides a sufficient setup/hold margin to avoid a metastability or other problem in a subsystem receiving data across an asynchronous boundary.

Abstract: In a digital protection relay with a time sync function, the sampling timing of which is specified based on a reference timing transmitted from a time signal generator to a time sync unit, with a determination value. The time sync unit includes a reception circuit that receives a discrimination code and time data transmitted from the time signal generator, a code discrimination circuit that discriminates the reference timing on condition that the received discrimination code coincides with a desired code, a time calculation circuit that calculates the sampling timing on the basis of the discriminated reference timing and the time data, and a sampling sync circuit that specifies the sampling timing of a digital quantity of electricity on the basis of the calculated sampling timing.

Abstract: A skip-free retiming system and method for transmission of digital information in a plesiochronous data communication system is described. The system is capable of supporting an unlimited number of retimers in serial data path between a first and a last node. The retimers are configured to retime, amplify and retransmit a received data stream without altering the received data rate. Thus, the data rate from the first node is received at the same frequency at the last node, regardless of the number of retimers. In general, the retimer performs rate compensation on a retimer local clock, rather than on the data stream, so the attributes of the clean retimer clock can be applied to the data stream without changing the data rate.

Abstract: In an auto baud system and method, the baud rates between two communicating devices are synchronized by timing the transmission of a plurality of bits by counting the cycles of a reference clock. The number of cycles counted is then divided by the number of bits counted over and any remaining cycles are distributed evenly across the data being transmitted or received. The interface of the circuit is preferably implemented as a single pin, open drain interface which can be connected to an RS-232 communications link using external hardware.

Abstract: A clock data recovery (CDR) circuit to recover a clock signal and data signal from an input signal. The CDR circuit includes a control circuit, a select circuit and a phase adjust circuit. The control circuit generates a first control signal according to a phase relationship between the input signal and a first clock signal. The select circuit is coupled to receive the first control signal from the control circuit and coupled to receive a second control signal. The select circuit is responsive to a select signal to select either the first control signal or the second control signal to be output as a selected control signal. The phase adjust circuit is coupled to receive the selected control signal from the select circuit, the phase adjust circuit being responsive to the selected control signal to adjust the phase of the first clock signal.

Abstract: The invention relates to a method for data transmission in a communication system, especially in a CDMA mobile radio system, wherein the data are transmitted structured into frames (1, 4, 5) and a transmitting station transmits the data in such a manner that a receiving station receiving the data is able to perform other functions, especially carrying out measurements via a receiving device, during one or more interruption phases (2) in which it interrupts the reception and/or the processing of received data. It is the object of the invention to allow interruption phases (2) whilst maintaining as good a quality of the data transmission as possible. For this purpose, it is proposed that an individual continuous interruption phase (2) extends over at least sectional-portions of at least two successive frames (4, 5).

Abstract: An apparatus for immediately outputting a response of a synchronous system to an asynchronous event includes an advanced calculation device by means of which the responses of the synchronous system to possible asynchronous events can be calculated in advance. Also, a switching device is included by means of which the output signal from the advanced calculation device or the output signal from the synchronous system can be passed on selectively. It is thus possible to output responses from synchronous systems to asynchronous events immediately after such events occur.

Abstract: A clock recovery unit for generating a clock signal corresponding to an asynchronous data signal.

Abstract: A counter value of a divider counter 3 that determines a communication speed is compared by a comparator 4 with a value calculated from a difference between fall delay and rise delay, and data is received with a matching signal serving as a data reception shift clock (S201), thereby acquiring receive data on the optimum position. Further, with the data reception shift clock (S201) serving as a data transmission shift clock (S201), the transmission control circuit 5 transmits serial data (S203) from the data transmission shift register 7 as data with a duty ratio reversed from a varied duty ratio of the communication system. Thus, it is possible to transmit data with a normal duty ratio to another communication device.

Abstract: A control portion A transmits only a transmission right to a control portion B. The control portion B receives the transmission right sent from the control portion A, obtains transmission-requested data B from a utilization portion B, and then transmits it with the transmission right to the control portion A. The control portion A receives the data B and transmission right transmitted from the control portion B. If the control portion A is receiving a transmission request for data A from the utilization portion A at this time, it first obtains the transmission-requested data A from the utilization portion A and transmits it to the control portion B together with the transmission right. After transmitting the data A, the control portion A transfers the data B received from the control portion B to the utilization portion A.

Abstract: A first counter measures the span of the start bit of a first character of an AT command transmitted from a DTE based on instructions from an MPU. A decoder receives a measurement result of the first counter, outputs frequency-dividing data for producing a clock for sampling the first character, and also outputs, when the rate of the start bit is more than a preset value, a flag indicating this matter. A second counter selects, in accordance with whether or not the flag has been set, the frequency-dividing data from either the decoder or the MPU, and produces the sampling clock. A shift register receives data subsequent to the start bit of the first character based on the sampling clock from the second register, holds the received data, which data is then read by the MPU.

Abstract: Method and apparatus for synchronizing communication between a battery and an electronic device are disclosed. Bytes consisting of a number of bits are transmitted between the electronic device and the battery. A predetermined bit sequence is appended to at least some of the bytes prior to transmission. The time interval between given shifts in the predetermined bit sequence is used to synchronize the communication.

Abstract: A multipath processor processes a plurality of groups of spread-spectrum signals. Each group has a plurality of spread-spectrum signals. A first plurality of spread-spectrum signals is despread within a first group to generate a first plurality of despread signals. The first plurality of despread signals are combined as a first combined-despread signal. A second plurality of spread-spectrum signals is despread within a second group to generate a second plurality of despread signals. The second plurality of despread signals are combined as a second combined-despread signal. The first and second combined-despread signal are combined as an output-despread signal.

Abstract: Sampling data with wide bi-phase code symbols includes sampling a wide bi-phase code symbol in the data a number (N) of times to produce samples of data, selecting a subset of the samples, determining which sample in the subset of samples has a largest magnitude, and selecting a subset of samples in a subsequent wide bi-phase code symbol based on a sample in a previous subset that has the largest magnitude.

Abstract: Interface apparatus for interfacing data to a plurality of different clock domains where the clock signals in the different domains are phase locked together and respective clock signals have different frequencies includes a plurality of cascade connected first and second latches coupled between respective clock domains. One of the latches is a clocked Data Latch and the other is a clocked and Enabled Data Latch. A timing generator provides respective domain clock signals, wherein a domain clock signal of a domain providing a data signal is applied to the clock input connection of the first latch of a respective cascade connected set of latches and a domain clock signal of a domain receiving said data signal is applied to the second latch. The timing generator also provides a common Enable Signal phase locked to the domain clocked signals. The common Enable Signal is applied to the enable input terminal of one of the latches of each set of cascade connected latches.

Abstract: Methods for automatically calibration & synchronization for digital asynchronous communication., the inverter comprising: (a) initialing a target device; (b) beginning to counting as soon as the target device is detected by a falling edge of a incoming START bit; (c) ending up the counting until a rising edge of the START bit detected; (d) storing a counting result; (e) setting the result/2 to be a sampling pointer; (f) compensating a latency and elapsing a first wait loop; (g) sampling and storing a first bit; (h)compensating a latency and elapsing a second wait loop; (i) sampling and storing in accordance with bits; (j) identifiing to sampling and storing 8 bits; (k) locating a Inter Character Region according to the initialing; finally, repeating to step(b)˜step(k).

Abstract: A data synchronizer transfers information across an asynchronous interface by using system domain and core domain logic on either side of the asynchronous interface. Information registers receive data beats from a data bus coupled to an external system. Each data beat is loaded into the registers in sequential order. A corresponding system valid bit is provided for each register and is set when the corresponding register is loaded. In the core domain, a corresponding set of core valid bit registers is set in response to the system valid bit registers being set. A data sampler monitors the core valid bits in sequential order and controls a multiplexor to select a corresponding one of the registers that contains valid data. The data sampler resets the core valid bits which in-turn reset the system valid bits to signal the completion of a data transfer across the asynchronous interface.

Abstract: A spread spectrum phased array receiver has a set of phased array antennas. The set of phased array antennas receive a spread spectrum signal containing a plurality of channels. The receiver outputs timed versions of the received signal. Each timed version is associated with a respective one out of the set of phased array antennas. A plurality of despread signals is produced by despreading each timed version of the received signal using a plurality of chip code sequences associated with the channels. The despread signals are combined as a despread signal. A magnitude of the combined despread signal is determined for obtaining a present and a prior magnitude. The present and prior magnitude are compared. A delay associated with the timed versions is adjusted in response to the comparison so antenna beams are steered towards components of the spread spectrum signal with a highest combined magnitude.

Abstract: A method wherein an activated control signal is transmitted between two assemblies, which are driven asynchronously relative to one another, as a code signal which is switched between different conditions with a prescribed rate. In the receiving unit, the code signal is classified as an activated control signal only if an expected number of changes of condition are registered during a prescribed time period. There is thus a high degree of security against a misinterpretation of the control signal.

Abstract: A circuit for exchanging communications via a transmission line, including a detector for detecting a predetermined start-of-communication signal, a means for coupling the transmission line on the one hand to a transmit line to provide outgoing communications to the transmission line, and on the other hand to a receive line, to receive incoming communications from the transmission line. The detector is connected to the transmit line.

Abstract: A microcontroller provides an asynchronous serial port with a serial clock derived from the processor clock. Although the serial clock cannot be exactly programmed to yield an ideal frame length at a particular baud rate, an additional register is provided for tuning the frame length. Each transmitted asynchronous serial frame is stretched by a number of either serial clock phases or processor clocks defined in the tuning register. This provides for improved reception of the asynchronous data, because the frame length more nearly matches the ideal baud rate frame length.

Abstract: Methods of transmitting and receiving asynchronous serial data using a serial port of a digital signal processor are provided.

Abstract: A state dependent synchronization circuit synchronizes an asynchronous input signal to a clock signal to generate a synchronous output signal. The circuit synchronizes both the leading edge and the trailing edge of the input signal and also maintains the state of the output signal at a level corresponding to the input signal when the input signal does not change. The circuit includes an input signal latch which receives the input signal and provides a latched signal which does not charge state even if the input signal subsequently changes state until the latched signal is synchronized to the clock signal. The circuit further includes a synchronizer which synchronizes the latched signal with the clock signal. The synchronizer provides feedback signals to the input signal latch to permit the input signal latch to recognize a change in the state of the input signal only after the synchronizer has synchronized the previous state of the input signal.

Abstract: The speed of asynchronous serial communications is detected by determining a duration of a data bit within an asynchronous data stream. The duration of the data bit is used to generate a clock frequency. The clock frequency is used to clock data from the asynchronous data stream into a register. The clocked data is processed according to an error indication.

Abstract: In a communication system in which an asynchronous mode is employed as a media access control system, a synchronizing signal of digital data, which are sent out from a sender terminal apparatus and separated into the synchronizing signal and the bit stream data, is converted into block synchronizing signals which consist of a start signal indicating head position of bit stream data and an end signal indicating end position thereof, then the bit stream data and converted block synchronizing signals are converted into compressed block data by multiplexing them not to be overlapped on a time base respectively, and then the compressed block data are transmitted to a destination terminal apparatus via a data transmission line.

Abstract: A method and apparatus for digitally synchronizing data units received from multiple asynchronous data sources which includes storing the data necessary to compensate for phase and frequency differences between the independently clocked asynchronous sources. The method includes the step of comparing the input queues for each of said data streams against a set of known threshold conditions, and generating the composite output upon satisfaction of the threshold conditions. This method allows data from asynchronous data sources to be properly interleaved without implementation of complex phase or frequency compensation techniques, and without a large amount of data storage for buffering the input data. Furthermore, in its preferred embodiment, this invention allows the implementation of a fixed rate output clock, which greatly simplifies the design over the prior art.

Abstract: A data transmission system includes a sender and a receiver, both employing different clock rates and a data bus coupled between the sender and the receiver for transmitting signals therebetween. The receiver generates an enable signal from the receiver clock to control data transmission at the sender. The enable signal is a pulse generated at each rising edge of the receiver clock and corresponds to the data transfer rate of the receiver clock. A detector module, located at the sender, receives and captures the asynchronous enable signal and initiates transmission of one data byte for each pulse of the enable signal, thereby automatically adjusting the data transfer rate of the sender to the data transfer rate of the receiver.

Abstract: A method for handling underflow and overflow of data in a FIFO buffer includes steps of inserting an insert data word in the FIFO buffer if there is an underflow of data at the FIFO buffer and discarding a discard data word of the FIFO buffer if there is an overflow of data at the FIFO buffer. In one embodiment, the insert data word is null and does not change the status of the FIFO buffer.

Abstract: Many digital processors have an asynchronous bus controlled by two control signals. To interface a synchronous memory to an asynchronous bus, interface logic is required. In an interface for transferring data from an asynchronous circuit to a synchronous circuit, data to be written are written in an intermediate register while timing control signals are being synchronized to a system clock by means of flip-flops. Correspondingly, in an interface for transferring data from the synchronous circuit to the asynchronous circuit, a signal indicating a read transaction from the synchronous circuit is synchronized to the system clock by means of a flip-flop circuit.

Abstract: A method for protecting the transmission of network independent clocking and status information over an air interface between a mobile station and base transceiver station is disclosed. The method involves defining a parallel logical channel between the mobile station and base transceiver station to carry network independent clocking and status information. The network independent clocking and status information are removed from the data stream of the traffic channel and transmitted on the parallel channel over the air interface. Alternatively, a buffer may be used in conjunction with or singly to process the data stream of the traffic channel to delete or insert bits or characters to minimize or eliminate the need for network independent clocking information.

Abstract: A communication system that communicates between a base station and a mobile station over a wireless rf channel. The communication system uses a novel protocol for transmitting a data frame in which an 8-bit data byte is divided into two 4-bit data nibbles. Each data nibble is assigned a 4-bit sequence number to form a transmission byte. By determining the sequence number of any transmission byte or series of transmission bytes, the beginning and the end of a data frame can be determined. A CRC check indicates when a data frame has been received successfully. The protocol does not require the use of unique start-of-frame (SOF) and end of-frame (EOF) characters. Also, the system implements a majority vote algorithm that collects data from successively transmitted copies of a given data frame and performs a majority vote to determine a mostly likely received data pattern. The protocol allows the system to achieve an improvement analogous to a 1.5 to 2.

Abstract: A method is provided for allowing the transmission of digital video segments along a number of transmission channels, with the line speed, or rate of transmission in bits per second, being variable during a transmission. For each transmission channel, video data segments are stored in a data buffer, along with data segments known as Write Control Blocks (WCBs). Each WCB includes a pointer to the video data segment with which it is associated and a line speed code indicating the preferred rate of data transmission. The addresses of the WCBs are stored in a FIFO buffer which is established for each transmission channel. When coded information within a WCB indicates that a speed change is needed, a run-time subroutine executing in a co-processor sets bits within a channel control word forming a portion of each WCB to stop a DMA process and to issue an interrupt when the corresponding video segment is to be transmitted.

Abstract: Circuitry is provided that allows a register without an asynchronous loading capability to be asynchronously loaded. Logic gates are provided before and after the register. The logic gates are driven by an output signal from a storage circuit such as a latch. When the output signal has one value the logic gates act as non-inverting buffers. When the output signal has another value the logic gates act as inverters. The circuitry allows the normal synchronous operations of the register to be maintained. A hazard coverage circuit can be provided to prevent glitches from appearing at the output during asynchronous operations. The logic gates may be formed from exclusive OR gates implemented in programmable logic on a programmable logic device.

Abstract: A method and apparatus for delaying frames received asynchronously from a fiber channel port until receive memory is properly sequenced for storing the delayed frames in which a circular buffer is positioned on the data path between the fiber channel port and the receive memory for delaying the frames in accordance with control signals generated by a sequencer having knowledge of the receive memory sequence count.

Abstract: A transmission mode selector, for changing a transmission mode selector, and a reception mode selector, for changing a reception mode, are added to an infrared communication circuit that conventionally supports an IrDA; and a UART that controls serial communication, is so set in a given condition where communication can be performed with a home electronic appliance remote controller, that a protocol for the home electronic appliances can be emulated by using the infrared communication apparatus of the personal computer.

Abstract: In a serial data transmission apparatus connected to a data transmission bus, an edge detector detects an edge in a signal at the data transmission bus. An edge interrupt operation is carried out to operate a timer in response to the edge. The edge interrupt operation is stopped when the timer is being operated. A timer interrupt operation carries out a fetching operation of a bit data on the data transmission bus in a receiving mode or a transmitting operation of a bit data to the data transmission bus in a transmitting mode, in response to the timer means whose content reaches a predetermined value.

Abstract: Apparatus and method for providing communication between two computers over a communications network and for detecting a command word received form the network for interrupting normal communication. In one embodiment, the apparatus includes a first part for organizing data transmitted onto the network in asynchronous format such that the data is arranged in frames with a flag designating the start of each frame and having an interframe period between each frame during which data is not transmitted. Each frame has a time period less than the predetermined time of transmission of the command word. The apparatus includes a second part responsive to the command word for interrupting normal communication, and a third part responsive to the flag for placing the second part in a disabled state for the time period of each frame, and when the frame time period is complete, for enabling the second part to respond to the command word during the interframe period.

Abstract: A voice transmitting apparatus and a voice receiving apparatus using voice activation techniques. The voice transmitting apparatus is provided with a UW2 burst generator 8 for generating, in the absence of voice, second unique word pattern (UW2) differing from first unique word pattern (UW) used in the presence of voice. Also, the voice receiving apparatus is provided with a UW2 detection circuit which makes it silent upon the detection of the second unique word pattern (UW2), thus preventing the occurrence of unwanted sounds while positively maintaining the frame timing.

Abstract: The present invention relates to a circuit for restoring bits transmitted by an asynchronous signal, including a comparator of the signal level with a reference level; a sampling circuit supplying several samples of the comparator output for each time interval corresponding to a bit; a circuit for determining a succession of windows, each of which corresponds to a bit; an acquisition circuit receiving the samples and supplying, for each window, the number of samples having a first logic value, the number of sample transitions, and the value of a border sample of an adjacent window; and an estimation circuit for correcting the reference level and the alignment of the windows on the bits according to the outputs of the acquisition circuit.