Abstract: A method for transmitting synchronization messages in a communications network including a plurality of nodes having a first node and at least one second node, wherein in order to take into account differences in a reference clock frequency of a reference clock and an internal clock frequency of an internal clock of the at least one second node, a compensation interval, with which the second clock count state is adjusted on measurement of a delay time, is subdivided into smaller compensation timespans, and the smaller compensation timespans are used to determine a compensated time value for the delay time with a high degree of accuracy, where the compensated time value is then used to update the time information in the synchronization message.

Abstract: Disclosed herein is a synchronizing circuit including: a first PLL circuit; a second PLL circuit; a first output circuit; a second output circuit; a first detection circuit; a second detection circuit; a control circuit; and a holding section.

Abstract: An exemplary clock and data recovery circuit includes a serial data input node arranged for receiving a serial data; a reference clock input node arranged for receiving a reference clock; a control circuit arranged for generating a control signal to selectively configure the clock and data recovery to operate in one of a plurality of phases; a detective circuit arranged for generating a first adjusting signal while the clock and data recovery operates in a frequency locking phase, and for generating a second adjusting signal while the clock and data recovery circuit operates in a clock and data recovery phase; and a controllable oscillator arranged for generating a recovered clock according to the first adjusting signal in the frequency locking phase, and for generating the recovered clock according to the second adjusting signal in the clock and data recovery phase.

Abstract: A circuit may include a phase difference selector, a clock signal generator, a reference clock phase detector, and a data signal phase detector. The phase difference selector may be configured to select one of multiple reference clock phase difference signals generated by the reference clock phase detector based on a difference in phase between multiple clock signals and a reference clock. The clock signal generator may be configured to generate the multiple clock signals based on the selected reference clock phase difference signal. The data signal phase detector may be configured to generate a data phase difference signal based on differences in phase between the clock signals and a data signal. The data phase difference signal may be used by the phase difference selector to select one of the reference clock phase difference signals.

Abstract: A circuit for clocking includes an input data path, a receiver, a set of flip-flops, at least one interpolator and a controller. The receiver is coupled to the input data path for receiving input data. The flip-flops, coupled to the receiver, sample the input data. A first interpolator, coupled to one or more of the flip-flops, receives the sampled input data. The controller, coupled to the first interpolator, controls the first interpolator by providing phase information regarding the input data to the first interpolator. The circuit reduces any jitter transferred from the input path to an output path.

Abstract: Generate a series of digital data according to a pair of differential signals received from a low speed universal serial bus. Calibrate coarsely a frequency of an oscillator according to a width of an end-of-packet of the series of digital data. And calibrate finely the frequency of the oscillator according to a width of a SYNC pattern of the series of digital data.

Abstract: A clock generation device provided for a transmitter is provided and comprises a clock generator, a calculator and a first phase locked loop (PLL) circuit. The clock generator generates a first clock signal. The calculator calculates a frequency difference between the first and second clock signals. The first PLL circuit generates an output clock signal according to a first reference clock signal related to the first clock signal, and a frequency of the output clock signal is changed according to the frequency difference. The transmitter transmits data according to the output clock signal.

Abstract: An integrated CMOS clock generator with a self-biased phase locked loop circuit comprises a phase-frequency detector with a reference signal input, a feedback signal input and an output. A first charge pump of the clock generator has an input connected to the output of the phase-frequency detector and an output that supplies a control voltage. A loop capacitor is connected to the output of the first charge pump. The clock generator further has a second charge pump with an input connected to the output of the phase-frequency detector and an output. In particular, the clock generator has two oscillator blocks.

Abstract: Various embodiments of the present invention relate to systems, devices and methods of oversampling electronic components where high frequency oversampling clock signals are generated internally. The generated oversampling clock is automatically synchronous with the input clock and the input serial data in a serial data link, and is adaptive to predetermined parameters, such as bit depth and oversampling rate.

Abstract: In accordance with an embodiment of the present disclosure a phase-locked loop comprises a voltage controlled oscillator (VCO) configured to generate an output signal based on an input reference signal. The phase-locked loop further comprises a first charge pump communicatively coupled to a control input of the VCO and configured to generate, for a duration of time following occurrence of an event, a first control signal. The first control signal is independent of the output signal and is for causing the output signal to have a first frequency based on a second frequency of the input reference signal. The phase-locked loop further comprises a second charge pump communicatively coupled to the control input of the VCO. The second charge pump is configured to generate, after the duration of time, a second control signal.

Abstract: A clock and data recovery (CDR) circuit includes an inductor-capacitor voltage controlled oscillator (LCVCO) configured to generate a clock signal with a clock frequency. A delay locked loop (DLL) is configured to receive the clock signal from the LCVCO and generate multiple clock phases. A charge pump is configured to control the LCVCO. A phase detector is configured to receive a data input and the multiple clock phases from the DLL, and to control the first charge pump in order to align a data edge of the data input and the multiple clock phases.

Abstract: Embodiments allow for the use of the SS modulation technique (and thus for significant reduction of EMI due to clock transmission) in scenarios involving tight synchronization requirements between two devices. In particular, embodiments can be used in high-speed communication networks (e.g., high-speed Ethernet) where a clock signal embedded in the data stream at the transmitter and recovered from the data stream at the receiver is the only source for synchronization between the transmitter and the receiver (i.e., no other synchronization channel available). Embodiments are also especially useful in communication systems utilizing echo cancellers.

Abstract: A single chip radio transceiver includes circuitry that enables received wideband RF signals to be down converted to base band frequencies and base band signals to be up converted to wideband RF signals prior to transmission without requiring conversion to an intermediate frequency. The circuitry includes a low noise amplifier, automatic frequency control circuitry for aligning the LO frequency with the frequency of the received RF signals, signal power measuring circuitry for measuring the signal to signal and power ratio and for adjusting frontal and rear amplification stages accordingly, and finally, filtering circuitry to filter high and low frequency interfering signals including DC offset.

Abstract: It is described an electronic device for generating a fractional synthesized frequency. The device comprises a multi-phase controlled oscillator configured to generate, from a control signal, a plurality of signals phase-shifted each other and comprises a phase detector configured to receive a selected signal from the plurality of phase-shifted signals, to receive a reference signal and to measure a difference between a phase of the selected signal and a phase of the reference signal. The electronic device further comprises control means for estimating, from the measured phase difference, a phase error affecting the generation of at least one of the plurality of phase-shifted signals, and for generating a corrected measure of the phase difference taking into account the estimated phase error, the corrected measure being used to provide the control signal.

Abstract: Systems and methods are provided for calibrating the internal oscillator of a microcontroller from a remote clock source. In some embodiments, an electronic device can request timing information from a third party device using a timing independent signal. The timing information received from the third party device may be used to calibrate the microcontroller clock of the electronic device. In some embodiments, the internal oscillator may be calibrated based on timing information received from multiple third party devices. Once calibrated, the microcontroller may initiate timing dependent communication with other electronic devices using a timing dependent protocol, such as a serial protocol.

Abstract: A clock data restoration device (1A) includes a sampler portion (11), a phase comparison portion (12), a drive portion (13), a charge pump (14), a capacitive element (15), a potential adjustment portion (16) and a voltage control oscillator (17). The phase comparison portion (12) outputs a signal (UP) that becomes a significant value when the phase of a clock (CKX) delays with respect to an input digital signal, and outputs a signal (DN) that becomes a significant value when the phase advances. The drive portion (13) increases or decreases a value ? to or from a variable ? when the signals (UP) and (DN) become a significant value, and increases or decrease a value N to or from the variable ? when the value of the variable ? is equal to or more than +N or when the value of the variable ? is equal to or less than ?N, and signals (UPFRQ) and (DNFRQ) are output to the charge pump (14).

Abstract: A Phase-Locked Loop (PLL) includes a Phase-to-Digital Converter (PDC), a programmable digital loop filter, a Digitally-Controlled Oscillator (DCO), and a loop divider. Within the PDC, phase information is converted into a stream of digital values by a charge pump and an Analog-to-Digital Converter (ADC). The stream of digital values is supplied to the digital loop filter which in turn supplies digital tuning words to the DCO. A number of types of ADCs can be used for the ADC including a continuous-time delta-sigma oversampling Digital ADC and a Successive Approximation ADC. The voltage signal on the charge pump output is a small amplitude midrange voltage signal. The small voltage amplitude of the signal leads to numerous advantages including improved charge pump linearity, reduced charge pump noise, and lower supply voltage operation of the overall PLL.

Abstract: In an embodiment, a primary charge pump and replica charge pump may be coupled to matching control mechanisms and loads. In an embodiment, the replica charge pump may produce an error current originating from charge pump timing mismatches in a steady locked loop state. The error current produced by the replica charge pump may be measured by a difference amplifier to adjust at least one current source to compensate for the error current originating from the timing mismatches. To adjust the current sources, the amplifier may cause the current source to produce an equal but opposite current to cancel the effects of the error current, resulting in a constant output voltage.

Abstract: Output driver feedback circuitry limits output slew rates across a wide range of output loads. A transition time lock loop architecture of the feedback circuitry compares a transition time pulse with a reference pulse to adjusts transition time of an output signal for various process-voltage-temperature (PVT) process corners, output voltage domains and output capacitances. Reference pulse generation circuitry provides a reference pulse in phase with the transition time pulse for each rise and fall of the output signal.

Abstract: A technique that is readily implemented in monolithic integrated circuits includes a method including generating an output clock signal during a presence of a reference clock signal based, at least in part, on a digital control value indicating a phase difference between a feedback signal of a PLL and a reference clock signal. The method includes generating the output clock signal during an absence of the reference clock signal and based, at least in part, on an average digital control word indicating an average value of a number of samples of the digital control value during the presence of the reference clock signal, the number of samples preceding the absence of the reference clock signal by a delay period. The number of samples is selected from a plurality of numbers of samples and the delay period is selected from a plurality of delay periods.

Abstract: A frequency synthesis system with self-calibrated loop stability and bandwidth, which outputs an output signal based on an input signal and includes a detector, a charge pump, a filter, a controllable oscillator and a programmable frequency divider. The detector produces a detection signal based on a logic level difference between the input signal and a feedback signal. The charge pump is connected to the detector in order to produce a control signal based on the detection signal. The filter is connected to the charge pump in order to produce a tuning signal based on the control signal. The controllable oscillator is connected to the filter in order to produce the output signal based on the tuning signal. The programmable frequency divider is connected to the controllable oscillator in order to produce the feedback signal based on the output signal. The filter is a discrete time loop filter.

Abstract: A continuous-rate clock and data recovery circuit includes a delay locked loop with a first integrator and a phase locked loop with a separate integrator. The delay locked loop and the phase locked loop are in a dual loop architecture. The first integrator is a digital accumulator that wraps upon exceeding a maximum or minimum value. The second integrator is a digital accumulator that saturates at its maximum or minimum value.

Abstract: A spread spectrum clock generation circuit and a controlling method thereof are disclosed, which provide clocks having less jitter and ideal spread spectrum and enable a reduction in circuit scale and in power consumption. To this end, a current control type modulator 19a is equipped with a current source Ia (current 4i). A charger unit CGa and a discharger unit DGa are designed such that currents i, 2i and 4i are allowed to flow, for example, by properly setting the sizes of transistors. Modulation cycles CIa to CIIIa are repeated and an output code is generated from a switching control circuit 20a according to each modulation cycle. A switching unit SSa is controlled according to the output code, thereby charging or discharging a capacitor element C1 with a charge/discharge current CDI corresponding to the output code. Hence, charge amounts and discharge amounts for all the modulation cycles CIa to CIIIa have the same value, i.e., 6i [A·clock].

Abstract: A clock and data recovery circuit injects a noise waveform into the control loop to offset the data sampling point artificially in order to induce errors. The amplitude of the injected waveform can be varied to ascertain the effect on the bit error rate (BER) so as to be able to evaluate the temporal noise margin.

Abstract: A phase detection and decision feedback equalization circuit is provided. A first latch and a second latch are coupled to an input of the circuit. A third latch and a fourth latch are respectively coupled in series to outputs of the first latch and second latch. The first and fourth latches are enabled by a clock signal, and the second and third latches are enabled by a complement of the clock signal. A first feedback circuit is configured to provide a signal output from the first latch and a first feedback signal derived from the output of the fourth latch to an input of the third latch. A second feedback circuit is configured to provide a signal output from the second latch and a second feedback signal derived from the output of the third latch to an input of the fourth latch.

Abstract: A communication system includes: a transmitter adapted to transmit a synchronizing clock and serial data synchronous with the synchronizing clock over a line at low amplitude; and a receiver adapted to receive the serial data and synchronizing clock from the transmitter. The receiver includes an amplifier adapted to amplify the received synchronizing clock of low amplitude to restore the clock to its original amplitude, a latched comparator adapted to latch the received serial data in synchronism with a reproduction clock, and a phase-locked circuit.

Abstract: A clock and data recovery (CDR) architecture which includes a frequency detector, a phase detector, a phase charge pump circuit, a frequency charge pump circuit and a voltage controlled oscillator is provided. The phase detector is configured to only include four AND gates to receive and evaluate the intermediate signals, generated by the frequency detector, and accordingly generate a phase control signal. The voltage controlled oscillator is configured to output a plurality of clock signals with different phases according to the current signals outputted from the phase and frequency charge pump circuits, and select at least one of the plurality of clock signals with different phases for sampling a data signal.

Abstract: The present disclosure provides a variable delay circuit comprising a delay circuit that includes a first delay unit and a second delay unit and delays an input signal to generate an output signal; a selection signal generation unit that detects a delay value of the delay circuit and generates a selection signal to select a delay unit for delaying the input signal from the first delay unit and the second delay unit; a first control unit that controls a delay value of the delay unit selected by the selection signal in response to a delay increase/decrease signal; and a second control unit that controls a delay value of the delay unit which is not selected by the selection signal.

Abstract: A linear phase detector includes an up/down pulse generator operating in response to received data signals and a recovered clock signal. The phase detector generates up and down pulses that have pulse widths proportional to the phase differences between transitions of the received data signals and edges of the recovered clock signal. By generating up and down pulses using a linear phase detector in proportion to a phase error, data signals are effectively recovered, even data signals with significant jitter.

Abstract: A phase locked loop includes a voltage controlled oscillator operable to generate an output signal corresponding to a reference signal in response to a control voltage signal outputted by a filter in response to a current signal, and a variable frequency divider operable to perform frequency division on the output signal using a variable divisor so as to generate a divided feedback signal. A charge pump outputs the current signal in response to a phase detecting output from a phase/frequency detector indicating phases of the divided feedback signal and the reference signal. A phase error comparator outputs, in accordance with the phase detecting output, a digital output indicating whether the divided feedback signal lags or leads the reference signal and further indicating a phase difference between the divided feedback signal and the reference signal.

Abstract: A clock and data recovery (CDR) architecture which includes a frequency detector, a phase detector, a phase charge pump circuit, a frequency charge pump circuit and a voltage controlled oscillator is provided. The phase detector is configured to only include four AND gates to receive and evaluate the intermediate signals, generated by the frequency detector, and accordingly generate a phase control signal. The voltage controlled oscillator is configured to output a plurality of clock signals with different phases according to the current signals outputted from the phase and frequency charge pump circuits, and select at least one of the plurality of clock signals with different phases for sampling a data signal.

Abstract: A computer system with a phase detector that generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector circuits receiving the first and second clock signals and generating select signals having duty cycles corresponding to the phase relationship between the clock edges of the first and second clock signals. The phase detector also includes a charge pump that receives select signals from the phase detector circuits and produces an increasing or decreasing control signal when the first and second clock signals do not have the predetermined phase relationship, and a non-varying control signal when the first and second clock signals do have the predetermined phase relationship. The delay value of a voltage-controlled delay circuit and the phase relationship between the first and second clock signals to a predetermined phase relationship are thereby adjusted.

Abstract: A system and method are provided for determining a time for safely sampling a signal of a clock domain. In one embodiment, a frequency estimate of a first clock domain is calculated utilizing a frequency estimator. Additionally, a time during which a signal from the first clock domain is unchanging is determined such that the signal is capable of being safely sampled by a second clock domain, using the frequency estimate. In another embodiment, a frequency estimate of a first clock domain is calculated utilizing a frequency estimator. Further, a phase estimate of the first clock domain is calculated based on the frequency estimate, utilizing a phase estimator. Moreover, a time during which a signal from the first clock domain is unchanging is determined such that the signal is capable of being safely sampled by a second clock domain, using the phase estimate.

Abstract: A communication device includes a communication circuit part, a transmission path for signals, a ground, a coupler electrode, and a resonance part. The coupler electrode includes an upper flat part as an electrode, a support, and a connecting portion. The support supports the upper flat part. Thus, the upper flat part faces the ground and is separately placed therefrom at a height only enough to ignore the wavelength of the signal, while having a flexible portion which is elastically deformable in the height direction. On the connecting portion, the other end of the support is connected to the transmission path. The resonance part enlarges a current flowing into the coupler electrode through the transmission path. A micro dipole is a line segment connecting between the center of accumulated electric charge in the coupler electrode and the center of mirror charge accumulated in the ground.

Abstract: A system accountably maintains an accumulated charge of a photo-detector charge well at or around a predefined level.

Abstract: Disclosed herein is a synchronization circuit including: a first phase-locked loop circuit; a second phase-locked loop circuit; a first output circuit; a second output circuit; a first detection circuit; a second detection circuit; and a control circuit.

Abstract: A serial bus clock frequency calibration system and a method thereof are disclosed herein. The system utilizes a first frequency calibration device, a second frequency calibration device and a third frequency calibration device to share the same oscillator as so to perform multi-stage clock frequency resolution calibrations for different frequency-tuning ranges. This can bring an optimal frequency resolution, greatly reduce system complexity and save element cost.

Abstract: In the following B cycles, the second frequency-divided signal fA is maintained at a low level, while the third frequency-divided signal fB is maintained at a high level. The three-modulus prescaler 13 has a frequency division value (M?1) if the pseudo random values are negative values, and a frequency division value (M+1) if the pseudo random values are positive values, in accordance with the signs of the pseudo random values outputted from the ?? modulator 8. After that, the frequency division value becomes M. A frequency division value of (MN+A+Bx) including the pseudo random value Bx is obtained in the comparison frequency divider 4. A fractional frequency division operation can be realized through ?? modulation by using the pseudo random numbers including negative values, as they are.

Abstract: A data receiver circuit includes: a clock/data recovery circuit to recover a clock and data from a received signal; a fixed pattern generation circuit to generate fixed pattern data; a first selection circuit to select and output one of the fixed pattern data generated by the fixed pattern generation circuit and recovered data recovered by the clock/data recovery circuit; a second selection circuit to select and output one of a reference clock and recovered clock recovered by the clock/data recovery circuit; and a switching circuit to make the first selection circuit output the fixed pattern data and to make the second selection circuit output the reference clock, when an input signal is lost or the clock/data recovery circuit is in a loss-of-lock state.

Abstract: Disclosed herein are embodiments of an improved built-in self-test (BIST) circuit and an associated method for measuring phase and/or cycle-to-cycle jitter of a clock signal. The embodiments of the BIST circuit implement a Variable Vernier Digital Delay Locked Line method. Specifically, the embodiments of the BIST circuit incorporate both a digital delay locked loop and a Vernier delay line, for respectively coarse tuning and fine tuning portions of the circuit. Additionally, the BIST circuit is variable, as the resolution of the circuit changes from chip to chip, and digital, as it is implemented with standard digital logic elements.

Abstract: A method of dynamically adjusting phase-chasing speed for increasing efficiency of a DLL circuit includes detecting an overall loop delay for an input clock signal in the DLL circuit, obtaining an optimal divisor according to the overall loop delay, and in the phase-locking period of the DLL circuit, dividing the frequencies of the input clock signal and a feedback clock signal corresponding to the input clock signal according to the optimal divisor.

Abstract: A delay compensation circuit for a delay locked loop which includes a main delay line having a fine delay line comprising fine delay elements and a coarse delay line comprising coarse delay elements, the main delay line being controlled by a controller, the delay compensation circuit comprising: an adjustable fine delay for modeling a coarse delay element, a counter for controlling the adjustable fine delay to a value which is substantially the same as that of a coarse delay element, a circuit for applying a representation of the system clock to the delay compensation circuit, and a circuit for applying the fine delay count from the counter to the controller for adjusting the fine delay line of the main delay line to a value which is substantially the same as that of a coarse delay element of the main delay line.

Abstract: A data receiver identifies an alignment symbol in a parallel data stream including encoded symbols, generates a bit order indicator indicating a bit order of the alignment symbol identified in the parallel data stream, and generates a symbol stream including the encoded symbols. Further, the data receiver decodes symbols in the symbol stream and generates a bit polarity indicator indicating a bit polarity of the parallel data stream based on the decoded symbols. Additionally, the data receiver generates a formatted symbol stream having a predetermined bit order and a predetermined bit polarity, based on the symbol stream, the bit order indicator, and the bit polarity indicator. In some embodiments, the data receives a serial data stream and generates the parallel data stream by deserializing data in the serial data stream.

Abstract: This invention discloses a phase interpolation controller for a clock and data recovery circuit receiving an indication of a phase relationship between a first and a second signal, the phase interpolation controller comprises a plurality of serially coupled bi-directional shift-registers, wherein when the received indication indicates the first signal is ahead of the second signal in phase, the plurality of serially coupled bi-directional shift-registers shifts in one of the bi-directions, and when the received indication indicates the first signal is behind the second signal in phase, the plurality of serially coupled bi-directional shift-registers shifts in the other of the bi-directions.

Abstract: The present disclosure provides a phase comparator including, a first latch, a second latch, a first detection circuit, a second detection circuit, and a charge-pump circuit having the function of a changeover switch.

Abstract: An example method includes receiving a phase correction signal representing a phase difference between a source signal and a reference signal, generating a first control voltage from the phase correction signal using a charge pump circuit, generating a second control voltage from the phase correction signal in response to a digitally filtered version of the phase correction signal, wherein the second control voltage corrects for an offset error present in the first control voltage, calculating a VCO control signal based on a linear combination of the first and the second control voltages; and generating the source signal in response to the VCO control signal.

Abstract: A method of achieving reduced modulation range requirement in a Digitally Controlled Oscillator (DCO) which is deployed as part of a DRP (Digital Radio Processor) and tuned to a tuning frequency range having operating-channel center-frequencies, wherein phase difference between consecutive samples is termed as FCW (Frequency Control Word), uses the steps of digitally modifying and limiting the FCW so that the FCW does not exceed known FCW thresholds, e.g., chosen from ?/2, ?/4, ?/8, and redistributing the FCWs while maintaining a cumulative sum of phases and without significant EVM (Error Vector Magnitude) degradation. The FCW threshold can be chosen arbitrarily and need not be in the form of ?/2n. The method uses a FCW limiting algorithm which reduces supply voltage sensitivity of the DCO and enables significant reduction in area of capacitor bank which would be otherwise needed.

Abstract: A 4× over-sampling data recovery system consists of a charge pump PLL, a 4× over-sampler, a data regenerator and a digital PLL. The charge pump PLL receives a clock signal and generates a plurality of multiplicative clock signals in response to the clock signal. The 4× over-sampler samples a serial data to generate a M-bit signal according to the plurality of multiplicative clock signals, wherein each bit in the serial data is sampled for four times. The data regenerator sequentially receives and combines two M-bit signals to generate a (M+N)-bit signal. The digital PLL divides the (M+N)-bit signal into (N+1) groups of M-bit data and selects a designated M-bit data from the (N+1) groups of M-bit data to generate a P-bit recovery data.

Abstract: A parallel-serial converter includes a converter circuit that converts parallel data into serial data; a first sampling circuit that samples, according to a first clock signal, the serial data output from the converter circuit; a second sampling circuit that samples, according to a second clock signal that is an inverse of the first clock signal, replica data that is synchronized with the serial data; a third sampling circuit that samples, according to plural third signals respectively having different phases, output from the second sampling circuit; and a control circuit that controls sampling timing of the first sampling circuit, based on each output from the third sampling circuit.

Abstract: In accordance with an embodiment of the present disclosure a phase-locked loop comprises a voltage controlled oscillator (VCO) configured to generate an output signal based on an input reference signal. The phase-locked loop further comprises a first charge pump communicatively coupled to a control input of the VCO and configured to generate, for a duration of time following occurrence of an event, a first control signal. The first control signal is independent of the output signal and is for causing the output signal to have a first frequency based on a second frequency of the input reference signal. The phase-locked loop further comprises a second charge pump communicatively coupled to the control input of the VCO. The second charge pump is configured to generate, after the duration of time, a second control signal.