Abstract: Systems and methods for synthesis of a modulated RF signal using a variety of modulation schemes are described. An embodiment includes a direct frequency synthesizer with frequency modulated continuous wave (FMCW) modulation that includes: a high speed BAW resonator that generates a frequency signal; a BAW oscillator that receives the frequency signal and generates an output BAW clock signal (BAW CLK); a frequency and phase estimation circuit that receives a reference clock signal from a reference clock (REF CLK) and the BAW CLK and generates a frequency error and a phase error; a frequency chirp generator that receives chirp parameters, a chirp sync signal and generates a nominal frequency control word (FCW); and a high speed digital to analog converter (HS DAC) that receives the BAW CLK and the codeword and outputs an analog signal.

Abstract: A method for processing clock drift implemented by a first network element includes: receiving a first notification message transmitted by a second network element, the first notification message including a first clock difference between a first clock domain and a second clock domain acquired by the second network element, transmission of the first notification message being triggered by a clock drift between the first clock domain and the second clock domain being greater than a drift amplitude value, which is a maximum value of a change amplitude of a clock difference between the first and second clock domain; determining first time sensitive communication assistance information (TSCAI) according to the first clock difference; and transmitting the first TSCAI to a radio access network (RAN) device, the first TSCAI being used by the RAN device to perform time control on a data stream in the first clock domain.

Abstract: In an embodiment, a method includes: receiving a first plurality of digital codes from a time-to-digital converter (TDC); TDC; generating a coarse histogram from the first plurality of digital codes; detecting a peak coarse bin from the plurality of coarse bins; after receiving the first plurality of digital codes, receiving a second plurality of digital codes from the TDC; and generating a fine histogram from the second plurality of digital codes based on the detected peak coarse bin, where a fine histogram depth range is narrower than a coarse histogram depth range, where a lowest fine histogram depth is lower or equal to a lowest coarse peak depth, and where a highest fine histogram depth is higher or equal to a highest coarse peak depth.

Abstract: In order to synchronize the respective local network time of participants of a real-time network, wherein the participants are connected to one another via ports, the participants transmit, preferably cyclically, synchronization packets to connected participants, wherein one participant of the real-time network is designated as the synchronization master, and using the synchronization packets, the local network time of the other participants is synchronized with the local network time of the synchronization master.

Abstract: A method and system for managing transcoding of data in a stream that includes identifying an input source change for the stream with a new input source type, and adding a decoder for the new input source type, the decoder configured to output for a respective encoder in a transcoder pipeline.

Abstract: A Controller Area Network (CAN) transmitter, in which transitions between output levels are smoothed through use of multiple Digital to Analog Converters (DACs) switched by a multi-phase clock signal. Example embodiments include a CAN transmitter (100) comprising: an oscillator (101) configured to generate a clock signal having n equally spaced phases (clk_0, clk_120, clk_240), where n is an integer greater than 1; n Digital to Analog Converters, DACs (1021-3), each DAC having an input connected to one of the n phases of the clock signal and to a common data input line, each DAC being configured to provide an output signal that transitions between first and second output levels in M discrete steps upon being triggered by a transition of a signal on the data input line synchronized with the one of the n phases of the clock signal; and an output amplifier stage (103) configured to provide a differential CAN output signal from a combination of output signals from each of the n DACs (1021-3).

Abstract: A clock-and-data recovery circuit for serial receiver includes a jitter meter and an adaptive loop gain adjustment circuitry. The clock-recovery circuitry phase aligns a clock signal to the incoming data. A jitter meter provides a measure of jitter, while adaptation circuitry uses the measure to adjust the clock-recovery circuitry in a manner that reduces clock jitter. The jitter measure can be a ratio of errors associated with different inter-symbol slew rates.

Abstract: A microcontroller system includes a processing unit supporting at least one near or sub Vt circuit and a plurality of memory blocks, each memory block connected to a DMA controller and independently power controlled. A power control system uses power gates to power control at least the memory blocks. In some embodiments, a wake-up interrupt controller is connected to the power control system and a voltage regulator system is used to supply voltage to separate power domains, with the voltage regulator systems controlled at least in part by power gates operated by the power control system. A plurality of clocks can be connected to define clock domains associated with separate power domains.

Abstract: An optical system includes a transmitter including transmitter circuitry configured to cause transmission of a transmitted optical signal over a fiber link on an X polarization and a Y polarization; and a receiver including receiver circuitry configured to receive a received optical signal from the fiber link on the X polarization and the Y polarization, wherein the transmitter circuitry is configured to cause State of Polarization (SOP) changes on the X polarization and the Y polarization for a test of the fiber link. The transmitter circuitry and the receiver circuitry are built-in with the transmitter and the receiver, respectively, for performance of the test.

Abstract: Present disclosure describes the techniques for regaining synchronization between the RPD and the PTP server, without resetting RPD, in the event of run time-phase jump experienced at RPD. To do so, said technique discloses identifying a run time phase jump event at a remote Physical device (RPD) and initiating an Upstream Channel Descriptor (UCD) refresh procedure to reconnect the RPD with Precision Time Protocol (PTP) server.

Abstract: Optimal determination of a Wireless Local Area Network (WLAN) sounding method and system may be provided. An Access Point (AP) selects a subchannel for the partial sounding. The AP then sounds the selected subchannel. A client station responds with Channel State Information (CSI). The AP can receive the CSI, from the client station, in response to the sounding. Based on the CSI from the selected subchannel, the AP extrapolates the CSI to determine predicted CSI for a wider bandwidth channel.

Abstract: A radio node may calculate one or more performance metrics based on measured satellite signals, which are associated with a global positioning system, or wireless signals that are associated with a cellular-telephone network. Then, the radio node may determine, based on the one or more performance metrics, whether the radio node is a synchronization master in a cluster of radio nodes. When the radio node is the synchronization master, the radio node may provide information intended for a computer specifying that the radio node is the synchronization master and the one or more performance metrics. In response, the radio node may receive a synchronization request associated with another radio node in the cluster. Furthermore, the radio node may provide the synchronization information intended for the other radio node, where the synchronization information specifies time, frequency, and phase synchronization for at least the cluster.

Abstract: A multi-member Bluetooth device for communicating data with a source Bluetooth device, wherein the source Bluetooth device acts as a master in a first piconet. The multi-member Bluetooth device includes a main Bluetooth circuit and an auxiliary Bluetooth circuit. The main Bluetooth circuit acts as a slave in the first piconet, and acts as a master in a second piconet. The auxiliary Bluetooth circuit acts as a slave in the second piconet. The main Bluetooth circuit generates a first slave clock and a second main clock synchronized with a first main clock generated by the source Bluetooth device, and samples a first audio data to be playback. The auxiliary Bluetooth circuit generates a second slave clock and a third slave clock synchronized with the second main clock, and samples a second audio data to be playback.

Abstract: An electronic device is disclosed. The electronic device comprises a first clock configured to operate at a frequency. First circuitry of the electronic device is configured to synchronize with the first clock. Second circuitry is configured to determine a second clock based on the first clock. The second clock is configured to operate at the frequency of the first clock, and is further configured to operate with a phase shift with respect to the first clock. Third circuitry is configured to synchronize with the second clock.

Abstract: An apparatus for time management of a peripheral device is disclosed. A peripheral interface circuit receives information from a host circuit over a peripheral bus, the host circuit maintaining a global timebase in accordance with a first clock signal within a first clock domain. The peripheral interface circuit maintains, based om a second clock signal within a second clock domain, a first local timebase correlated to the global timebase. A peripheral control circuit operates in a third clock domain and maintains a second local timebase based on the first. The peripheral interface circuit determines phase and frequency differences between the second and third clock signals in determining a correlation between the second and first local timebases. A peripheral logic circuit in the third clock domain performs, operations that utilize a timestamp from the second local timebase, which accounts for correlation with the first local timebase.

Abstract: A network transceiver device is provided, including at least two variable gain amplifiers (VGAs), and at least two sets of analog digital converters (ADCs), each set including ADCs coupled to an output of one of the VGAs, the sets being arranged in VGA-specific channels. The device includes a plurality of feed-forward equalizers (FFEs), each FFE being coupled to receive an output of one of the ADCs in one of the VGA-specific channels. Each FFE is configured to adaptively equalize the output received from the ADCs utilizing a first equalization coefficient subset with coefficient values that are common to all FFEs, and a second equalization coefficient subset that is channel specific and that has a first set of coefficient values for a first VGA-specific channel and a second set of coefficient values for a second VGA-specific channel, the sets of coefficient values being computed independently.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a base station (BS) may determine at least one of a variable random access response (RAR) window start time, a variable maximum quantity of slots for an index of a first slot of a physical random access channel occasion, or scheduling information related to one or more variable delays for an uplink transmission. The BS may transmit, to a user equipment, at least one of information that identifies the RAR window start time, information that identifies the variable maximum quantity of slots, or the scheduling information. Numerous other aspects are provided.

Abstract: A memory device includes a data storage circuit configured to store, when a write operation is performed, a first internal write data and a second internal write data in a memory cell array which is accessed by an internal address, and output, when a read operation is performed, data stored in a memory cell array which is accessed by the internal address, as internal read data; and a flag generation circuit configured to generate a flag for controlling generation of a data strobe signal, based on the internal read data.

Abstract: Methods and systems are described for receiving N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2, generating a plurality of partial phase error signals, each partial phase error signal formed at least in part by comparing (i) a respective phase of the M phases of the reference signal to (ii) a respective phase of the N phases of the local clock signal, and generating a composite phase error signal by summing the plurality of partial phase error signals, and responsively adjusting a fixed phase of a local oscillator using the composite phase error signal.

Abstract: A receiving device includes a first sampling circuit extracting first binary data from a first signal based on a first edge timing of a first clock signal. The receiving device includes a second sampling circuit extracting second binary data from the first signal based on the first edge timing, and further extracting third binary data from the first signal based on a second edge timing of a second clock signal having a phase delayed from a phase of the first clock signal. The receiving device includes a circuit outputting a second signal indicating a phase shift direction of a third clock signal. The receiving device includes a circuit outputting waveform data based on the first binary data and the second binary data or the third binary data. The second sampling circuit selects either the second binary data or the third binary data based on the second signal.

Abstract: Disclosed herein is an apparatus that includes a first circuit configured to measure a first time period from a first active edge of one of plurality of internal signals to a second active edge of one of the plurality of internal signals, and a second circuit configured to compare the first time period with a second time period to generate an alert signal.

Abstract: A network device may receive, from a timing source of a network, timing information. The network device may identify a client device to which the timing information is to be provided, wherein the network device provides an interface between the client device and the network. The network device may select a virtual network address to associate with a timing agent of the network device, wherein the virtual network address is within an address range that is reachable by the client device. The network device may provide to the client device, and via a network layer communication, a timing control packet comprising the timing information, wherein the timing control packet identifies the virtual network address as a source network address of the timing control packet, and wherein the timing information is to be used by the client device to update a clock of the client device.

Abstract: An electronic device is disclosed. The electronic device comprises a first clock configured to operate at a frequency. First circuitry of the electronic device is configured to synchronize with the first clock. Second circuitry is configured to determine a second clock based on the first clock. The second clock is configured to operate at the frequency of the first clock, and is further configured to operate with a phase shift with respect to the first clock. Third circuitry is configured to synchronize with the second clock.

Abstract: A method, an apparatus, and a computer program product for real-time processing in wireless communications systems. An interruption of processing of one or more first symbol packets at one or more wireless communication components is detected. A predetermined period of time for a delay in processing of one or more second symbol packets is determined. Processing of one or more second symbol packets is delayed until expiration of the predetermined period of time. Processing of one or more second symbol packets is then performed.

Abstract: Techniques are presented for receiving Quadrature Amplitude Modulated (QAM) symbols from a transmitter via a transmission path. In one example, a demodulator is configured to down-convert an incoming Radio Frequency (RF) signal to a baseband signal and convert the baseband signal to digital samples, and output the digital samples. A demapper is configured to receive the digital samples output from the demodulator and output data encoded in QAM symbols. The demapper is further configured to: determine from a constellation of QAM symbols a subset of QAM symbols that a digital sample from the demodulator may represent; apply an offset to each QAM symbol in the subset of QAM symbols of the constellation to result in a subset of offset QAM symbols; determine which QAM symbol in the subset of offset QAM symbols the digital sample most likely represents; and output data representing a determined QAM symbol.

Abstract: A method, an apparatus, a system, and a computer program product for radio synchronous status messaging between communications units in wireless communications systems. A change of status event by one or more first communications devices is detected. A message indicative of the detected change of status event is generated. The generated message is transmitted to one or more second communications devices.

Abstract: In order to provide flexible scaling and dynamic reconfiguration, a wireless local area network controller includes a virtual dataplane with one or more virtual machines. These virtual machines pre-calculate processing parameters for packets in a data flow. For example, the pre-calculated processing parameters may include: encapsulation parameters, quality-of-service parameters and priority parameters. Subsequently, when one of the virtual machines receives a packet in the data flow on an input port, the virtual machine modifies information in a header of the packet based on one or more of the pre-calculated processing parameters and information associated with the data flow (which specifies the one or more pre-calculated processing parameters). Then, the virtual machine transmits the packet on an output port. In this way, the virtual machine maintains a fixed inter-packet time between packets in the data flow.

Abstract: In a signal processing arrangement a first and a second input signal associated with the rotating object are received at signal inputs. Amplitude processing blocks are connected to the signal inputs and each have an adjustable gain. A trigonometric processing block has inputs coupled to outputs of the second amplitude processing blocks via respective signal paths. The trigonometric processing block is configured to determine a magnitude value and a phase value based on signals at its inputs. The signal processing arrangement further has compensation blocks configured to store values at the inputs of the trigonometric processing block as respective peak values, when the phase value assumes a respective phase value. A gain value is determined by applying a respective regulation function to respective amplitude errors being based on the peal values, and the gains of the amplitude processing blocks are adjusted based on the respective gain values.

Abstract: Provided are an apparatus capable of generating a stream clock having the same frequency as a frequency in a normal mode, in a panel self-refresh mode and an embedded DisplayPort system including the same. The embedded DisplayPort system includes a stream clock generator. The stream clock generator may include an internal oscillator configured to oscillate an internal clock, a frequency regulator configured to compare frequencies of the internal clock and a link symbol clock, generate control signals, and adjust a frequency of the internal clock using the control signals, wherein the link symbol clock is reconstructed from stream data of the embedded DisplayPort system, and a phase-locked loop configured to generate a stream clock using the internal clock and lock a phase of the stream clock to a phase of the internal clock.

Abstract: The present disclosure provides a clock data recovery apparatus. The clock data recovery apparatus includes a phase detection circuit, a digital filter, a phase-interpolating circuit and an oscillator circuit. The phase detection circuit receives and samples a data signal according to multiple reference clock signals having different phases, to generate a phase detection result. The digital filter performs accumulation on the phase detection result, to generate a phase-adjusting signal. The phase interpolator circuit performs phase adjustment on a source clock signal according to the phase-adjusting signal, in order to generate an injection clock signal. The oscillator circuit generates the reference clock signals according to the injection clock signal, in which the phases of the reference clock signals follow the phase of the injection clock signal.

Abstract: This disclosure describes techniques for delivering high-accuracy and high-precision clock synchronization in heterogeneous distributed computer clusters. For example, the disclosure describes a synchronization engine that sets efficient clock synchronization processes based on a cluster node's characteristics, pricing, precision, geolocation, and/or cluster topology, while in some cases using a combination of master clock data with internal atomic clocks of computers. The techniques described herein integrate the synchronization engine into a time synchronization process that may provide stability, versatility, precision and cost balance using technical improvements for characterizing timing system delivery channels.

Abstract: Examples described herein provide a computer-implemented method that includes initiating a logic built-in self-test (LBIST) of a device under test (DUT). The method further includes performing latch state counting using a multiple input signature register (MISR) of the DUT, the performing responsive to the MISR being in a counter mode. The method further includes performing a latch transition counting of latches of the DUT using the MISR of the DUT and a storage latch, the performing responsive to the MISR being in the counter mode. The method further includes performing a latch count comparison by comparing an output of the MISR responsive to the MISR being in the counter mode to an output of a count compare register, the output of the count compare register representing a desired MISR state.

Abstract: Circuitry and methods for receiving data that may be compliant with a specific protocol is discussed. The described systems may be employed to implement a physical media access (PMA) sublayer and/or physical coding sublayer (PCS) for high-speed Ethernet protocols. Embodiments described herein may have reduced circuitry footprint that may be achieved by the use of a single recovered clock to drive the operations of PCS circuitry. Efficient use of components may also be achieved by the use of smaller-sized words for processing by the PCS circuitry. The circuitry may process the smaller-sized words by implementing pipelined circuitry. Implementations that employ programmable circuitry, hardened circuitry, or hybrid implementations are also discussed.

Abstract: Novel techniques are described for lock-free sharing of a circular buffer. Embodiments can provide shared, lock-free, constant-bitrate access by multiple consumer systems to a live stream of audiovisual information being recorded to a circular buffer by a producer. For example, when a producer system writes a data stream to the circular buffer, the producer system records shared metadata. When a consumer system desires to begin reading from the shared buffer at a particular time, the shared metadata is used to compute a predicted write pointer location and corresponding dirty region around the write pointer at the desired read time. A read pointer of the consumer system can be set to avoid the dirty region, thereby permitting read access to a stable region of the circular buffer without relying on a buffer lock.

Abstract: A clock and data recovery apparatus is provided that includes a sampling circuit, a storage circuit and a determining circuit. The sampling circuit includes sampling units each sampling a received data according to one of reference clock signals to generate a sampling result. The storage circuit includes FIFO storage units configured to store the sampling result of the received data corresponding to different time spots. The determining circuit is configured to set a certain number of received data as a reference data pattern, to adjust a starting position of a sampling window according to a transition point of sampled values within the reference data pattern when only one data transition exists therein and adjust a length of the sampling window according to an amount of high state sample points of the sampled values within the reference data pattern when more than one data transitions exist therein.

Abstract: The disclosed systems, structures, and methods are directed to a multi-level multi-mode transmitter, employing a first pre-driver configured to receive M-parallel data streams and to convert the M-parallel data streams into a serial data stream, a first voltage-driver configured to operate on the single data stream and to provide a voltage in accordance with the single data stream, a second pre-driver configured to receive and process the M-parallel data streams in accordance with at least one of the following modes: moderate impedance (Z) post-cursor mode, moderate Z pre-cursor mode, low Z high-swing mode, low Z post-cursor mode, and low Z pre-cursor mode, and convert the processed M-parallel data streams into a first serial stream and a second serial stream and a second voltage-driver configured to operate on the first serial stream and the second serial stream and to provide a voltage.

Abstract: The present invention is directed to systems and methods for reducing noise levels by harmonization in a DCC-DAS using smart weighted aggregation of noise and signal resources to achieve an optimal signal to noise ratio in varying traffic and interference conditions.

Abstract: An integrated circuit includes a master-slave storage element having a data input coupled to receive a data signal and an asymmetrical clock generator coupled to provide an asymmetrical clock signal to the master-slave storage element. A first phase of the asymmetrical clock signal is configured for inhibiting intermediate data signal transitions from propagating through the master portion of the master-slave storage element.

Abstract: Circuits and methods for performing a clock and data recovery are disclosed. In one example, a circuit is disclosed. The circuit includes an FSM. The FSM includes: a first accumulator, a second accumulator, and a third accumulator. The first accumulator is configured to receive an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle, to accumulate input phase codes for different FSM cycles, and to generate a first order phase code at each FSM cycle. The second accumulator is coupled to the first accumulator and configured to accumulate the input phase codes and first order phase codes for different FSM cycles, and to generate a second order phase code at each FSM cycle. The third accumulator is coupled to the second accumulator and configured to accumulate the input phase codes and second order phase codes for different FSM cycles, and to generate a third order phase code at each FSM cycle.

Abstract: Generating a composite interpolated phase-error signal for clock phase adjustment of a local oscillator by forming a summation of weighted phase-error signals generated using a matrix of partial phase comparators, each of which compare a phase of the local oscillator with a corresponding phase of a reference clock.

Abstract: A method operates by receiving a first voltage, which is a logical signal; converting the first voltage into a second voltage using a first inverting buffer with a first pull-up resistance and a first pull-down resistance; and converting the second voltage into a third voltage using a second inverting buffer with a second pull-up resistance and a second pull-down resistance, wherein: the first pull-up resistance, the first pull-down resistance, the second pull-up resistance, the second pull-down resistance are all tunable, and a difference between the first pull-up resistance and the first pull-down resistance is approximately equal to a difference between the second pull-down resistance and the second pull-up resistance.

Abstract: A clock timing recovery method for determining a clock timing of an input signal is described, wherein the input signal is generated by a signal source, comprising: receiving the input signal; determining signal edges of the input signal based on the received input signal; determining at least a first clock timing model parameter; determining at least one jitter component of the input signal; and determining a clock timing error associated with the at least one jitter component, wherein the clock timing error is determined based on the determined signal edges, the determined first clock timing model parameter and the determined jitter component. Moreover, a measurement instrument is described.

Abstract: Devices and methods for generating a bias voltage for a transceiver operating in time division multiplexing operation, and corresponding transceivers are provided. In this case, the bias voltage is controlled in guard intervals between transmission and reception of signals by the transceiver.

Abstract: A signal analysis method for recovering a clock signal from an input signal is described. The input signal comprises a symbol sequence, wherein each symbol has one of N different amplitude values, and wherein N is an integer bigger than 1. The signal analysis method comprises the following steps: The input signal is received. Transition times of the input signal are determined, wherein the input signal respectively crosses one of several predetermined amplitude thresholds at the transition times. The transition times are transformed into one reference symbol period, thereby obtaining transformed transition times. The clock signal is determined based on the transformed transition times. Further, a signal analysis module for recovering a clock signal from an input signal is described.

Abstract: Apparatus and associated methods relate to a dynamic lane-to-lane skew reduction technique having (a) a clocking architecture configured to provide a corresponding first delayed clock signal and a corresponding second delayed clock signal through a first and a second plurality of routing traces, respectively, and (b) a number of skew compensation circuits configured to process the corresponding first delayed clock signal and the corresponding second delayed clock signal to generate a corresponding user clock signal for a corresponding lane of a transmitter. In an illustrative example, a first routing trace may transmit a first delayed clock signal in a direction opposite to a second routing trace transmitting a second delayed clock signal. By implementing the technique, each transmitter lane may receive a corresponding user clock signal having substantially the same delay relative to a reference clock signal such that dynamic lane-to-lane skew may be advantageously reduced.

Abstract: A device includes a receiver configured to receive an encoded bitstream from a second device. The encoded bitstream includes a temporal mismatch value. The device also includes a decoder configured to decode the encoded bitstream to generate a first signal and a second signal. Based on the temporal mismatch value, the decoder is configured to map one of the first signal or the second signal as a decoded target channel. The decoder is also configured to perform a shift operation on the decoded target channel based on the temporal mismatch value to generate an adjusted decoded target channel. The device also includes an output device configured to output a first output signal and a second output signal. The second output signal is based on the adjusted decoded target channel.

Abstract: Systems and methods configured to cancel spurs in a phase locked loop (PLL) system are provided. A method configured to cancel spurs in a PLL system includes receiving a PLL signal from the PLL system; determining an estimated spur frequency of a spur in the received PLL signal based on the received PLL signal; and canceling the spur in the received PLL signal based on the estimated spur frequency.

Abstract: A method of communication in a Bluetooth Low Energy network is presented. The network has a master device and a plurality of slave devices between a first slave device and a second slave device. The method steps include: sending from the master device to the first slave device a synchronisation delay parameter; and sending from the master device to the second slave device the synchronisation delay parameter and a relative offset parameter. At the second slave device, the method steps include determining a synchronisation time point by adding the relative offset parameter to the synchronisation delay parameter. At the synchronisation time point, the method steps include waking the first and second slave devices and sending a communication from the first slave device to the second slave device.

Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

Abstract: Apparatuses and methods for reducing a number of command shifters are disclosed. An example apparatus includes an encoder circuit, a latency shifter circuit, and a decoder circuit. The encoder circuit may be configured to encode commands, wherein the commands are encoded based on their command type and the latency shifter circuit, coupled to the encoder circuit, may be configured to provide a latency to the encoded commands. The decoder circuit, coupled to the latency shifter circuit, may be configured to decode the encoded commands and provide decoded commands to perform memory operations associated with the command types of the decoded commands.