Phase Displacement, Slip Or Jitter Correction Patents (Class 375/371)
  • Patent number: 10805064
    Abstract: A system includes an optical transmitter including a transmitter Phase Lock Loop (PLL) circuit; an optical receiver connected to the optical transmitter and including a receiver PLL circuit; and circuitry configured to inject a test stimulus to a clock causing jitter in one of the transmitter PLL circuitry and the receiver PLL circuit, wherein the test stimulus is set for characterizing the jitter tolerance of optical receiver. As well, a circuit that injects SOP transient at the transmitter is included. It is configured to test the tolerance of optical receiver to handle fast change in the SOP state. The optical receiver is configured to determine if the system is operational at a jitter value due to the test stimulus based on compliance to one or more thresholds including any of a target Bit Error Rate, a Forward-Error-Correction (FEC) hit, and a jitter Root Mean Square (RMS).
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: October 13, 2020
    Assignee: Ciena Corporation
    Inventors: Sadok Aouini, Naim Ben-Hamida, Ahmad Abdo, Timothy James Creasy, Lukas Jakober, Yalmez M. A. Yazaw, Shahab Oveis Gharan
  • Patent number: 10771346
    Abstract: A method monitors a data transmission network having a plurality of devices connected to one another over fixedly prescribed signal transmission paths, for anomalies. One of the devices is a master device that has a counter and a trigger apparatus, by which a prescribed signal feature of a signal is acquired, and upon the acquisition, a master counter state corresponding thereto is read. The method provides for an evaluation apparatus to determine, under predetermined conditions, a setpoint value of at least one network-specific parameter defined by a physical property of the network, before an actual value of the network-specific parameter is determined from a difference between the master counter state and a further counter state, and an anomaly is indicated if a predetermined deviation criterion between the actual value and the setpoint value is met.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: September 8, 2020
    Assignee: Conti Temic microelectronic GmbH
    Inventors: Uli Joos, Florian Gerster, Lorenz Lieder
  • Patent number: 10763866
    Abstract: An electronic circuit includes a clock recovery circuit that generates a first reference clock signal based on first reception data and generates a second reference clock signal based on second reception data received after the first reception, a sampling clock generator that generates a sampling clock signal having a phase based on a phase difference between the first reference clock signal and the second reference clock signal, and a sampler that recovers the second reception data based on the generated sampling clock signal.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: September 1, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyungho Ryu, Hansu Pae, Kilhoon Lee, Jaeyoul Lee, Jung-Pil Lim, Hyunwook Lim
  • Patent number: 10739874
    Abstract: In one embodiment, a computer-readable non-transitory storage medium embodies logic that is configured when executed to determine a first correlation between first consecutive edges of a synchronization signal and a pre-determined coefficient vector. The logic is further configured when executed to determine a second correlation between second consecutive edges of the synchronization signal and the pre-determined coefficient vector and synchronize one or more timings for communication between a stylus and a device based at least in part on the first and second correlations.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: August 11, 2020
    Assignee: Wacom Co., Ltd.
    Inventors: Vemund Bakken, Eivind Holsen
  • Patent number: 10701695
    Abstract: The present disclosure is a novel utility of a software defined radio (SDR) based Distributed Antenna System (DAS) that is field reconfigurable and support multi-modulation schemes (modulation-independent), multi-carriers, multi-frequency bands and multi-channels. The present disclosure enables a high degree of flexibility to manage, control, enhance, facilitate the usage and performance of a distributed wireless network such as flexible simulcast, automatic traffic load-balancing, network and radio resource optimization, network calibration, autonomous/assisted commissioning, carrier pooling, automatic frequency selection, frequency carrier placement, traffic monitoring, traffic tagging, pilot beacon, etc.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: June 30, 2020
    Assignee: DALI WIRELESS, INC.
    Inventors: Paul Lemson, Shawn Patrick Stapleton, Sasa Trajkovic, Albert S. Lee
  • Patent number: 10644706
    Abstract: A data and clock recovery circuit includes a first selecting circuit, a high speed phase detector, a low speed phase detector, a charge pump, a voltage control oscillator and a frequency divider. The high speed phase detector generates a first phase difference signal according to the first reference clock signal and a divided clock signal or according to the data signal and the divided clock signal. The low speed phase detector generates a second phase difference signal according to a second reference clock signal and the divided clock signal. The charge pump generates a control voltage according to the first phase difference signal or the second phase difference signal. The voltage control oscillator receives the control voltage, and generates a recovered clock signal. The frequency divider receives the recovered clock signal, and generates the divided clock signal.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: May 5, 2020
    Assignee: Faraday Technology Corp.
    Inventors: Young-Bok Kim, Andrew Chao
  • Patent number: 10644870
    Abstract: A clock recovery system includes: a sampler that samples reception data with 2N phase clocks and outputs 2N×M sampling signals; a data selector that selects n×M recovery signals from the 2N×M sampling signals and outputs the n×M recovery signals; a phase comparator that outputs, for each of the n×M recovery signals, a phase comparison signal based on the recovery signal, a first sampling signal sampled with a first clock that leads by one or more phases from a sampling clock, and a second sampling signal sampled with a second clock that delays by one or more phases from the sampling clock; a controller that designates n based on a data rate of the reception data; and a multiphase clock generator that generates and outputs the 2N phase clocks based on the phase comparison signal and n.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: May 5, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Akinori Shinmyo, Syuji Kato
  • Patent number: 10594469
    Abstract: The present application describes a computer-implemented method for frequency hopping including configuring a radio front end to operate on a first frequency; receiving a transmit signal in a first path in the radio front end; amplifying a transmit signal in the first path; phase shifting the transmit signal in a second path in the radio front end, the second path being different from the first path; coupling the amplified transmit signal to a third path in the radio front end; coupling the phase-shifted transmit signal in the second path to the amplified transmit signal in the third path to form a carrier-cancelled signal in a fourth path in the radio front end in the radio front end; phase shifting the carrier-cancelled signal in the fourth path; coupling the phase-shifted carrier-cancelled signal in the fourth path to the amplified transmit signal in the first path; and reconfiguring the radio front end to operate on a second frequency.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: March 17, 2020
    Inventors: Alan Scott Brannon, Riley Nelson Pack, Benjamin Joseph Baker
  • Patent number: 10588080
    Abstract: A digital signal processing device of a base station configured to process down-link signals in a wireless communication system employing orthogonal frequency division multiple access (OFDMA) and a method of processing data in the device are provided. The device includes a clock controller configured to monitor whether a signal is allocated to an input and control a frequency of clocks to have a first or second characteristic based on the monitored result, and a data processor configured to process the input, and synchronize with the clock controlled by the clock controller.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: March 10, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yonghae Choi, Hanseok Kim, Seongyong Park, Jeongjae Won, Junsung Lee
  • Patent number: 10575272
    Abstract: In the present invention, a method for synchronizing frequency and time in a wireless communication system and an apparatus for supporting the same are disclosed. Particularly, a method for synchronizing frequency and time performed by a terminal in a wireless communication system may include receiving a specific signal including a PSS, compensating the specific signal with at least one time offset candidate, generating at least one first differentiation value, generating at least one second differentiation value, calculating a cross correlation value between the at least one first differentiation value and the at least one second differentiation value, and estimating a time offset and a frequency offset of the PSS based on a time offset candidate that corresponds to a greatest cross correlation value among at least one cross correlation value calculated for at least one time offset candidate.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: February 25, 2020
    Assignee: LG ELECTRONICS INC.
    Inventors: Seokmin Shin, Hyunsoo Ko, Bonghoe Kim, Byounghoon Kim
  • Patent number: 10545746
    Abstract: In a dynamic computing environment, it is a nontrivial task to verify code running in the environment because most approaches to software similarity require extensive and time-consuming analysis of a binary, or the approaches fail to recognize executables that are similar but nonidentical. A biosequence-based method for quantifying similarity of executable binaries is used to identify allowed codes in a real-world multi-user environment.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: January 28, 2020
    Assignee: Battelle Memorial Institute
    Inventors: Elena S. Peterson, Christopher S. Oehmen, Aaron R. Phillips, Darren S. Curtis
  • Patent number: 10547475
    Abstract: A receiver device includes circuitry and memory. The circuitry converts an input signal into a data signal that includes data symbols transmitted in successive unit intervals (UIs), determines a first threshold associated with a first symbol type, adjusts a gain of the receiver device such that an average amplitude of data signal samples, when receiving data symbols having the first symbol type, corresponds to the first threshold, determines a second threshold that corresponds to an average amplitude of the data signal samples when data symbols of a current UI have the first symbol type and data symbols of a first UI, at a first determined time distance from the current UI, have a second symbol type, and computes, as a first cursor value associated with the first UI, a first difference between the first threshold and the second threshold, multiplied by a first constant.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: January 28, 2020
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventor: Mathieu Gagnon
  • Patent number: 10504552
    Abstract: A plurality of kinds of LPCM signals/compression digital audio signals is switched to one another in transmission, thereby enabling audio reproduction to be satisfactorily carried out. A digital audio signal is transmitted to an external apparatus through a predetermined transmission path. Information associated with the digital audio signal to be next transmitted is added to the digital audio signal which is currently being transmitted. For example, first metadata exhibiting a transmission frequency of the digital audio signal, and second metadata exhibiting a data type of the digital audio signal are contained in the information.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: December 10, 2019
    Assignee: SONY CORPORATION
    Inventor: Gen Ichimura
  • Patent number: 10505549
    Abstract: A PLL includes a controlled oscillator, a phase accumulator to measure the controlled oscillator output phase, a phase predictor to calculate the required output phase, and a phase subtractor to calculate the phase difference or phase error. The phase accumulator includes a fast counter and a low-power counter, and two sets of corresponding latches. The fast counter counts cycles of the controlled oscillator clock signal, and the low-power counter counts carry signals from the fast counter. The low-power counter represents one or more most significant bits of the integer part of the measured phase, and the fast counter represents the remaining bits. The phase accumulator may further include a delay line, second latches, and a delay line decoder to measure a fractional part of the phase. A calibration feedback loop may keep the number of delay line steps per output clock pulse known and stable.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: December 10, 2019
    Assignee: Perceptia IP Pty Ltd
    Inventor: Julian Jenkins
  • Patent number: 10491367
    Abstract: A clock and data recovery (CDR) circuit receives a data signal and generates a clock signal and a recovered data signal. The CDR circuit includes a clock-recovery circuit (CRC), a sampling phase-recovery circuit (PRC), an analog-to-digital converter (ADC), and a data-recovery circuit (DRC). The CRC receives the data signal and generates an intermediate clock signal. The PRC receives the intermediate clock signal, a sampled data signal and the recovered data signal, and generates the clock signal. The ADC receives the data signal and generates the sampled data signal. The DRC receives the sampled data signal and generates the recovered data signal. The clock signal is phase and frequency synchronized with the data signal.
    Type: Grant
    Filed: February 17, 2019
    Date of Patent: November 26, 2019
    Assignee: Synopsys, Inc.
    Inventors: Biman Chattopadhyay, Ravi Mehta
  • Patent number: 10461787
    Abstract: Systems and methods are disclosed for spur mitigation for pulse signal drivers in radio frequency (RF) devices. An RF integrated circuit includes RF circuitry and analog-to-digital (ADC) circuitry. The RF circuitry operates using a local oscillator (LO) clock to receive and/or transmit RF signals, and the ADC circuitry samples one or more analog input signals and has internal timing based upon a raw digital clock. A retime circuit receives the raw digital clock and the LO clock and has a retimed clock as an output. The retimed clock represents the raw digital clock retimed with the LO clock. While other digital circuitry is timed using the raw digital clock, one or more drivers are timed by the retimed clock and provide pulse output signals to output pads. Having the drivers timed with the retimed clock and other digital circuitry timed with the raw digital clock improves overall performance.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: October 29, 2019
    Assignee: Silicon Laboratories Inc.
    Inventors: Phillip Matthews, Paul I. Zavalney, John M. Khoury, Karma S. Bhutia
  • Patent number: 10447509
    Abstract: Precompensator-based quantization techniques offer a way to reduce the complexity and power requirements of clock recovery modules while offering improved timing recovery performance relative to a bang-bang scheme operating in a lossy channel.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: October 15, 2019
    Assignee: Credo Technology Group Limited
    Inventors: Fang Cai, Junqing Sun, Haoli Qian
  • Patent number: 10425167
    Abstract: First data and second data are transmitted by a simple configuration by including a generation unit that generates a wavelength-changed signal on the basis of the second data, and a transmission unit that transmits the wavelength-changed signal together with a first signal that indicates the first data.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: September 24, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Hideki Matsui
  • Patent number: 10425123
    Abstract: An apparatus is provided which comprises: a first circuitry to track a spread spectrum of a differential signal according to sampled data; and a second circuitry to adjust phase of a clock according to the spread spectrum, wherein the clock is used for sampling the differential signal.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: September 24, 2019
    Assignee: Intel Corporation
    Inventor: Amit Kumar Srivastava
  • Patent number: 10419204
    Abstract: A quarter-rate clock signal is doubled in a frequency doubler to produce a half-rate clock signal used by a serializer/deserializer (SerDes) interface to serialize and deserialize data.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: September 17, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Eskinder Hailu, Bupesh Pandita, Zhuo Gao
  • Patent number: 10410701
    Abstract: A clock monitoring circuit includes: a sampling circuit suitable for sampling a monitoring target clock in synchronization with a sampling clock; a first counter circuit suitable for counting the number of times that the sampling circuit samples the monitoring target clock at a predetermined level; and a second counter circuit suitable for counting the number of times that the sampling circuit performs sampling.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: September 10, 2019
    Assignee: SK hynix Inc.
    Inventors: Myeong-Jae Park, Young-Jae Choi
  • Patent number: 10374615
    Abstract: A transmission circuit includes: a clock generating circuit configured to generate a first clock signal and a second clock signal whose frequency is lower than a frequency of the first clock signal; a first conversion circuit configured to convert, based on the second clock signal, input data into intermediate data whose bit width is narrower than a bit width of the input data; a second conversion circuit configured to convert, based on the first clock signal, the intermediate data into output data whose bit width is narrower than the bit width of the intermediate data; capture circuits configured to sequentially capture a data sequence of the output data; an analysis circuit configured to perform an analysis on the captured data sequence; and a phase adjusting circuit configured to adjust a phase of the second clock signal based on a result of the analysis.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: August 6, 2019
    Assignee: SOCIONEXT INC.
    Inventor: Taro Moriai
  • Patent number: 10359803
    Abstract: Pipelined logic latency in a memory system operating at a reduced frequency may be compensated for. Pipelined logic may be controlled using at least first and second clock signals. All registers of the pipelined logic may be controlled using the first clock signal when the memory system is operating at a higher frequency. However, when the memory system is operating at a reduced frequency, one or more registers may be controlled using the first clock signal, and one or more other registers may be controlled using the second clock signal.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: July 23, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Dexter Tamio Chun, Richard Alan Stewart
  • Patent number: 10355725
    Abstract: Systems and methods are provided for handling jitter improvement in transmitters. During processing of input data for serial transmission, it may be determined if jitter may occur, and when jitter occurs one or more adjustments may be determined, based on dummy data, to reduce jitter in an output corresponding to the input data. The one or more adjustments may then be applied during processing of the input data, to reduce jitter in a serial output corresponding to the input data. The dummy data may be generated based on the input data. The dummy data may be configured such that it may generate corresponding dummy current pulses which may be used in controlling supply variations during generation of the serial output. The use of the dummy data may be selectively turned on or off.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: July 16, 2019
    Assignee: MAXLINEAR, INC.
    Inventors: Amir Hadji-Abdolhamid, Sheng Ye
  • Patent number: 10355901
    Abstract: Aspects of the description provide a method and devices to allow frequency domain spectral shaping (FDSS) to be used on both a reference sequence and data to enable low PAPR. Being able to use FDSS on both the reference sequence and data allows the FDSS to be transparent to the receiver. The method comprises obtaining a first sequence, wherein the first sequence is a base sequence of a set of base sequences, the set of base sequences comprising sub group base sequences, the first sequence obtained by cyclically repeating the sub group sequences at least once; and transmitting, by the device, a reference signal based on the first sequence.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: July 16, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Ming Jia, Jianglei Ma
  • Patent number: 10250074
    Abstract: To prevent an overvoltage from being applied to a load in a power reception circuit of a power supply system. A power supply system is provided which includes a power supply device equipped with a power supply coil, and a power reception device equipped with a power reception coil. When a resonance circuit is in a resonance state, a peak voltage value of a voltage generated in the power reception coil is set higher than a prescribed voltage value. When the resonance circuit is in a non-resonance state, the peak voltage value of the voltage generated in the power reception coil is set lower than the prescribed voltage value.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: April 2, 2019
    Assignee: ABLIC INC.
    Inventor: Norihiro Okazaki
  • Patent number: 10224978
    Abstract: Circuits and methods for performing a clock and data recovery are disclosed. In one example, a clock and data recovery circuit is disclosed. The circuit includes a third order digital filter, e.g. a finite state machine (FSM) that includes three accumulators connected in series. Among the three accumulators, a first accumulator receives an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle and accumulates input phase codes for different FSM cycles to generate a first order phase code at each FSM cycle; a second accumulator accumulates the input phase codes and first order phase codes for different FSM cycles to generate a second order phase code at each FSM cycle; and a third accumulator accumulates the input phase codes and second order phase codes for different FSM cycles to generate a third order phase code at each FSM cycle.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: March 5, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Hsiang Lan, Cheng-Hsiang Hsieh
  • Patent number: 10184981
    Abstract: Provided is an apparatus for measuring an input time of an input signal, and more particularly, an apparatus for measuring an input time of an input signal more precisely than a reference clock using a delay circuit. The apparatus for measuring an input time of an input signal includes: a signal input unit receiving a signal; a clock generation unit generating a reference clock; a delay unit including at least one delay circuit generating at least one delayed clock by delaying the reference clock; a detection unit detecting a signal input from the signal input unit, depending on a clock signal input from the clock generation unit and delay circuits; and an operation unit operating an input time of an input signal from the signal input unit based on data detected by the detection unit.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: January 22, 2019
    Assignee: Korea Aerospace Research Institute
    Inventors: Jae-Won Chang, Tae-Sik Kim, Jung Wook Hyun
  • Patent number: 10187498
    Abstract: A method for setting a waiting time duration includes: controlling a target component to send preset data to a processor a plurality of times, and controlling the processor to receive the preset data sent by the target component each time based on a different waiting time duration; determining, from the different waiting time durations, a maximum waiting time duration and a minimum waiting time duration that are used by the processor for correctly receiving the preset data; and determining and storing a to-be-used waiting time duration according to the maximum waiting time duration and the minimum waiting time duration.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: January 22, 2019
    Assignee: Xiaomi Inc.
    Inventors: Zhongshuai Wang, Yizhen Yang, Ning Ma
  • Patent number: 10185413
    Abstract: In one embodiment, a computer-readable non-transitory storage medium embodies logic that is configured when executed to determine a first correlation between first consecutive edges of a synchronization signal and a pre-determined coefficient vector. The logic is further configured when executed to determine a second correlation between second consecutive edges of the synchronization signal and the pre-determined coefficient vector and synchronize one or more timings for communication between a stylus and a device based at least in part on the first and second correlations.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: January 22, 2019
    Assignee: Wacom Co., Ltd.
    Inventors: Vemund Bakken, Eivind Holsen
  • Patent number: 10187085
    Abstract: The present discloses provides a decoding method, decoding apparatus and decoder for correcting burst errors. In particular, the decoding method for correcting burst errors comprises: computing an initial syndrome of a received data frame, wherein the data frame is encoded according to cyclic codes for correcting burst errors; determining error correctability of burst error contained in the data frame based on the computed initial syndrome; and processing the burst error in the data frame and outputting the processed data frame based on the determined error correctability. With the decoding method, decoding apparatus, and decoder of the present invention, error correctability of burst errors contained in a data frame can be determined before the data is send out, while having smaller decoding latency through determining the error correctability and error pattern of the burst errors contained in the data frame using initial syndrome of the data frame.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: January 22, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng Wei Song, Hao Yang, Fan Zhou, Hou Gang Li, Yufei Li
  • Patent number: 10096203
    Abstract: In one aspect, there is described a computer-implemented method of configuring timeout values for an electronic gaming system. The electronic gaming system includes an electronic gaming machine and a first host coupled to the electronic gaming machine through a network. The method includes: receiving a command to initiate timeout calibration through an input interface associated with the electronic gaming system; and in response to receiving the command: i) sending a plurality of test messages between the electronic gaming machine and the first host; ii) determining transmission times for the test messages; iii) based on the determined transmission times, automatically determining one or more timeout values; and iv) configuring one or both of the electronic gaming machine and the first host based on the determined timeout values.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: October 9, 2018
    Assignee: IGT Canada Solutions ULC
    Inventors: Bradley Boudreau, Yan Meunier
  • Patent number: 10057050
    Abstract: A signal recovery circuit includes an oscillator configured to control a frequency of generating first clock, and a feedback circuit configured to control the oscillator in order that input data is synchronized with the first clock in accordance with a phase relation between the input data and the first clock, wherein the feedback circuit includes a controller configured to control the oscillator in accordance with the phase relation between the input data and the first clock, a first phase detector configured to generate a clock phase control signal in accordance with the phase relation between the input data and the first clock, and a state detection circuit configured to detect whether the signal recovery circuit is in a locked state or an unlocked state, based on a magnitude of an amplitude of a first component or a second component of the clock phase control signal.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: August 21, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Yukito Tsunoda
  • Patent number: 10044539
    Abstract: Embodiments of the present disclosure relate to methods and device for receiving PAM data stream. In an embodiment, a method comprises receiving a signal stream modulated with pulse amplitude modulation (PAM) associated with a plurality of bit patterns; determining boundary voltages for the plurality of bit patterns; and calibrating, based on the boundary voltages, a threshold voltage for use in recognition of the plurality of bit patterns. In this way, bit patterns may be accurately recognized based on the calibrated threshold voltage.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: August 7, 2018
    Assignee: Lattice Semiconductor Corporation
    Inventors: Qiming Wu, Bing Zhang, Fei Song
  • Patent number: 10038507
    Abstract: An increase in circuit scale is suppressed and a phase variation caused in a transmission path or the like is compensated for.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: July 31, 2018
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Mitsuteru Yoshida, Etsushi Yamazaki, Seiji Okamoto, Hiroyuki Uzawa, Kengo Horikoshi, Koichi Ishihara, Takayuki Kobayashi, Yoshiaki Kisaka, Masahito Tomizawa, Naoki Fujiwara, Tomoyoshi Kataoka, Kazushige Yonenaga
  • Patent number: 9973332
    Abstract: An electronic apparatus including a PLL unit to an original clock signal, a pair of phase interpolators, a sampler, a phase detector, a control unit and a loop filter is provided. The phase interpolators receive the original clock signal and generate a reference clock signal and an auxiliary clock signal offset by 90 degrees having transition edges. The sampler samples an input data signal at each of the transition edge. The phase detector determines a phase difference of a data transition of the input data signal relative to the reference clock signal. The control unit superimposes an adjusting phase on phases of the reference clock signal and the auxiliary clock signal according to the phase difference. The phase detector determines that the phase difference is within a predetermined range. The loop filter superimposes a varying phase on the phases of the reference clock signal and the auxiliary clock signal accordly.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: May 15, 2018
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Hong-Yean Hsieh
  • Patent number: 9960902
    Abstract: An example method of clock and data recovery in a receiver includes generating data samples and crossing samples of a received signal based on a data clock signal and a crossing clock signal, respectively, which are derived from a sampling clock signal; adjusting a phase of the sampling clock signal using a clock and data recovery (CDR) circuit based on the data samples and the crossing samples; adjusting relative phase between the data clock signal and the crossing clock signal from a first phase difference to a second phase difference that is less than ninety degrees; and reverting the relative phase between the data clock signal and the crossing clock signal to the first phase difference after a threshold time period.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: May 1, 2018
    Assignee: XILINX, INC.
    Inventors: Winson Lin, Yu Xu, Caleb S. Leung, Alan C. Wong, Christopher J. Borrelli, Yohan Frans, Kun-Yung Chang
  • Patent number: 9906231
    Abstract: A clock and data recovery (CDR) circuit is provided, and includes a sampling circuit, an error sampler, a phase detect circuit, and a phase adjust circuit. The sampling circuit generates a data signal according to an input data and a first clock signal, and generates an edge signal according to the input data and a second clock signal. The error sampler compares the input data with a reference voltage according to the first clock signal to generate a control signal. The phase detect circuit receives the control signal and generates a corrective signal according to the data signal and the edge signal. When the values of the control signal and the data signal are different, the phase detect circuit stops transmitting the corrective signal. The phase adjust circuit generates and adjusts the first and the second clock signal according to the corrective signal.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: February 27, 2018
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Juh Kang, Yen-Chung Chen, Chen-Yang Pan
  • Patent number: 9892712
    Abstract: Techniques related to filtering hot plug signals are described herein. The techniques include receiving a first hot plug detect (HPD) signals and a second HPD signal from an external display device. A time period between receiving the first and second HPD signals is determined, and the first and second HPD signals are filtered based on the determined time period.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: February 13, 2018
    Assignee: Intel Corporation
    Inventors: Saran Chandra, Vandana Kannan, Ganesh Ram Sumaithangi Thattai
  • Patent number: 9857973
    Abstract: An interface circuit may include a first FIFO circuit and a second FIFO circuit. The first FIFO circuit may generate first output data based on a first sampling signal and a second sampling signal. The second FIFO circuit may generate second output data based on a third sampling signal and a fourth sampling signal. The first FIFO circuit and the second FIFO circuit may be cross-reset.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: January 2, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwanyeob Chae, Yoonjee Nam, Ji Hun Oh, Shinyoung Yi, Jong-Ryun Choi
  • Patent number: 9832551
    Abstract: An optical transmission device includes: a receiver configured to receive a signal including data; a generator configured to generate an output clock to output the data based on a signal clock synchronized with the signal; and a controller configured to control a frequency of the output clock based on a first amount of the data so that the output clock follows a clock of a transmission source of the data.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: November 28, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Hiroshi Yoshida
  • Patent number: 9733731
    Abstract: In one embodiment, a stylus includes a controller, a delay line, a coefficient line and a computer-readable non-transitory storage medium. The controller is operable to receive a synchronization signal that is transmitted from a computing device and received by the stylus. The delay line is operable to store a first consecutive edges of the synchronization signal. The coefficient line includes a pre-determined coefficient vector.
    Type: Grant
    Filed: May 12, 2014
    Date of Patent: August 15, 2017
    Assignee: Atmel Corporation
    Inventors: Vemund Bakken, Eivind Holsen
  • Patent number: 9692401
    Abstract: A skew adjustment circuit comprises a phase adjustment circuit that adjusts a phase of a first input clock based on a predetermined phase control signal, and outputs it as an output clock, a logical circuit that performs a logical operation between signals that are input, an integral circuit that generates a predetermined voltage signal, based on a result of the logical operation by the logical circuit, a comparator that compares an electric potential of the predetermined voltage signal and an electric potential of a predetermined reference voltage signal, a first controller that generates the predetermined phase control signal based on a result of the comparison by the comparator, and a second controller that performs control for selecting a signal that is to be input to the logical circuit. The second controller, in a first mode, performs the control such that the output clock and a second input clock are selected.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: June 27, 2017
    Assignee: MegaChips Corporation
    Inventor: Shingo Adachi
  • Patent number: 9692588
    Abstract: A method of performing synchronization in a super regenerative receiver (SRR) includes setting a quench rate of the SRR to a value of 1.5 times a chip rate of an incoming signal, acquiring an expected preamble sequence of an arbitrary sample set among a plurality of possible sample sets, acquiring an expected start frame delimiter (SFD) sequence for all of the possible sample sets to achieve frame synchronization, computing respective correlation metrics for bits of the expected SFD sequence while the expected SFD sequence is acquired for all of the possible sample sets, calculating a decision metric based on the correlation metrics in response to an SFD sequence being detected for one or more of the possible sample sets, and identifying a best sample set for demodulating the incoming signal among all of the possible sample sets based on the decision metric to achieve pulse synchronization.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: June 27, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kiran Bynam, Sujit Jos, PS Chandrashekhar Thejaswi, ChangSoon Park, Jinesh P. Nair, Young-Jun Hong, Youngsoo Kim, Manoj Choudhary
  • Patent number: 9647781
    Abstract: A data reception device which receives data transmitted through a plurality of transmission lines. The data reception device includes a position detection unit which corrects a skew of data transmitted respectively through the plurality of transmission lines, and detects for each lane a position of a marker for identification of a lane which is assigned the data, and an information extraction unit which extracts identification information indicated by the marker for each lane using a result of the detection of the position of the marker by the position detection unit.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: May 9, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Katsutoshi Miyaji, Hiroyuki Homma, Ken Shiine, Hiromichi Makishima
  • Patent number: 9548727
    Abstract: An oscillator circuit includes: a plurality of delay elements, a first delay element configured to receive a first oscillator signal outputted from a second delay element in one stage before the first delay element and a second oscillator signal outputted from a third delay element in two or more stages before the first delay element, the plurality of delay terminals being connected in a ring by at least three or more delay elements, and the first oscillator signal and the second oscillator signal having phases different from one another; and a bias voltage generator configured to change a ratio of a first input bias current for the first oscillator signal to a second input bias current for the second oscillator signal, in accordance with a first bias voltage and a second bias voltage supplied to the plurality of delay elements.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: January 17, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Win Chaivipas
  • Patent number: 9531572
    Abstract: A system may include an interface circuit coupled to a wire bus. The interface circuit may receive a multi-level symbol according to a status of the wire bus. The interface circuit may include a clock recovery circuit configured to generate a recovered clock based on the multi-level symbol. The interface circuit may latch the multi-level symbol based on one of an external clock and the recovered clock according to an operation speed of the system.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: December 27, 2016
    Assignee: SK HYNIX INC.
    Inventors: Jong Joo Shim, Keun Soo Song
  • Patent number: 9509319
    Abstract: A clock and data recovery (CDR) circuit that receives an input signal and generates clock and sampled output signals includes a phase-frequency detector (PFD) circuit, a control circuit, a digital-to-analog converter (DAC), a current-controlled oscillator (CCO) and a data sampler. The PFD generates intermediate and fine digital control signals. The DAC receives the intermediate digital control signal as a coarse digital control signal and the fine digital control signal and generates an output current. The CCO receives the output current and generates the clock signal. The coarse digital control signal is used to coarse calibrate a frequency of the clock signal and the fine digital control signal is used to fine calibrate the frequency of the clock signal. The data sampler receives the clock signal and samples the input signal at the frequency of the clock signal to generate the sampled output signal.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: November 29, 2016
    Assignee: SILAB TECH PVT. LTD.
    Inventors: Biman Chattopadhyay, Ravi Mehta, Gopal Krishna Ullal Nayak, Sharath Bhat N
  • Patent number: 9509487
    Abstract: Method and apparatus for generating a jitter reduced clock signal from signal transmitted over a communication medium includes receiving, with high speed data interface circuitry, a modulated signal that includes a binary encoded data stream. A recovered clock signal is generated from the modulated signal and tracks the long-term drift in the modulated signal. A jitter reduced clock signal is generated by filtering the recovered clock signal with a filtering circuit having a bandwidth sufficient to remove jitter while allowing the jitter reduced clock signal to track the drift in the modulated signal.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: November 29, 2016
    Assignee: CommScope Technologies LLC
    Inventors: Donald Robert McAllister, Christopher Goodman Ranson, Fred William Phillips
  • Patent number: 9509446
    Abstract: A signal transmission system includes: a signal sending device including a signal sender converting a sending signal to a transmission signal using a signal sending parameter and sends the transmission signal to a signal path, and a sending controller receiving a sending control signal and changes the signal sending parameter according to the sending control signal; and a signal receiving device including a signal receiver converting the transmission signal received via the signal path, to a reception signal using a signal reception parameter, a signal reception monitor monitoring a signal reception status of the transmission signal and outputs monitor information acquired by the monitoring, and a reception controller checking transmission quality of the signal path using the monitor information, creates the sending control signal for changing the signal sending parameter according to a checking result to send, and changes the signal reception parameter.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: November 29, 2016
    Assignee: NEC CORPORATION
    Inventor: Tomohiro Takahashi