Phase Displacement, Slip Or Jitter Correction Patents (Class 375/371)
  • Patent number: 11115142
    Abstract: This disclosure describes techniques for delivering high-accuracy and high-precision clock synchronization in heterogeneous distributed computer clusters. For example, the disclosure describes a synchronization engine that sets efficient clock synchronization processes based on a cluster node's characteristics, pricing, precision, geolocation, and/or cluster topology, while in some cases using a combination of master clock data with internal atomic clocks of computers. The techniques described herein integrate the synchronization engine into a time synchronization process that may provide stability, versatility, precision and cost balance using technical improvements for characterizing timing system delivery channels.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: September 7, 2021
    Assignee: Equinix, Inc.
    Inventors: Anand Ozarkar, Ankur Sharma, Christopher Alan Anderson, Danjue Li, Lance Weaver, Brian J. Lillie
  • Patent number: 11105853
    Abstract: Examples described herein provide a computer-implemented method that includes initiating a logic built-in self-test (LBIST) of a device under test (DUT). The method further includes performing latch state counting using a multiple input signature register (MISR) of the DUT, the performing responsive to the MISR being in a counter mode. The method further includes performing a latch transition counting of latches of the DUT using the MISR of the DUT and a storage latch, the performing responsive to the MISR being in the counter mode. The method further includes performing a latch count comparison by comparing an output of the MISR responsive to the MISR being in the counter mode to an output of a count compare register, the output of the count compare register representing a desired MISR state.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: August 31, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Franco Motika, Richard Frank Rizzolo, Paul Jacob Logsdon
  • Patent number: 11101923
    Abstract: Circuitry and methods for receiving data that may be compliant with a specific protocol is discussed. The described systems may be employed to implement a physical media access (PMA) sublayer and/or physical coding sublayer (PCS) for high-speed Ethernet protocols. Embodiments described herein may have reduced circuitry footprint that may be achieved by the use of a single recovered clock to drive the operations of PCS circuitry. Efficient use of components may also be achieved by the use of smaller-sized words for processing by the PCS circuitry. The circuitry may process the smaller-sized words by implementing pipelined circuitry. Implementations that employ programmable circuitry, hardened circuitry, or hybrid implementations are also discussed.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: August 24, 2021
    Assignee: Intel Corporation
    Inventor: Faisal Khan
  • Patent number: 11093400
    Abstract: Novel techniques are described for lock-free sharing of a circular buffer. Embodiments can provide shared, lock-free, constant-bitrate access by multiple consumer systems to a live stream of audiovisual information being recorded to a circular buffer by a producer. For example, when a producer system writes a data stream to the circular buffer, the producer system records shared metadata. When a consumer system desires to begin reading from the shared buffer at a particular time, the shared metadata is used to compute a predicted write pointer location and corresponding dirty region around the write pointer at the desired read time. A read pointer of the consumer system can be set to avoid the dirty region, thereby permitting read access to a stable region of the circular buffer without relying on a buffer lock.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: August 17, 2021
    Assignee: Sling Media Pvt. Ltd.
    Inventors: Amit Kumar, Gopikumar Ranganathan
  • Patent number: 11082200
    Abstract: A clock and data recovery apparatus is provided that includes a sampling circuit, a storage circuit and a determining circuit. The sampling circuit includes sampling units each sampling a received data according to one of reference clock signals to generate a sampling result. The storage circuit includes FIFO storage units configured to store the sampling result of the received data corresponding to different time spots. The determining circuit is configured to set a certain number of received data as a reference data pattern, to adjust a starting position of a sampling window according to a transition point of sampled values within the reference data pattern when only one data transition exists therein and adjust a length of the sampling window according to an amount of high state sample points of the sampled values within the reference data pattern when more than one data transitions exist therein.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: August 3, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chieh-Shiung Chang, Chia-Jung Chang, Yu-An Chang, Cheng-Yu Liu
  • Patent number: 11069989
    Abstract: The disclosed systems, structures, and methods are directed to a multi-level multi-mode transmitter, employing a first pre-driver configured to receive M-parallel data streams and to convert the M-parallel data streams into a serial data stream, a first voltage-driver configured to operate on the single data stream and to provide a voltage in accordance with the single data stream, a second pre-driver configured to receive and process the M-parallel data streams in accordance with at least one of the following modes: moderate impedance (Z) post-cursor mode, moderate Z pre-cursor mode, low Z high-swing mode, low Z post-cursor mode, and low Z pre-cursor mode, and convert the processed M-parallel data streams into a first serial stream and a second serial stream and a second voltage-driver configured to operate on the first serial stream and the second serial stream and to provide a voltage.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: July 20, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Faisal Ahmed Musa, Euhan Chong
  • Patent number: 11064501
    Abstract: The present invention is directed to systems and methods for reducing noise levels by harmonization in a DCC-DAS using smart weighted aggregation of noise and signal resources to achieve an optimal signal to noise ratio in varying traffic and interference conditions.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: July 13, 2021
    Inventors: Abraham Hasarchi, Amir Meir
  • Patent number: 11048292
    Abstract: An integrated circuit includes a master-slave storage element having a data input coupled to receive a data signal and an asymmetrical clock generator coupled to provide an asymmetrical clock signal to the master-slave storage element. A first phase of the asymmetrical clock signal is configured for inhibiting intermediate data signal transitions from propagating through the master portion of the master-slave storage element.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: June 29, 2021
    Assignee: NXP USA, INC.
    Inventors: Anis Mahmoud Jarrar, John Mark Boyer, Nancy Hing-Che Amedeo
  • Patent number: 11025294
    Abstract: Circuits and methods for performing a clock and data recovery are disclosed. In one example, a circuit is disclosed. The circuit includes an FSM. The FSM includes: a first accumulator, a second accumulator, and a third accumulator. The first accumulator is configured to receive an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle, to accumulate input phase codes for different FSM cycles, and to generate a first order phase code at each FSM cycle. The second accumulator is coupled to the first accumulator and configured to accumulate the input phase codes and first order phase codes for different FSM cycles, and to generate a second order phase code at each FSM cycle. The third accumulator is coupled to the second accumulator and configured to accumulate the input phase codes and second order phase codes for different FSM cycles, and to generate a third order phase code at each FSM cycle.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: June 1, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Hsiang Lan, Cheng-Hsiang Hsieh
  • Patent number: 11018675
    Abstract: Generating a composite interpolated phase-error signal for clock phase adjustment of a local oscillator by forming a summation of weighted phase-error signals generated using a matrix of partial phase comparators, each of which compare a phase of the local oscillator with a corresponding phase of a reference clock.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: May 25, 2021
    Assignee: KANDOU LABS, S.A.
    Inventor: Armin Tajalli
  • Patent number: 11005467
    Abstract: A method operates by receiving a first voltage, which is a logical signal; converting the first voltage into a second voltage using a first inverting buffer with a first pull-up resistance and a first pull-down resistance; and converting the second voltage into a third voltage using a second inverting buffer with a second pull-up resistance and a second pull-down resistance, wherein: the first pull-up resistance, the first pull-down resistance, the second pull-up resistance, the second pull-down resistance are all tunable, and a difference between the first pull-up resistance and the first pull-down resistance is approximately equal to a difference between the second pull-down resistance and the second pull-up resistance.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: May 11, 2021
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Chia-Liang (Leon) Lin
  • Patent number: 10965571
    Abstract: A clock timing recovery method for determining a clock timing of an input signal is described, wherein the input signal is generated by a signal source, comprising: receiving the input signal; determining signal edges of the input signal based on the received input signal; determining at least a first clock timing model parameter; determining at least one jitter component of the input signal; and determining a clock timing error associated with the at least one jitter component, wherein the clock timing error is determined based on the determined signal edges, the determined first clock timing model parameter and the determined jitter component. Moreover, a measurement instrument is described.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: March 30, 2021
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventors: Bernhard Nitsch, Andreas Maier, Adrian Ispas
  • Patent number: 10958224
    Abstract: Devices and methods for generating a bias voltage for a transceiver operating in time division multiplexing operation, and corresponding transceivers are provided. In this case, the bias voltage is controlled in guard intervals between transmission and reception of signals by the transceiver.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: March 23, 2021
    Assignee: Infineon Technologies AG
    Inventors: David Seebacher, Pantelis Sarais, Peter Singerl, Herwig Wappis
  • Patent number: 10951214
    Abstract: A signal analysis method for recovering a clock signal from an input signal is described. The input signal comprises a symbol sequence, wherein each symbol has one of N different amplitude values, and wherein N is an integer bigger than 1. The signal analysis method comprises the following steps: The input signal is received. Transition times of the input signal are determined, wherein the input signal respectively crosses one of several predetermined amplitude thresholds at the transition times. The transition times are transformed into one reference symbol period, thereby obtaining transformed transition times. The clock signal is determined based on the transformed transition times. Further, a signal analysis module for recovering a clock signal from an input signal is described.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: March 16, 2021
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventors: Adrian Ispas, Michael Reinhold
  • Patent number: 10924096
    Abstract: Apparatus and associated methods relate to a dynamic lane-to-lane skew reduction technique having (a) a clocking architecture configured to provide a corresponding first delayed clock signal and a corresponding second delayed clock signal through a first and a second plurality of routing traces, respectively, and (b) a number of skew compensation circuits configured to process the corresponding first delayed clock signal and the corresponding second delayed clock signal to generate a corresponding user clock signal for a corresponding lane of a transmitter. In an illustrative example, a first routing trace may transmit a first delayed clock signal in a direction opposite to a second routing trace transmitting a second delayed clock signal. By implementing the technique, each transmitter lane may receive a corresponding user clock signal having substantially the same delay relative to a reference clock signal such that dynamic lane-to-lane skew may be advantageously reduced.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: February 16, 2021
    Assignee: XILINX, INC.
    Inventors: Gourav Modi, Chee Chong Chan, Azarudin Abdulla, Riyas Noorudeen Remla
  • Patent number: 10891961
    Abstract: A device includes a receiver configured to receive an encoded bitstream from a second device. The encoded bitstream includes a temporal mismatch value. The device also includes a decoder configured to decode the encoded bitstream to generate a first signal and a second signal. Based on the temporal mismatch value, the decoder is configured to map one of the first signal or the second signal as a decoded target channel. The decoder is also configured to perform a shift operation on the decoded target channel based on the temporal mismatch value to generate an adjusted decoded target channel. The device also includes an output device configured to output a first output signal and a second output signal. The second output signal is based on the adjusted decoded target channel.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: January 12, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Venkata Subrahmanyam Chandra Sekhar Chebiyyam, Venkatraman Atti
  • Patent number: 10873333
    Abstract: Systems and methods configured to cancel spurs in a phase locked loop (PLL) system are provided. A method configured to cancel spurs in a PLL system includes receiving a PLL signal from the PLL system; determining an estimated spur frequency of a spur in the received PLL signal based on the received PLL signal; and canceling the spur in the received PLL signal based on the estimated spur frequency.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: December 22, 2020
    Assignee: Intel Corporation
    Inventors: Rotem Avivi, Michael Kerner, Yair Dgani
  • Patent number: 10863468
    Abstract: A method of communication in a Bluetooth Low Energy network is presented. The network has a master device and a plurality of slave devices between a first slave device and a second slave device. The method steps include: sending from the master device to the first slave device a synchronisation delay parameter; and sending from the master device to the second slave device the synchronisation delay parameter and a relative offset parameter. At the second slave device, the method steps include determining a synchronisation time point by adding the relative offset parameter to the synchronisation delay parameter. At the synchronisation time point, the method steps include waking the first and second slave devices and sending a communication from the first slave device to the second slave device.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: December 8, 2020
    Assignee: Dialog Semiconductor B.V.
    Inventor: Kanji Kerai
  • Patent number: 10855413
    Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: December 1, 2020
    Assignee: Rambus Inc.
    Inventors: Jared Zerbe, Pak Shing Chau, William Franklin Stonecypher
  • Patent number: 10825492
    Abstract: Apparatuses and methods for reducing a number of command shifters are disclosed. An example apparatus includes an encoder circuit, a latency shifter circuit, and a decoder circuit. The encoder circuit may be configured to encode commands, wherein the commands are encoded based on their command type and the latency shifter circuit, coupled to the encoder circuit, may be configured to provide a latency to the encoded commands. The decoder circuit, coupled to the latency shifter circuit, may be configured to decode the encoded commands and provide decoded commands to perform memory operations associated with the command types of the decoded commands.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: November 3, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Debra Bell, Kallol Mazumder
  • Patent number: 10805064
    Abstract: A system includes an optical transmitter including a transmitter Phase Lock Loop (PLL) circuit; an optical receiver connected to the optical transmitter and including a receiver PLL circuit; and circuitry configured to inject a test stimulus to a clock causing jitter in one of the transmitter PLL circuitry and the receiver PLL circuit, wherein the test stimulus is set for characterizing the jitter tolerance of optical receiver. As well, a circuit that injects SOP transient at the transmitter is included. It is configured to test the tolerance of optical receiver to handle fast change in the SOP state. The optical receiver is configured to determine if the system is operational at a jitter value due to the test stimulus based on compliance to one or more thresholds including any of a target Bit Error Rate, a Forward-Error-Correction (FEC) hit, and a jitter Root Mean Square (RMS).
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: October 13, 2020
    Assignee: Ciena Corporation
    Inventors: Sadok Aouini, Naim Ben-Hamida, Ahmad Abdo, Timothy James Creasy, Lukas Jakober, Yalmez M. A. Yazaw, Shahab Oveis Gharan
  • Patent number: 10771346
    Abstract: A method monitors a data transmission network having a plurality of devices connected to one another over fixedly prescribed signal transmission paths, for anomalies. One of the devices is a master device that has a counter and a trigger apparatus, by which a prescribed signal feature of a signal is acquired, and upon the acquisition, a master counter state corresponding thereto is read. The method provides for an evaluation apparatus to determine, under predetermined conditions, a setpoint value of at least one network-specific parameter defined by a physical property of the network, before an actual value of the network-specific parameter is determined from a difference between the master counter state and a further counter state, and an anomaly is indicated if a predetermined deviation criterion between the actual value and the setpoint value is met.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: September 8, 2020
    Assignee: Conti Temic microelectronic GmbH
    Inventors: Uli Joos, Florian Gerster, Lorenz Lieder
  • Patent number: 10763866
    Abstract: An electronic circuit includes a clock recovery circuit that generates a first reference clock signal based on first reception data and generates a second reference clock signal based on second reception data received after the first reception, a sampling clock generator that generates a sampling clock signal having a phase based on a phase difference between the first reference clock signal and the second reference clock signal, and a sampler that recovers the second reception data based on the generated sampling clock signal.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: September 1, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyungho Ryu, Hansu Pae, Kilhoon Lee, Jaeyoul Lee, Jung-Pil Lim, Hyunwook Lim
  • Patent number: 10739874
    Abstract: In one embodiment, a computer-readable non-transitory storage medium embodies logic that is configured when executed to determine a first correlation between first consecutive edges of a synchronization signal and a pre-determined coefficient vector. The logic is further configured when executed to determine a second correlation between second consecutive edges of the synchronization signal and the pre-determined coefficient vector and synchronize one or more timings for communication between a stylus and a device based at least in part on the first and second correlations.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: August 11, 2020
    Assignee: Wacom Co., Ltd.
    Inventors: Vemund Bakken, Eivind Holsen
  • Patent number: 10701695
    Abstract: The present disclosure is a novel utility of a software defined radio (SDR) based Distributed Antenna System (DAS) that is field reconfigurable and support multi-modulation schemes (modulation-independent), multi-carriers, multi-frequency bands and multi-channels. The present disclosure enables a high degree of flexibility to manage, control, enhance, facilitate the usage and performance of a distributed wireless network such as flexible simulcast, automatic traffic load-balancing, network and radio resource optimization, network calibration, autonomous/assisted commissioning, carrier pooling, automatic frequency selection, frequency carrier placement, traffic monitoring, traffic tagging, pilot beacon, etc.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: June 30, 2020
    Assignee: DALI WIRELESS, INC.
    Inventors: Paul Lemson, Shawn Patrick Stapleton, Sasa Trajkovic, Albert S. Lee
  • Patent number: 10644706
    Abstract: A data and clock recovery circuit includes a first selecting circuit, a high speed phase detector, a low speed phase detector, a charge pump, a voltage control oscillator and a frequency divider. The high speed phase detector generates a first phase difference signal according to the first reference clock signal and a divided clock signal or according to the data signal and the divided clock signal. The low speed phase detector generates a second phase difference signal according to a second reference clock signal and the divided clock signal. The charge pump generates a control voltage according to the first phase difference signal or the second phase difference signal. The voltage control oscillator receives the control voltage, and generates a recovered clock signal. The frequency divider receives the recovered clock signal, and generates the divided clock signal.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: May 5, 2020
    Assignee: Faraday Technology Corp.
    Inventors: Young-Bok Kim, Andrew Chao
  • Patent number: 10644870
    Abstract: A clock recovery system includes: a sampler that samples reception data with 2N phase clocks and outputs 2N×M sampling signals; a data selector that selects n×M recovery signals from the 2N×M sampling signals and outputs the n×M recovery signals; a phase comparator that outputs, for each of the n×M recovery signals, a phase comparison signal based on the recovery signal, a first sampling signal sampled with a first clock that leads by one or more phases from a sampling clock, and a second sampling signal sampled with a second clock that delays by one or more phases from the sampling clock; a controller that designates n based on a data rate of the reception data; and a multiphase clock generator that generates and outputs the 2N phase clocks based on the phase comparison signal and n.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: May 5, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Akinori Shinmyo, Syuji Kato
  • Patent number: 10594469
    Abstract: The present application describes a computer-implemented method for frequency hopping including configuring a radio front end to operate on a first frequency; receiving a transmit signal in a first path in the radio front end; amplifying a transmit signal in the first path; phase shifting the transmit signal in a second path in the radio front end, the second path being different from the first path; coupling the amplified transmit signal to a third path in the radio front end; coupling the phase-shifted transmit signal in the second path to the amplified transmit signal in the third path to form a carrier-cancelled signal in a fourth path in the radio front end in the radio front end; phase shifting the carrier-cancelled signal in the fourth path; coupling the phase-shifted carrier-cancelled signal in the fourth path to the amplified transmit signal in the first path; and reconfiguring the radio front end to operate on a second frequency.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: March 17, 2020
    Inventors: Alan Scott Brannon, Riley Nelson Pack, Benjamin Joseph Baker
  • Patent number: 10588080
    Abstract: A digital signal processing device of a base station configured to process down-link signals in a wireless communication system employing orthogonal frequency division multiple access (OFDMA) and a method of processing data in the device are provided. The device includes a clock controller configured to monitor whether a signal is allocated to an input and control a frequency of clocks to have a first or second characteristic based on the monitored result, and a data processor configured to process the input, and synchronize with the clock controlled by the clock controller.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: March 10, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yonghae Choi, Hanseok Kim, Seongyong Park, Jeongjae Won, Junsung Lee
  • Patent number: 10575272
    Abstract: In the present invention, a method for synchronizing frequency and time in a wireless communication system and an apparatus for supporting the same are disclosed. Particularly, a method for synchronizing frequency and time performed by a terminal in a wireless communication system may include receiving a specific signal including a PSS, compensating the specific signal with at least one time offset candidate, generating at least one first differentiation value, generating at least one second differentiation value, calculating a cross correlation value between the at least one first differentiation value and the at least one second differentiation value, and estimating a time offset and a frequency offset of the PSS based on a time offset candidate that corresponds to a greatest cross correlation value among at least one cross correlation value calculated for at least one time offset candidate.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: February 25, 2020
    Assignee: LG ELECTRONICS INC.
    Inventors: Seokmin Shin, Hyunsoo Ko, Bonghoe Kim, Byounghoon Kim
  • Patent number: 10545746
    Abstract: In a dynamic computing environment, it is a nontrivial task to verify code running in the environment because most approaches to software similarity require extensive and time-consuming analysis of a binary, or the approaches fail to recognize executables that are similar but nonidentical. A biosequence-based method for quantifying similarity of executable binaries is used to identify allowed codes in a real-world multi-user environment.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: January 28, 2020
    Assignee: Battelle Memorial Institute
    Inventors: Elena S. Peterson, Christopher S. Oehmen, Aaron R. Phillips, Darren S. Curtis
  • Patent number: 10547475
    Abstract: A receiver device includes circuitry and memory. The circuitry converts an input signal into a data signal that includes data symbols transmitted in successive unit intervals (UIs), determines a first threshold associated with a first symbol type, adjusts a gain of the receiver device such that an average amplitude of data signal samples, when receiving data symbols having the first symbol type, corresponds to the first threshold, determines a second threshold that corresponds to an average amplitude of the data signal samples when data symbols of a current UI have the first symbol type and data symbols of a first UI, at a first determined time distance from the current UI, have a second symbol type, and computes, as a first cursor value associated with the first UI, a first difference between the first threshold and the second threshold, multiplied by a first constant.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: January 28, 2020
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventor: Mathieu Gagnon
  • Patent number: 10505549
    Abstract: A PLL includes a controlled oscillator, a phase accumulator to measure the controlled oscillator output phase, a phase predictor to calculate the required output phase, and a phase subtractor to calculate the phase difference or phase error. The phase accumulator includes a fast counter and a low-power counter, and two sets of corresponding latches. The fast counter counts cycles of the controlled oscillator clock signal, and the low-power counter counts carry signals from the fast counter. The low-power counter represents one or more most significant bits of the integer part of the measured phase, and the fast counter represents the remaining bits. The phase accumulator may further include a delay line, second latches, and a delay line decoder to measure a fractional part of the phase. A calibration feedback loop may keep the number of delay line steps per output clock pulse known and stable.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: December 10, 2019
    Assignee: Perceptia IP Pty Ltd
    Inventor: Julian Jenkins
  • Patent number: 10504552
    Abstract: A plurality of kinds of LPCM signals/compression digital audio signals is switched to one another in transmission, thereby enabling audio reproduction to be satisfactorily carried out. A digital audio signal is transmitted to an external apparatus through a predetermined transmission path. Information associated with the digital audio signal to be next transmitted is added to the digital audio signal which is currently being transmitted. For example, first metadata exhibiting a transmission frequency of the digital audio signal, and second metadata exhibiting a data type of the digital audio signal are contained in the information.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: December 10, 2019
    Assignee: SONY CORPORATION
    Inventor: Gen Ichimura
  • Patent number: 10491367
    Abstract: A clock and data recovery (CDR) circuit receives a data signal and generates a clock signal and a recovered data signal. The CDR circuit includes a clock-recovery circuit (CRC), a sampling phase-recovery circuit (PRC), an analog-to-digital converter (ADC), and a data-recovery circuit (DRC). The CRC receives the data signal and generates an intermediate clock signal. The PRC receives the intermediate clock signal, a sampled data signal and the recovered data signal, and generates the clock signal. The ADC receives the data signal and generates the sampled data signal. The DRC receives the sampled data signal and generates the recovered data signal. The clock signal is phase and frequency synchronized with the data signal.
    Type: Grant
    Filed: February 17, 2019
    Date of Patent: November 26, 2019
    Assignee: Synopsys, Inc.
    Inventors: Biman Chattopadhyay, Ravi Mehta
  • Patent number: 10461787
    Abstract: Systems and methods are disclosed for spur mitigation for pulse signal drivers in radio frequency (RF) devices. An RF integrated circuit includes RF circuitry and analog-to-digital (ADC) circuitry. The RF circuitry operates using a local oscillator (LO) clock to receive and/or transmit RF signals, and the ADC circuitry samples one or more analog input signals and has internal timing based upon a raw digital clock. A retime circuit receives the raw digital clock and the LO clock and has a retimed clock as an output. The retimed clock represents the raw digital clock retimed with the LO clock. While other digital circuitry is timed using the raw digital clock, one or more drivers are timed by the retimed clock and provide pulse output signals to output pads. Having the drivers timed with the retimed clock and other digital circuitry timed with the raw digital clock improves overall performance.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: October 29, 2019
    Assignee: Silicon Laboratories Inc.
    Inventors: Phillip Matthews, Paul I. Zavalney, John M. Khoury, Karma S. Bhutia
  • Patent number: 10447509
    Abstract: Precompensator-based quantization techniques offer a way to reduce the complexity and power requirements of clock recovery modules while offering improved timing recovery performance relative to a bang-bang scheme operating in a lossy channel.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: October 15, 2019
    Assignee: Credo Technology Group Limited
    Inventors: Fang Cai, Junqing Sun, Haoli Qian
  • Patent number: 10425123
    Abstract: An apparatus is provided which comprises: a first circuitry to track a spread spectrum of a differential signal according to sampled data; and a second circuitry to adjust phase of a clock according to the spread spectrum, wherein the clock is used for sampling the differential signal.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: September 24, 2019
    Assignee: Intel Corporation
    Inventor: Amit Kumar Srivastava
  • Patent number: 10425167
    Abstract: First data and second data are transmitted by a simple configuration by including a generation unit that generates a wavelength-changed signal on the basis of the second data, and a transmission unit that transmits the wavelength-changed signal together with a first signal that indicates the first data.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: September 24, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Hideki Matsui
  • Patent number: 10419204
    Abstract: A quarter-rate clock signal is doubled in a frequency doubler to produce a half-rate clock signal used by a serializer/deserializer (SerDes) interface to serialize and deserialize data.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: September 17, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Eskinder Hailu, Bupesh Pandita, Zhuo Gao
  • Patent number: 10410701
    Abstract: A clock monitoring circuit includes: a sampling circuit suitable for sampling a monitoring target clock in synchronization with a sampling clock; a first counter circuit suitable for counting the number of times that the sampling circuit samples the monitoring target clock at a predetermined level; and a second counter circuit suitable for counting the number of times that the sampling circuit performs sampling.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: September 10, 2019
    Assignee: SK hynix Inc.
    Inventors: Myeong-Jae Park, Young-Jae Choi
  • Patent number: 10374615
    Abstract: A transmission circuit includes: a clock generating circuit configured to generate a first clock signal and a second clock signal whose frequency is lower than a frequency of the first clock signal; a first conversion circuit configured to convert, based on the second clock signal, input data into intermediate data whose bit width is narrower than a bit width of the input data; a second conversion circuit configured to convert, based on the first clock signal, the intermediate data into output data whose bit width is narrower than the bit width of the intermediate data; capture circuits configured to sequentially capture a data sequence of the output data; an analysis circuit configured to perform an analysis on the captured data sequence; and a phase adjusting circuit configured to adjust a phase of the second clock signal based on a result of the analysis.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: August 6, 2019
    Assignee: SOCIONEXT INC.
    Inventor: Taro Moriai
  • Patent number: 10359803
    Abstract: Pipelined logic latency in a memory system operating at a reduced frequency may be compensated for. Pipelined logic may be controlled using at least first and second clock signals. All registers of the pipelined logic may be controlled using the first clock signal when the memory system is operating at a higher frequency. However, when the memory system is operating at a reduced frequency, one or more registers may be controlled using the first clock signal, and one or more other registers may be controlled using the second clock signal.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: July 23, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Dexter Tamio Chun, Richard Alan Stewart
  • Patent number: 10355725
    Abstract: Systems and methods are provided for handling jitter improvement in transmitters. During processing of input data for serial transmission, it may be determined if jitter may occur, and when jitter occurs one or more adjustments may be determined, based on dummy data, to reduce jitter in an output corresponding to the input data. The one or more adjustments may then be applied during processing of the input data, to reduce jitter in a serial output corresponding to the input data. The dummy data may be generated based on the input data. The dummy data may be configured such that it may generate corresponding dummy current pulses which may be used in controlling supply variations during generation of the serial output. The use of the dummy data may be selectively turned on or off.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: July 16, 2019
    Assignee: MAXLINEAR, INC.
    Inventors: Amir Hadji-Abdolhamid, Sheng Ye
  • Patent number: 10355901
    Abstract: Aspects of the description provide a method and devices to allow frequency domain spectral shaping (FDSS) to be used on both a reference sequence and data to enable low PAPR. Being able to use FDSS on both the reference sequence and data allows the FDSS to be transparent to the receiver. The method comprises obtaining a first sequence, wherein the first sequence is a base sequence of a set of base sequences, the set of base sequences comprising sub group base sequences, the first sequence obtained by cyclically repeating the sub group sequences at least once; and transmitting, by the device, a reference signal based on the first sequence.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: July 16, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Ming Jia, Jianglei Ma
  • Patent number: 10250074
    Abstract: To prevent an overvoltage from being applied to a load in a power reception circuit of a power supply system. A power supply system is provided which includes a power supply device equipped with a power supply coil, and a power reception device equipped with a power reception coil. When a resonance circuit is in a resonance state, a peak voltage value of a voltage generated in the power reception coil is set higher than a prescribed voltage value. When the resonance circuit is in a non-resonance state, the peak voltage value of the voltage generated in the power reception coil is set lower than the prescribed voltage value.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: April 2, 2019
    Assignee: ABLIC INC.
    Inventor: Norihiro Okazaki
  • Patent number: 10224978
    Abstract: Circuits and methods for performing a clock and data recovery are disclosed. In one example, a clock and data recovery circuit is disclosed. The circuit includes a third order digital filter, e.g. a finite state machine (FSM) that includes three accumulators connected in series. Among the three accumulators, a first accumulator receives an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle and accumulates input phase codes for different FSM cycles to generate a first order phase code at each FSM cycle; a second accumulator accumulates the input phase codes and first order phase codes for different FSM cycles to generate a second order phase code at each FSM cycle; and a third accumulator accumulates the input phase codes and second order phase codes for different FSM cycles to generate a third order phase code at each FSM cycle.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: March 5, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Hsiang Lan, Cheng-Hsiang Hsieh
  • Patent number: 10187085
    Abstract: The present discloses provides a decoding method, decoding apparatus and decoder for correcting burst errors. In particular, the decoding method for correcting burst errors comprises: computing an initial syndrome of a received data frame, wherein the data frame is encoded according to cyclic codes for correcting burst errors; determining error correctability of burst error contained in the data frame based on the computed initial syndrome; and processing the burst error in the data frame and outputting the processed data frame based on the determined error correctability. With the decoding method, decoding apparatus, and decoder of the present invention, error correctability of burst errors contained in a data frame can be determined before the data is send out, while having smaller decoding latency through determining the error correctability and error pattern of the burst errors contained in the data frame using initial syndrome of the data frame.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: January 22, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng Wei Song, Hao Yang, Fan Zhou, Hou Gang Li, Yufei Li
  • Patent number: 10185413
    Abstract: In one embodiment, a computer-readable non-transitory storage medium embodies logic that is configured when executed to determine a first correlation between first consecutive edges of a synchronization signal and a pre-determined coefficient vector. The logic is further configured when executed to determine a second correlation between second consecutive edges of the synchronization signal and the pre-determined coefficient vector and synchronize one or more timings for communication between a stylus and a device based at least in part on the first and second correlations.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: January 22, 2019
    Assignee: Wacom Co., Ltd.
    Inventors: Vemund Bakken, Eivind Holsen
  • Patent number: 10184981
    Abstract: Provided is an apparatus for measuring an input time of an input signal, and more particularly, an apparatus for measuring an input time of an input signal more precisely than a reference clock using a delay circuit. The apparatus for measuring an input time of an input signal includes: a signal input unit receiving a signal; a clock generation unit generating a reference clock; a delay unit including at least one delay circuit generating at least one delayed clock by delaying the reference clock; a detection unit detecting a signal input from the signal input unit, depending on a clock signal input from the clock generation unit and delay circuits; and an operation unit operating an input time of an input signal from the signal input unit based on data detected by the detection unit.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: January 22, 2019
    Assignee: Korea Aerospace Research Institute
    Inventors: Jae-Won Chang, Tae-Sik Kim, Jung Wook Hyun