Phase Displacement, Slip Or Jitter Correction Patents (Class 375/371)
  • Patent number: 10250074
    Abstract: To prevent an overvoltage from being applied to a load in a power reception circuit of a power supply system. A power supply system is provided which includes a power supply device equipped with a power supply coil, and a power reception device equipped with a power reception coil. When a resonance circuit is in a resonance state, a peak voltage value of a voltage generated in the power reception coil is set higher than a prescribed voltage value. When the resonance circuit is in a non-resonance state, the peak voltage value of the voltage generated in the power reception coil is set lower than the prescribed voltage value.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: April 2, 2019
    Assignee: ABLIC INC.
    Inventor: Norihiro Okazaki
  • Patent number: 10224978
    Abstract: Circuits and methods for performing a clock and data recovery are disclosed. In one example, a clock and data recovery circuit is disclosed. The circuit includes a third order digital filter, e.g. a finite state machine (FSM) that includes three accumulators connected in series. Among the three accumulators, a first accumulator receives an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle and accumulates input phase codes for different FSM cycles to generate a first order phase code at each FSM cycle; a second accumulator accumulates the input phase codes and first order phase codes for different FSM cycles to generate a second order phase code at each FSM cycle; and a third accumulator accumulates the input phase codes and second order phase codes for different FSM cycles to generate a third order phase code at each FSM cycle.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: March 5, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Hsiang Lan, Cheng-Hsiang Hsieh
  • Patent number: 10185413
    Abstract: In one embodiment, a computer-readable non-transitory storage medium embodies logic that is configured when executed to determine a first correlation between first consecutive edges of a synchronization signal and a pre-determined coefficient vector. The logic is further configured when executed to determine a second correlation between second consecutive edges of the synchronization signal and the pre-determined coefficient vector and synchronize one or more timings for communication between a stylus and a device based at least in part on the first and second correlations.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: January 22, 2019
    Assignee: Wacom Co., Ltd.
    Inventors: Vemund Bakken, Eivind Holsen
  • Patent number: 10184981
    Abstract: Provided is an apparatus for measuring an input time of an input signal, and more particularly, an apparatus for measuring an input time of an input signal more precisely than a reference clock using a delay circuit. The apparatus for measuring an input time of an input signal includes: a signal input unit receiving a signal; a clock generation unit generating a reference clock; a delay unit including at least one delay circuit generating at least one delayed clock by delaying the reference clock; a detection unit detecting a signal input from the signal input unit, depending on a clock signal input from the clock generation unit and delay circuits; and an operation unit operating an input time of an input signal from the signal input unit based on data detected by the detection unit.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: January 22, 2019
    Assignee: Korea Aerospace Research Institute
    Inventors: Jae-Won Chang, Tae-Sik Kim, Jung Wook Hyun
  • Patent number: 10187085
    Abstract: The present discloses provides a decoding method, decoding apparatus and decoder for correcting burst errors. In particular, the decoding method for correcting burst errors comprises: computing an initial syndrome of a received data frame, wherein the data frame is encoded according to cyclic codes for correcting burst errors; determining error correctability of burst error contained in the data frame based on the computed initial syndrome; and processing the burst error in the data frame and outputting the processed data frame based on the determined error correctability. With the decoding method, decoding apparatus, and decoder of the present invention, error correctability of burst errors contained in a data frame can be determined before the data is send out, while having smaller decoding latency through determining the error correctability and error pattern of the burst errors contained in the data frame using initial syndrome of the data frame.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: January 22, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng Wei Song, Hao Yang, Fan Zhou, Hou Gang Li, Yufei Li
  • Patent number: 10187498
    Abstract: A method for setting a waiting time duration includes: controlling a target component to send preset data to a processor a plurality of times, and controlling the processor to receive the preset data sent by the target component each time based on a different waiting time duration; determining, from the different waiting time durations, a maximum waiting time duration and a minimum waiting time duration that are used by the processor for correctly receiving the preset data; and determining and storing a to-be-used waiting time duration according to the maximum waiting time duration and the minimum waiting time duration.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: January 22, 2019
    Assignee: Xiaomi Inc.
    Inventors: Zhongshuai Wang, Yizhen Yang, Ning Ma
  • Patent number: 10096203
    Abstract: In one aspect, there is described a computer-implemented method of configuring timeout values for an electronic gaming system. The electronic gaming system includes an electronic gaming machine and a first host coupled to the electronic gaming machine through a network. The method includes: receiving a command to initiate timeout calibration through an input interface associated with the electronic gaming system; and in response to receiving the command: i) sending a plurality of test messages between the electronic gaming machine and the first host; ii) determining transmission times for the test messages; iii) based on the determined transmission times, automatically determining one or more timeout values; and iv) configuring one or both of the electronic gaming machine and the first host based on the determined timeout values.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: October 9, 2018
    Assignee: IGT Canada Solutions ULC
    Inventors: Bradley Boudreau, Yan Meunier
  • Patent number: 10057050
    Abstract: A signal recovery circuit includes an oscillator configured to control a frequency of generating first clock, and a feedback circuit configured to control the oscillator in order that input data is synchronized with the first clock in accordance with a phase relation between the input data and the first clock, wherein the feedback circuit includes a controller configured to control the oscillator in accordance with the phase relation between the input data and the first clock, a first phase detector configured to generate a clock phase control signal in accordance with the phase relation between the input data and the first clock, and a state detection circuit configured to detect whether the signal recovery circuit is in a locked state or an unlocked state, based on a magnitude of an amplitude of a first component or a second component of the clock phase control signal.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: August 21, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Yukito Tsunoda
  • Patent number: 10044539
    Abstract: Embodiments of the present disclosure relate to methods and device for receiving PAM data stream. In an embodiment, a method comprises receiving a signal stream modulated with pulse amplitude modulation (PAM) associated with a plurality of bit patterns; determining boundary voltages for the plurality of bit patterns; and calibrating, based on the boundary voltages, a threshold voltage for use in recognition of the plurality of bit patterns. In this way, bit patterns may be accurately recognized based on the calibrated threshold voltage.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: August 7, 2018
    Assignee: Lattice Semiconductor Corporation
    Inventors: Qiming Wu, Bing Zhang, Fei Song
  • Patent number: 10038507
    Abstract: An increase in circuit scale is suppressed and a phase variation caused in a transmission path or the like is compensated for.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: July 31, 2018
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Mitsuteru Yoshida, Etsushi Yamazaki, Seiji Okamoto, Hiroyuki Uzawa, Kengo Horikoshi, Koichi Ishihara, Takayuki Kobayashi, Yoshiaki Kisaka, Masahito Tomizawa, Naoki Fujiwara, Tomoyoshi Kataoka, Kazushige Yonenaga
  • Patent number: 9973332
    Abstract: An electronic apparatus including a PLL unit to an original clock signal, a pair of phase interpolators, a sampler, a phase detector, a control unit and a loop filter is provided. The phase interpolators receive the original clock signal and generate a reference clock signal and an auxiliary clock signal offset by 90 degrees having transition edges. The sampler samples an input data signal at each of the transition edge. The phase detector determines a phase difference of a data transition of the input data signal relative to the reference clock signal. The control unit superimposes an adjusting phase on phases of the reference clock signal and the auxiliary clock signal according to the phase difference. The phase detector determines that the phase difference is within a predetermined range. The loop filter superimposes a varying phase on the phases of the reference clock signal and the auxiliary clock signal accordly.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: May 15, 2018
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Hong-Yean Hsieh
  • Patent number: 9960902
    Abstract: An example method of clock and data recovery in a receiver includes generating data samples and crossing samples of a received signal based on a data clock signal and a crossing clock signal, respectively, which are derived from a sampling clock signal; adjusting a phase of the sampling clock signal using a clock and data recovery (CDR) circuit based on the data samples and the crossing samples; adjusting relative phase between the data clock signal and the crossing clock signal from a first phase difference to a second phase difference that is less than ninety degrees; and reverting the relative phase between the data clock signal and the crossing clock signal to the first phase difference after a threshold time period.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: May 1, 2018
    Assignee: XILINX, INC.
    Inventors: Winson Lin, Yu Xu, Caleb S. Leung, Alan C. Wong, Christopher J. Borrelli, Yohan Frans, Kun-Yung Chang
  • Patent number: 9906231
    Abstract: A clock and data recovery (CDR) circuit is provided, and includes a sampling circuit, an error sampler, a phase detect circuit, and a phase adjust circuit. The sampling circuit generates a data signal according to an input data and a first clock signal, and generates an edge signal according to the input data and a second clock signal. The error sampler compares the input data with a reference voltage according to the first clock signal to generate a control signal. The phase detect circuit receives the control signal and generates a corrective signal according to the data signal and the edge signal. When the values of the control signal and the data signal are different, the phase detect circuit stops transmitting the corrective signal. The phase adjust circuit generates and adjusts the first and the second clock signal according to the corrective signal.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: February 27, 2018
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Juh Kang, Yen-Chung Chen, Chen-Yang Pan
  • Patent number: 9892712
    Abstract: Techniques related to filtering hot plug signals are described herein. The techniques include receiving a first hot plug detect (HPD) signals and a second HPD signal from an external display device. A time period between receiving the first and second HPD signals is determined, and the first and second HPD signals are filtered based on the determined time period.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: February 13, 2018
    Assignee: Intel Corporation
    Inventors: Saran Chandra, Vandana Kannan, Ganesh Ram Sumaithangi Thattai
  • Patent number: 9857973
    Abstract: An interface circuit may include a first FIFO circuit and a second FIFO circuit. The first FIFO circuit may generate first output data based on a first sampling signal and a second sampling signal. The second FIFO circuit may generate second output data based on a third sampling signal and a fourth sampling signal. The first FIFO circuit and the second FIFO circuit may be cross-reset.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: January 2, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwanyeob Chae, Yoonjee Nam, Ji Hun Oh, Shinyoung Yi, Jong-Ryun Choi
  • Patent number: 9832551
    Abstract: An optical transmission device includes: a receiver configured to receive a signal including data; a generator configured to generate an output clock to output the data based on a signal clock synchronized with the signal; and a controller configured to control a frequency of the output clock based on a first amount of the data so that the output clock follows a clock of a transmission source of the data.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: November 28, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Hiroshi Yoshida
  • Patent number: 9733731
    Abstract: In one embodiment, a stylus includes a controller, a delay line, a coefficient line and a computer-readable non-transitory storage medium. The controller is operable to receive a synchronization signal that is transmitted from a computing device and received by the stylus. The delay line is operable to store a first consecutive edges of the synchronization signal. The coefficient line includes a pre-determined coefficient vector.
    Type: Grant
    Filed: May 12, 2014
    Date of Patent: August 15, 2017
    Assignee: Atmel Corporation
    Inventors: Vemund Bakken, Eivind Holsen
  • Patent number: 9692401
    Abstract: A skew adjustment circuit comprises a phase adjustment circuit that adjusts a phase of a first input clock based on a predetermined phase control signal, and outputs it as an output clock, a logical circuit that performs a logical operation between signals that are input, an integral circuit that generates a predetermined voltage signal, based on a result of the logical operation by the logical circuit, a comparator that compares an electric potential of the predetermined voltage signal and an electric potential of a predetermined reference voltage signal, a first controller that generates the predetermined phase control signal based on a result of the comparison by the comparator, and a second controller that performs control for selecting a signal that is to be input to the logical circuit. The second controller, in a first mode, performs the control such that the output clock and a second input clock are selected.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: June 27, 2017
    Assignee: MegaChips Corporation
    Inventor: Shingo Adachi
  • Patent number: 9692588
    Abstract: A method of performing synchronization in a super regenerative receiver (SRR) includes setting a quench rate of the SRR to a value of 1.5 times a chip rate of an incoming signal, acquiring an expected preamble sequence of an arbitrary sample set among a plurality of possible sample sets, acquiring an expected start frame delimiter (SFD) sequence for all of the possible sample sets to achieve frame synchronization, computing respective correlation metrics for bits of the expected SFD sequence while the expected SFD sequence is acquired for all of the possible sample sets, calculating a decision metric based on the correlation metrics in response to an SFD sequence being detected for one or more of the possible sample sets, and identifying a best sample set for demodulating the incoming signal among all of the possible sample sets based on the decision metric to achieve pulse synchronization.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: June 27, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kiran Bynam, Sujit Jos, PS Chandrashekhar Thejaswi, ChangSoon Park, Jinesh P. Nair, Young-Jun Hong, Youngsoo Kim, Manoj Choudhary
  • Patent number: 9647781
    Abstract: A data reception device which receives data transmitted through a plurality of transmission lines. The data reception device includes a position detection unit which corrects a skew of data transmitted respectively through the plurality of transmission lines, and detects for each lane a position of a marker for identification of a lane which is assigned the data, and an information extraction unit which extracts identification information indicated by the marker for each lane using a result of the detection of the position of the marker by the position detection unit.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: May 9, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Katsutoshi Miyaji, Hiroyuki Homma, Ken Shiine, Hiromichi Makishima
  • Patent number: 9548727
    Abstract: An oscillator circuit includes: a plurality of delay elements, a first delay element configured to receive a first oscillator signal outputted from a second delay element in one stage before the first delay element and a second oscillator signal outputted from a third delay element in two or more stages before the first delay element, the plurality of delay terminals being connected in a ring by at least three or more delay elements, and the first oscillator signal and the second oscillator signal having phases different from one another; and a bias voltage generator configured to change a ratio of a first input bias current for the first oscillator signal to a second input bias current for the second oscillator signal, in accordance with a first bias voltage and a second bias voltage supplied to the plurality of delay elements.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: January 17, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Win Chaivipas
  • Patent number: 9531572
    Abstract: A system may include an interface circuit coupled to a wire bus. The interface circuit may receive a multi-level symbol according to a status of the wire bus. The interface circuit may include a clock recovery circuit configured to generate a recovered clock based on the multi-level symbol. The interface circuit may latch the multi-level symbol based on one of an external clock and the recovered clock according to an operation speed of the system.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: December 27, 2016
    Assignee: SK HYNIX INC.
    Inventors: Jong Joo Shim, Keun Soo Song
  • Patent number: 9509319
    Abstract: A clock and data recovery (CDR) circuit that receives an input signal and generates clock and sampled output signals includes a phase-frequency detector (PFD) circuit, a control circuit, a digital-to-analog converter (DAC), a current-controlled oscillator (CCO) and a data sampler. The PFD generates intermediate and fine digital control signals. The DAC receives the intermediate digital control signal as a coarse digital control signal and the fine digital control signal and generates an output current. The CCO receives the output current and generates the clock signal. The coarse digital control signal is used to coarse calibrate a frequency of the clock signal and the fine digital control signal is used to fine calibrate the frequency of the clock signal. The data sampler receives the clock signal and samples the input signal at the frequency of the clock signal to generate the sampled output signal.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: November 29, 2016
    Assignee: SILAB TECH PVT. LTD.
    Inventors: Biman Chattopadhyay, Ravi Mehta, Gopal Krishna Ullal Nayak, Sharath Bhat N
  • Patent number: 9509487
    Abstract: Method and apparatus for generating a jitter reduced clock signal from signal transmitted over a communication medium includes receiving, with high speed data interface circuitry, a modulated signal that includes a binary encoded data stream. A recovered clock signal is generated from the modulated signal and tracks the long-term drift in the modulated signal. A jitter reduced clock signal is generated by filtering the recovered clock signal with a filtering circuit having a bandwidth sufficient to remove jitter while allowing the jitter reduced clock signal to track the drift in the modulated signal.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: November 29, 2016
    Assignee: CommScope Technologies LLC
    Inventors: Donald Robert McAllister, Christopher Goodman Ranson, Fred William Phillips
  • Patent number: 9509446
    Abstract: A signal transmission system includes: a signal sending device including a signal sender converting a sending signal to a transmission signal using a signal sending parameter and sends the transmission signal to a signal path, and a sending controller receiving a sending control signal and changes the signal sending parameter according to the sending control signal; and a signal receiving device including a signal receiver converting the transmission signal received via the signal path, to a reception signal using a signal reception parameter, a signal reception monitor monitoring a signal reception status of the transmission signal and outputs monitor information acquired by the monitoring, and a reception controller checking transmission quality of the signal path using the monitor information, creates the sending control signal for changing the signal sending parameter according to a checking result to send, and changes the signal reception parameter.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: November 29, 2016
    Assignee: NEC CORPORATION
    Inventor: Tomohiro Takahashi
  • Patent number: 9490872
    Abstract: A reduced-memory vectored DSL system reduces the bandwidth and memory storage demands on a vectored DSL system in which FEXT data is transmitted and stored. When test signal data, such as training and/or tracking data, is sent to determine FEXT characteristics of the DSL system, error signals are available for all or substantially all of the upstream and/or downstream frequency band DSL tones used in the system. Dividing a frequency band into sub-bands, only a subset of tones in each sub-band is used for deriving FEXT data. For tones in the sub-band subsets, full-precision FEXT data values can be derived. For other tones, approximations of the FEXT data can be derived. Memory is reduced in both the transmission of such FEXT data (between upstream and downstream ends) and within an upstream-end device such as a DSLAM that performs vectoring using a separate or internal vectoring processing apparatus.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: November 8, 2016
    Assignee: Ikanos Communications, Inc.
    Inventors: Nicholas P. Sands, Kevin D. Fisher
  • Patent number: 9479365
    Abstract: A method for performing loop unrolled decision feedback equalization (DFE) and an associated apparatus are provided.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: October 25, 2016
    Assignee: MEDIATEK INC.
    Inventors: Tsung-Hsin Chou, Chih-Hsien Lin, Huai-Te Wang, Bo-Jiun Chen, Yan-Bin Luo
  • Patent number: 9471430
    Abstract: A semiconductor device includes an internal circuit configured to perform a specified operation in response to a predetermined command; a normal data input/output section configured to input/output a normal data synchronized with a center of a source clock, in response to data input/output commands; and a data recovery information signal input/output block configured to receive and store a data recovery information signal synchronized with an edge of the source clock and having a predetermined pattern, in response to either a command of the data input/output commands or the predetermined command upon entry to a data recovery operating mode, and to output the data recovery information signal after the passage of a predetermined time period.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: October 18, 2016
    Assignee: SK Hynix Inc.
    Inventor: Jung-Hoon Park
  • Patent number: 9413389
    Abstract: An electronic device includes a transmission module communicatively coupled to a synchronizer. The transmission module is configured to transform received data for transmission, receive a first instruction from the synchronizer, based on the instruction adjust the phase of a clock signal used to time the transformation of the received data, and send the adjusted clock signal to the synchronizer. The synchronizer is configured to receive the adjusted clock signal, receive a data signal comprising a frequency and a phase of data to be transmitted, based on the adjusted clock signal and the data signal, determine a second instruction for the transmission module, and provide the second instruction to the transmission module.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: August 9, 2016
    Assignee: Fujitsu Limited
    Inventors: Nikola Nedovic, Shuo-Chun Kao
  • Patent number: 9411773
    Abstract: Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchronizing the data input and/or output communication, and a mode input for controlling the data input and/or output communication. A clock/mode signal connects to the clock input of one circuit and to the mode input of the other circuit. A mode/clock signal connects to the mode input of the one circuit and to the clock input of the other circuit. The role of the mode and clock signals on the mode/clock and clock/mode signals, or their reversal, selects one or the other of the data communication circuits.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: August 9, 2016
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 9407388
    Abstract: The embodiments herein relate to a method in a communications network comprising a communications link connecting a first device to a second device. The communications link comprises an upper layer having a variable delay and a lower layer having a constant delay. The first device comprises a first clock and the second device comprises a second clock. The communications network synchronizes the first clock via the lower layer of the communications link with the second clock. The communications network determines, at the second device, a residence time for a first message when transmitted from the first device to the second device via the upper layer of the communications link.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: August 2, 2016
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (publ)
    Inventors: Hakan Grenabo, Per-Arne Thorsen
  • Patent number: 9383967
    Abstract: System and method for hardware implemented accumulation of waveform data. A digitizer is provided that includes: a circuit, and first and second memory banks, coupled to the circuit. The circuit may be configured to: store a first subset of the waveforms in the first memory bank, accumulate each waveform in a chunk-wise manner, where each chunk has a specified size, thereby generating a first bank sum including a first partial accumulation of the set of waveforms, store a second subset of waveforms in the second memory bank concurrently with the accumulation, and accumulate each waveform of the second subset of waveforms in a chunk-wise manner, thereby generating a second bank sum including a second partial accumulation of the set of waveforms, where the first and second partial accumulations of the set of waveforms are useable to generate an accumulated record of the set of waveforms.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: July 5, 2016
    Assignee: National Instruments Corporation
    Inventors: Anita L. Salmon, Jeff A. Bergeron, Andrew C. Thomson
  • Patent number: 9377993
    Abstract: Embodiments of methods that are useful to avoid overflow in fixed-length buffers. In one embodiment, the methods dynamically adjust parameters (e.g., sample time) and reconfigure data in the buffer to allow new data samples to fit in the buffer. These embodiments allow data collection to automatically adapt, e.g., by adjusting the sample rate to allow the data to fit in the limited buffer size. These embodiments can configure hardware and/or software on a valve positioner of a valve assembly to improve data collection for use in on-line valve diagnostics and other data processing techniques.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: June 28, 2016
    Assignee: Dresser, Inc.
    Inventors: Larry Gene Schoonover, Arkady Khasin, Vladimir Dimitrov Kostadinov, Justin Scott Shriver
  • Patent number: 9369119
    Abstract: A critical path monitor (CPM) having a set of split paths is configured in an integrated circuit (IC) that includes a corresponding set of critical paths. A first and a second split path is configured with a first and a second simulated delay sections and fine delay sections, respectively. A delay of each of the first and second fine delay sections is adjustable in several steps. The delay of the first fine delay section is adjustable differently from the delay of the second fine delay section in response to a common operating condition change. Differently adjusting the delays of the first and the second fine delay sections causes an edge of a pulse to be synchronized between a first edge detector located after the first simulated delay section and a second edge detector located after the second simulated delay section.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: June 14, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Alan James Drake, Michael Stephen Floyd, Pawel Owczarczyk, Gregory Scott Still, Marshall Dale Tiner, Xiaobin Yuan
  • Patent number: 9354990
    Abstract: Various examples of techniques for identifying a corrupt data lane and using a spare data lane are described herein. Some examples include a method of coordinating spare lane usage between link partners. One such example comprises analyzing data from a link partner to identify a corrupt lane, and communicating the corrupt lane to the link partner, wherein the communication does not require sideband communication channel. In some embodiments, communicating the corrupt lane to the link partner comprises identifying a transmit lane corresponding to the corrupt lane, transmitting a set of data intended for a corresponding transmit lane using a spare data lane, and transmitting bad data to the link partner using the corresponding transmit lane.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: May 31, 2016
    Assignee: International Business Machines Corporation
    Inventors: Etai Adar, Yiftach Benjamini, Pavel Granovsky
  • Patent number: 9344103
    Abstract: A circuit includes: a rectifier configured to receive a first clock signal and a second clock signal and output a rectified signal, wherein the second clock signal is the same as the first clock signal except for an offset in timing; a low-pass filter configured to receive the rectified signal and output a filtered signal; and an analog-to-digital converter configured to convert the filtered signal into a digital signal.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: May 17, 2016
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Chia-Liang (Leon) Lin
  • Patent number: 9344270
    Abstract: Techniques for detecting and correcting phase discontinuity of a local oscillator (LO) signal are disclosed. In one design, a wireless device includes an LO generator and a phase detector. The LO generator generates an LO signal used for frequency conversion and is periodically powered on and off. The phase detector detects the phase of the LO signal when the LO generator is powered on. The detected phase of the LO signal is used to identify phase discontinuity of the LO signal. The wireless device may further include (i) a single-tone generator that generates a single-tone signal used to detect the phase of the LO signal, (ii) a downconverter that downconverts the single-tone signal with the LO signal and provides a downconverted signal used by the phase detector to detect the phase of LO signal, and (iii) phase corrector that corrects phase discontinuity of the LO signal in the analog domain or digital domain.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: May 17, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Li Liu, Praveen-Kumar Sampath, Lai Kan Leung, Chiewcharn Narathong, Soon-Seng Lau, Ketan Humnabadkar, Raghu Narayan Challa, Devavrata Vasant Godbole
  • Patent number: 9317364
    Abstract: Methods, apparatuses, and systems are described related to memory controllers for memory. In one embodiment, a memory controller may include a distribution transformer configured to receive data to be stored into a memory, wherein the data has a distribution of m1:n1 ratio for bits having a first logic value and bits having a second logic value, where m1 and n1 are real numbers. The distribution transformer may transform the data into skewed data, wherein the skewed data has a distribution of m2:n2 ratio for bits having the first logic value and bits having the second logic value, where m2 and n2 are real numbers that are different from one another and respectively differ from m1 and n1. The distribution transformer may output the skewed data for storage in the memory. Other embodiments may be described and claimed.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: April 19, 2016
    Assignee: Intel Corporation
    Inventors: Ravi H. Motwani, Kiran Pangal
  • Patent number: 9285861
    Abstract: Power saving in computing devices is provided. A first computing device communicates with a second computing device using a first set of tones. A low power event is detected by the first computing device. In response to the detected low power event, a request to communicate using a second set of tones is sent to the second computing device by the first computing device. The second set of tones has fewer tones than the first set of tones, and may be a subset of the first set of tones.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: March 15, 2016
    Assignee: ARRIS Enterprises, Inc.
    Inventor: Selvamani Rajagopal
  • Patent number: 9231569
    Abstract: An apparatus is provided. The apparatus includes a flip-flop including an input configured to receive a setup time and delay control (SDC) signal, and an output buffer including first and second conductive paths. The second conductive path is non-conductive when the SDC signal has a first value at the input and is conductive when the SDC signal has a second value at the input. The apparatus includes a propagation delay sensor configured to estimate a propagation delay of the flip-flop, and, when the estimated propagation delay exceeds a threshold, supply the SDC signal having the second value to the input of the flip-flop.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: January 5, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Alexandro Giron Allende
  • Patent number: 9223541
    Abstract: Various methods and apparatus for managing signals between a processor and a memory device are disclosed. In one aspect, a method of managing signals between a processor and a memory device wherein the processor and the memory device are operatively coupled by a data signal path and a clock signal path is provided. The method includes setting the skew between the data signal path and the clock signal path away from a spectral peak of a phase jitter transfer function.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: December 29, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Shadi Barakat
  • Patent number: 9210351
    Abstract: According to one embodiment, a signal transmission apparatus being AC-coupled with a receiving apparatus through a digital transmission line includes a transmitting module configured to transmit a differential signal based on an encoded bit serial input signal such that a low frequency component of the differential signal to be transmitted is maintained at a constant level when the differential signal based on the encoded bit serial input signal is transmitted to the digital transmission line where the encoded bit serial input signal includes a ratio of the number of logic 1 to the number of logic 0 which is different from 5:5.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: December 8, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuaki Suzuki, Takashi Doi, Masahiko Mawatari
  • Patent number: 9207705
    Abstract: Embodiments of a jitter detection circuit are disclosed that may allow for detecting both cycle and phase jitter in a clock distribution network. The jitter detection circuit may include a phase selector, a data generator, a delay chain, a logic circuit, and clocked storage elements. The phase selector may be operable to select a clock phase to be used for the launch clock, and the data generator may be operable to generate a data signal responsive to the launch clock. The delay chain may generate a plurality of outputs dependent upon the data signal, and the clocked storage elements may be operable to capture the plurality of outputs from the delay chain, which may be compared to expected data by the logic circuit.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: December 8, 2015
    Assignee: Apple Inc.
    Inventors: Greg M Hess, James E Burnette, II
  • Patent number: 9191186
    Abstract: A device compensates for distortions of a serial data signal introduced by a communication channel in a serial communication system. The device includes main path, first and second delay paths, first and second pulse generators, and combiner. The first and second delay paths delay a tapped-off portion of the serial data signal by first and second delay amounts, respectively, where the first delay amount is less than a main path delay amount and the second delay amount greater the main path delay amount. The first and second pulse generators generate first and second compensation pulses in response to the serial data signal delayed by the first and second delay amounts, respectively. The combiner combines the first and second compensation pulses with the main path delayed serial data signal, where the first and second compensation pulses compensate for magnitude loss and nonlinear phase of the main path delayed serial data signal.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: November 17, 2015
    Assignee: Keysight Technologies, Inc.
    Inventors: Michael J. Lujan, Keith C. Griggs
  • Patent number: 9178551
    Abstract: Circuits and methods comprising: a radio frequency amplifier that powers off in response to an enable signal; a demodulator that outputs an RZ signal; an all-digital clock and data recovery circuit comprising: a phase detector that includes a tri-state phase frequency detector for use when in an acquisition mode and a Hogge phase detector for use when in a communication mode, that receives the RZ signal, and that outputs a phase detector output from the tri-state phase frequency detector when in the acquisition mode and from the Hogge phase detector when in the communication mode, a loop filter that receives the phase detector output from the phase detector and produces a loop filter output that is the sum of a proportional path of the loop filter and an integral path of the loop filter, and a numerical controlled oscillator that receives the loop filter output and produces the enable signal.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: November 3, 2015
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: Baradwaj Vigraham, Peter R Kinget
  • Patent number: 9178689
    Abstract: The present invention relates to a method includes: implementing, by the board in the BBU1, frequency synchronization between a system clock of the board in the BBU1 and a system clock of the board in the BBU0 by using a synchronous Ethernet clock that is output by the board in the BBU0; and implementing, by the board in the BBU1, time synchronization between the system clock of the board in the BBU1 and the system clock of the board in the BBU0 by using an IEEE1588 clock that is output by the board in the BBU0. The present invention can enable the multimode base station to support more standards.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: November 3, 2015
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Weidong Yu
  • Patent number: 9172523
    Abstract: A lens apparatus is detachable from an image pickup apparatus. The lens apparatus includes a controller configured to communicate with the image pickup apparatus in synchronization with a first signal. A communication contains a plurality of blocks in the same cycle of the first signal. The controller transmits information of a first time period to the image pickup apparatus, and prohibits a communication of an m-th block from starting before the first time period passes after a communication of an n-th block starts or ends where n is an integer equal to or larger than 1 and m is an integer larger than n.
    Type: Grant
    Filed: May 8, 2013
    Date of Patent: October 27, 2015
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Koji Okada
  • Patent number: 9160322
    Abstract: The present invention discloses a clock edge detection device capable of detecting the positive and negative edges of a target clock, comprising: a delay circuit for receiving the target clock and transmitting it; a register circuit coupled to the delay circuit for recording and outputting plural target clock levels in accordance with a working clock; a positive edge detection circuit including a plurality of positive edge detectors coupled to the register circuit for detecting the positive edge of the target clock; and a negative edge detection circuit including a plurality of negative edge detectors coupled to the register circuit for detecting the negative edge of the target clock, wherein the positive edge detection circuit is operable to perform a logic operation to the target clock levels while the negative edge detection circuit is operable to perform a different logic operation to the target clock levels.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: October 13, 2015
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Yu-Cheng Lo, Ying-Yen Chen, Chao-Wen Tzeng, Jih-Nung Lee
  • Patent number: 9159388
    Abstract: A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The memory controller can perform maintenance operations to update the phase relationship between the phase-providing and data-sampling signals.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: October 13, 2015
    Assignee: Rambus Inc.
    Inventors: Scott C. Best, Richard E. Warmke, David B. Roberts, Frank Lambrecht
  • Patent number: 9148277
    Abstract: A system includes a memory controller and a plurality of semiconductor devices that are series-connected. Each of the devices has memory core for storing data. The memory controller provides a clock signal for synchronizing the operations of the devices. Each device includes a phase-locked loop (PLL) that is selectively enabled or disabled by a PLL enable signal. In each group, the PLLs of a selected number of devices are enabled by PLL enable signals and the other devices are disabled. The enabled PLL provides a plurality of reproduced clock signals with a phase shift of a multiple of 90° in response to an input clock signal. The data transfer is synchronized with at least one of the reproduced clock signals. In the devices of disabled PLLs, the data transfer is synchronized with the input clock signal. The enabled PLL and disabled PLL cause the devices to be the source and the common synchronous clocking, respectively. The devices can be grouped.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: September 29, 2015
    Assignee: NovaChips Canada Inc.
    Inventors: Hong Beom Pyeon, Peter Gillingham