Phase Locking Patents (Class 375/373)
  • Patent number: 11509971
    Abstract: In one embodiment, a system includes a CATV node, a first device, and at least one micro distribution system. The CATV node transmits CATV RF signals to the first device, which converts the RF signals to optical signals. Each micro distribution system includes a micro node receiving the optical signals from the first device and converting the optical signals to RF signals. Each micro distribution system further includes at least two strings of taps independently coupled to the micro node and receiving the RF signals from the micro node. Each string of taps is terminated at an end by a low pass filter (LPF). For each string of taps, the received RF signals are passed from the micro node along the taps and blocked by the LPF, while a powering signal is passed along the taps and through the LPF.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: November 22, 2022
    Inventor: David E. Wachob
  • Patent number: 11469747
    Abstract: A shift register generates a synthesized pulse having a different pulse width according to which one of a first phase pulse and a second phase pulse is inputted, generates an internal shifted synthesized pulse and a shifted synthesized pulse from the synthesized pulse, and generates a detection signal by detecting a pulse width of the internal shifted synthesized pulse. The shift register outputs the shifted synthesized pulse as one of a first shifted phase pulse and a second shifted phase pulse based on the detection signal.
    Type: Grant
    Filed: December 15, 2021
    Date of Patent: October 11, 2022
    Assignee: SK hynix Inc.
    Inventors: Geun Ho Choi, Young Hyun Baek
  • Patent number: 11411560
    Abstract: An electronic system, an integrated circuit die and an operation method thereof are provided. The integrated circuit die includes a plurality of interface circuit slices and a merging circuit. The transmission data stream sent from the transmitter die is split into a plurality of sub-data streams. Each of the interface circuit slices provides a physical layer to receive the corresponding one of the sub-data streams. The merging circuit is coupled to the interface circuit slices to receive the sub-data streams. The merging circuit merges the sub-data streams from the interface circuit slices back to the original data corresponding to the transmission data stream to be provided to an application layer. The merging circuit aligns the sub-data streams from the interface circuit slices in timing to mitigate different delays of the interface circuit slices.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: August 9, 2022
    Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei Yu, Yung-Sheng Fang, Chang-Ming Liu, Igor Elkanovich
  • Patent number: 11315613
    Abstract: Systems and methods for operating a digital-to-analog converter (DAC) are described. In an example, a device can receive a digital input. The device can generate a clock signal having frequency in radio frequency (RF) range. The device can combine the digital input with the clock signal to generate a first voltage signal. The device can convert the first voltage signal into a second voltage signal having at least two phases. The device can convert the second voltage signal into a current signal. The device can distribute the current signal to at least one current mode DAC.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: April 26, 2022
    Assignee: International Business Machines Corporation
    Inventors: Sudipto Chakraborty, Rajiv Joshi, Steven J. Holmes, Bruce B. Doris
  • Patent number: 11283586
    Abstract: A predefined signal has been used to facilitate the detection of the clock rate difference between the transmitter and the receiver. First the predefined signal is to be detected by each of the sensors and its time frame boundary information is acquired by a detector. The detector is composed of a matched filter bank, an event detector and a state sequence detector. The phase error is derived with reference to a fixed reference stored. With each of the sensors updating its local clock to the same fixed reference they can be brought to an arbitrary close clock error with one another. Thus, by applying the method disclosed here the transmitter and all the receivers can have an arbitrary small clock rate error with respect to one another. The method described is really fast in the sense that the delay needed for the detection and adjustment is minimal.
    Type: Grant
    Filed: September 5, 2020
    Date of Patent: March 22, 2022
    Inventor: Francis Tiong
  • Patent number: 11209858
    Abstract: The present disclosure relates to systems and methods to maintain clock synchronization of multiple computers, or computer systems, through the exchange of communication messages that include clock and/or timing information.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: December 28, 2021
    Assignee: THE CHARLES STARK DRAPER LABORATORY, INC.
    Inventors: Eric Karl Mautner, Brianna Klingensmith
  • Patent number: 11177815
    Abstract: Provided herein are gap detection and compensation schemes for timing alignment systems. In certain embodiments, a timing alignment system includes a detector that generates one or more loop control signals based on comparing a reference clock signal to a feedback clock signal, a loop filter having a loop voltage that is adjusted based on the one or more loop control signals, and a gap detection and compensation circuit that processes the one or more loop control signals to detect a gap in at least one of the reference clock signal or the feedback clock signal. In response to detecting the gap, the gap detection and compensation circuit modifies the one or more loop control signals to provide an adjustment to the loop voltage.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: November 16, 2021
    Assignee: Analog Devices International Unlimited Company
    Inventors: Siwen Liang, Marlon Consuelo Maramba, Alberto Marinas
  • Patent number: 10963002
    Abstract: An in-phase/quadrature (I/Q) clock generator is described. The I/Q clock generated includes a poly-phase filter configured to generate a four-phase quadrature clock signal in response to a two-phase quadrature clock signal generated in response to a single-ended input clock signal. The I/Q clock generated also includes a phase interpolator configured to generate an output four-phase quadrature clock signal from the four-phase quadrature clock signal. The I/Q clock generated further includes a poly-phase filter tune circuit coupled to an output of the phase interpolator. The poly-phase filter tune circuit is configured to generate a control voltage for the poly-phase filter to tune the four-phase quadrature clock signal from the poly-phase filter.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: March 30, 2021
    Assignee: QUALCOMM Incorporated
    Inventor: Madjid Hafizi
  • Patent number: 10840924
    Abstract: Apparatuses and methods for phase interpolators are provided. An example apparatus comprises a phase interpolator and a controller coupled to the phase interpolator. The controller is configured to provide a digital timing code to the phase interpolator, and the phase interpolator is configured to apply a correction to the received digital timing code based, at least in part, on phase interpolator error correction data from a data structure containing phase interpolator error correction data.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: November 17, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Steven G. Wurzer, Neil Petrie, Joseph P. Kerzman, Kevin R. Duncan
  • Patent number: 10833681
    Abstract: This disclosure relates to a receiver comprising a clock and data recovery loop and a phase offset loop. The clock and data recovery loop may be controlled by a sum of gradients for a plurality of data interleaves. The phase offset loop may be controlled by an accumulated differential gradient for each of the data interleaves.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: November 10, 2020
    Assignee: NVIDIA Corp.
    Inventors: Gaurawa Kumar, Ky-Anh Tran, Olakanmi Oluwole, Vishnu Balan
  • Patent number: 10790959
    Abstract: A circuit includes a voltage-controlled oscillator (VCO) and a frequency divider. The frequency divider input is coupled to the VCO output. The circuit further includes a phase-frequency detector (PFD). A control output of the PFD is coupled to the VCO. A first PFD input is coupled to a first frequency divider output, and a second PFD input is coupled to a second frequency divider output. The first frequency divider output is configured to provide a first frequency divider signal and the second frequency divider output is configured to provide a second frequency divider signal 90 degrees out of phase with respect to the first frequency divider signal. The PFD is configured to detect an occurrence of at least two edges of a signal on the data input while the second frequency divider signal is continuously logic high across the at least two edges.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: September 29, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Chen-Lun Yen, Ramsin Michael Ziazadeh, Xin Liu
  • Patent number: 10742390
    Abstract: A method for a Mobile Industry Processor Interface (MIPI) master device for improving clock recovery at a MIPI slave device includes: transmitting a symbol sequence including a plurality of consecutive symbols which include at least one of a first symbol value and a second symbol value to the MIPI slave device prior to transmitting packet data to the MIPI slave device, wherein the first symbol value and the second symbol value bring relatively larger encoding jitters than other symbol values.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: August 11, 2020
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Jen-Hao Liao, Yu-Hsun Peng
  • Patent number: 10735007
    Abstract: Limiting frequency overshoot in a timing recovery loop involves using a proportional-integral (PI) control system to discipline a frequency of an output signal of a voltage controlled oscillator (VCO) in accordance with a time reference signal. A control signal output of the PI control system is monitored to detect conditions which will prospectively cause an excess deviation of the VCO frequency. In response to detecting such a condition, an output of an integral error term generator of the PI control system is locked or held constant. This will have the effect of preventing the excess frequency deviation of the VCO.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: August 4, 2020
    Assignee: HARRIS GLOBAL COMMUNICATIONS, INC.
    Inventors: Brian R. Carlson, James McIntyre
  • Patent number: 10361708
    Abstract: Systems and methods related to phase-locked loops circuitry and lock-detect circuitry are provided. Some of the systems and methods allow sharing of lock-detect circuitries between multiple phase-locked loops or other suitable circuitry. Others allow multiple circuitries to select from multiple lock-detect circuitries that may use different lock-detect techniques.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: July 23, 2019
    Assignee: ALTERA CORPORATION
    Inventors: Christopher Thomas Moore, Bo Zhou, Rajiv Kane
  • Patent number: 10234267
    Abstract: An optical instrument including at least a first and second wavelength swept vertical cavity laser (VCL) sources. The wavelength sweeping ranges spanned by the first and second VCL sources may differ with a region of spectral overlap. The first and second VCL sources may be operable under different modes of operation, wherein the modes of operation differ in at least one of: sweep repetition rate, sweep wavelength range, sweep center wavelength, and sweep trajectory. A VCL source may also exhibit sweep-to-sweep variation. Apparatus and methods are described for aligning sample signal data from the first VCL and sample signal data from the second VCL to generate output digital data. The output digital data is aligned with respect to at least one of: wavelength, wavenumber, and interferometric phase. The apparatus and methods can also be used to phase stabilize successive sweeps from the same VCL source or wavelength swept source.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: March 19, 2019
    Assignees: THORLABS, INC., PRAEVIUM RESEARCH, INC.
    Inventors: Alex Cable, Vijaysekhar Jayaraman, James Jiang, Benjamin Potsaid
  • Patent number: 10205385
    Abstract: A circuit and method for a switching converter that modifies the clock frequency when the panic comparator is activated is proposed. This solution for a switching converter is achieved by increases in the switching frequency in response to an undershoot condition. In summary, a switching converter circuit, comprising at least one phase functional block configured to provide an output voltage, a panic comparator configured to evaluate voltage excursion conditions of the output voltage, and a clock generator with pulse insertion function wherein the pulse insertion function is configured to increase the switching frequency during a voltage excursion condition to minimize or mitigate voltage excursions. In addition, a switching converter circuit, comprising a clock generator with a pulse width extender configured to provide a signal to said pulse insertion function logic.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: February 12, 2019
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Seiichi Ozawa, Santhos Ario Wibowo
  • Patent number: 10187017
    Abstract: Systems and methods are provided for clocking scheme to reduce nonlinear distortion. An example system may comprise at least two processing paths, each comprising at least one circuit exhibiting nonlinear behavior. Nonlinearity may be managed during processing of signals, such as by assessing effects of the nonlinear behavior during the processing of signals, and controlling clocking applied via at least one path based on the assessed effects, to reduce the effects of the nonlinear behavior during the processing of signals, eliminating the need for post-processing corrections. The controlling of clocking may comprise adjusting timing of a clock applied in the at least path, such as by introducing a timing-delay adjustment to a clock when the clock is applied to a circuit after the circuit exhibiting nonlinear behavior. A timing-advancement may be applied to signals processed via the at least one path, particularly before the circuit exhibiting nonlinear behavior.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: January 22, 2019
    Assignee: MAXLINEAR, INC.
    Inventors: Prasun Kali Bhattacharyya, Abhishek Ghosh, Prasenjit Bhowmik
  • Patent number: 9843334
    Abstract: A phase locked loop frequency synthesizer is arranged to provide a target frequency output signal for a radio transmitter or receiver. The synthesizer comprises: a voltage controlled oscillator (2) operating at a first frequency; a first, fixed frequency divider to provide a second frequency, a pre-scaler to provide a variable frequency division of said second frequency to produce a third frequency, said pre-scaler comprising: a second frequency divider (14) connected to said first output (12) and providing a second output at a second frequency; and a phase detector (4) controlling said voltage controlled oscillator (2) on the basis of a comparison between a reference signal and a signal dependent on said third frequency; wherein the synthesizer is configured so that said first output (10, 12) provides said target frequency output signal.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: December 12, 2017
    Assignee: Nordic Semiconductor ASA
    Inventors: Stein Erik Weberg, Ola Bruset
  • Patent number: 9685934
    Abstract: A multi-bit flip-flop includes at least two storage stages. Each of the storage stages includes redundant latches to suppress state corruptions resulting from soft error upset at the storage stage. In addition, the multi-bit flip-flop includes a split clock path that routes different shared clock signals that control the timing of the latches. The shared split clock path reduces or eliminates the impact of soft errors on the clock signals, thereby further limiting the impact of such errors on data stored at the flip-flop. In particular, the split clock path can be distributed over disparate cells in a layout of multi-bit flip-flop, thereby reducing the likelihood that a transient charge will cause a soft error in all paths of the split clock path.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: June 20, 2017
    Assignee: NXP USA, INC.
    Inventors: Alexander Ivanovich Kornilov, Victor Mikhailovich Mikhailov, Mikhail Yurievich Semenov, David Russell Tipple
  • Patent number: 9667358
    Abstract: A method is provided for compensating for impairment of an electrical signal output from a device under test (DUT), the impairment resulting from an impairment network. The method includes measuring an impaired electrical signal received at an electronic analyzer via the impairment network; applying a coded pulse sequence to the impairment network; estimating an impairment transfer function corresponding to the impairment based on the applied pulse sequence; and correcting the measured electrical signal using the impairment transfer function to determine the electrical signal output from the DUT.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: May 30, 2017
    Assignee: Keysight Technologies, Inc.
    Inventor: Douglas Baney
  • Patent number: 9632526
    Abstract: A microcontroller has a numerical controlled oscillator receiving a primary clock signal and is configured to provide an internal system clock of the microcontroller. A method for operating a microcontroller performs the following steps: Selecting a primary clock signal from a plurality of clock signals; feeding the primary clock signal to a numerical controlled oscillator; configuring the numerical controlled oscillator to generate a numerical controlled clock signal; and providing the numerical controlled clock signal as an internal system clock for the microcontroller.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: April 25, 2017
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Sean Steedman, Fanie Duvenhage
  • Patent number: 9608523
    Abstract: According to an embodiment, a regulator includes: a voltage control circuit to supply a voltage; a clock signal output circuit to output a clock signal controlled by the voltage supplied from the voltage control circuit; and a current control circuit to supply the voltage supplied from the voltage control circuit to the clock signal output circuit, the current control circuit make to flow a dummy current which is determined based on the voltage, and stopping flowing the dummy current at a timing when the clock signal output circuit outputs the clock signal.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: March 28, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takayuki Iwai, Yasushi Shizuki
  • Patent number: 9602225
    Abstract: A method is provided for compensating for impairment of an electrical signal output from a device under test (DUT), the impairment resulting from an impairment network. The method includes measuring an impaired electrical signal received at an electronic analyzer via the impairment network; applying a stimulus signal to the impairment network; estimating an impairment transfer function corresponding to the impairment based on the applied stimulus signal; and correcting the measured electrical signal using the impairment transfer function to determine the electrical signal output from the DUT.
    Type: Grant
    Filed: October 27, 2011
    Date of Patent: March 21, 2017
    Assignee: Keysight Technologies, Inc.
    Inventor: Douglas Baney
  • Patent number: 9588575
    Abstract: Methods and apparatus relating to link power savings with state retention are described. In one embodiment, one or more components of two agents coupled via a serial link are turned off during idle periods while retaining link state in each agent. Other embodiments are also disclosed.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: March 7, 2017
    Assignee: Intel Corporation
    Inventors: Naveen Cherukuri, Jeffrey Wilcox, Venkatraman Iyer, Selim Bilgin, David S. Dunning, Robin Tim Frodsham, Theodore Z. Schoenborn, Sanjay Dabral
  • Patent number: 9485817
    Abstract: A control circuit of a light-emitting element comprises a rectifying unit which full-wave rectifies an alternating current power supply, a clock generator which generates and outputs a clock signal (CLK), a first comparator which compares a comparison voltage (CS) corresponding to a current flowing to the light-emitting element and a reference voltage (REF), and a switching element which is set to an ON state in synchronization with the clock signal (CLK) and which is set to an OFF state when the comparison voltage (CS) becomes greater than the reference voltage (REF) at the first comparator, to switch the current flowing to the light-emitting element. In this structure, a period of the clock signal (CLK) generated in the clock generator is varied, to reduce or inhibit noise.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: November 1, 2016
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Shuhei Kawai, Yoshio Fujimura
  • Patent number: 9473292
    Abstract: The disclosure is a device and a method for Non Return to Zero (NRZ) Clock Data Recovery (CDR) calibration, which includes a CDR unit and a weight calculator unit. The CDR unit receives a compensative signal of an equalization filter to generate an error signal, a sampling clock signal, a transition sampling signal and a data signal. The weight calculator unit receives the error signal, the transition sampling signal and the data signal, and then uses a run length technique to generate weight data. The weight data controls a voltage control oscillator (VCO) which calibrates the phase and the frequency of the sampling clock signal.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: October 18, 2016
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Liang-Wei Huang, Mei-Chao Yeh, Ting-Fa Yu, Ta-Chin Tseng
  • Patent number: 9335372
    Abstract: This disclosure relates to delay line test circuits and methods. In one aspect, an integrated circuit (IC) can include a plurality of delay lines, a selection circuit, a delay comparison circuit, and a control circuit. The plurality of delay lines can generate a plurality of delayed clock signals, and the selection circuit can include a plurality of inputs configured to receive at least the plurality of delayed clock signals. The selection circuit can generate a first output clock signal and a second output clock signal by selecting amongst signals received at the plurality of inputs based on a state of a selection control signal. The delay comparison circuit can compare a delay of the first output clock signal to a delay of the second output clock signal and can generate a delay comparison such as a pass/fail flag based on the result. The control circuit can generate the selection control signal.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: May 10, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Scott Van De Graaff, Tyler Gomm, Brandon Roth, Eric Becker
  • Patent number: 9331794
    Abstract: A method of measuring signal impairments is disclosed for use in an asynchronous Digital Signal Processing (DSP) based data and timing recovery circuit including an interpolator circuit. The method includes: calculating amplitude values for data and timing recovery; calculating an interpolation index for the interpolator circuit; and overriding the interpolation index. In another implementation, a method of measuring signal impairments in an asynchronous DSP-based data and timing recovery circuit including an interpolator circuit includes: calculating amplitude values for data and timing recovery; calculating a timing control signal; and overriding the timing control signal.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: May 3, 2016
    Assignee: MICROSEMI STORAGE SOLUTIONS (U.S.), INC.
    Inventor: Aryan Saed
  • Patent number: 9264211
    Abstract: In an exemplary system, a first sampling circuit is coupled to a clock module to receive values therefrom. A second sampling circuit is coupled to the clock module to receive the values therefrom. The first sampling circuit includes a first converter, a first phase interpolator, and a first sampler. The first converter is coupled to replace the values with first replacement values for input to the first phase interpolator. The second sampling circuit includes a second converter, a second phase interpolator, and a second sampler. The second converter is coupled to replace the values with second replacement values for input to the second phase interpolator.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: February 16, 2016
    Assignee: XILINX, INC.
    Inventor: Michael O. Jenkins
  • Patent number: 9214956
    Abstract: A semiconductor device includes an error detection unit suitable for receiving data and a cyclic redundancy check (CRC) code, and for outputting a detection signal by detecting a transmission error of the data, and a signal change unit suitable for generating error information based on the detection signal while changing a signal form of the error information based on a signal transmission environment of the data.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: December 15, 2015
    Assignee: SK Hynix Inc.
    Inventor: Sung-Hwa Ok
  • Patent number: 9112655
    Abstract: Integrated circuits with high-speed communications capabilities are provided. Such types of integrated circuits may include clock data recovery (CDR) circuitry. The CDR circuitry may receive incoming data and may generate multiple clock signals that are used to latch the incoming data. The CDR circuitry may include data latching circuitry for separately latching even and odd data bits in alternating clock cycles. In particular, the data latching circuitry may be controlled using first, second, third, and fourth clock signals having different respective phase settings. The first and second clock signals may be used to capture even and odd data bits, respectively. The third and fourth clock signals may be used to sample data near the transition between the even and odd data bits. The phase of the first and second clock signals may be dynamically adjusted. The phase setting that yields the optimal link performance may be selected for normal operation.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: August 18, 2015
    Assignee: Altera Corporation
    Inventors: Tim Tri Hoang, Weiqi Ding, Sangeeta Raman, Richard Hernandez
  • Patent number: 9065695
    Abstract: The present disclosure provides for a method and apparatus for efficient cross-correlation between a reference sequence and a received sequence in a wireless communication system. The reference sequence includes a concatenation of sign-adjusted sub-sequences, the sign adjustments determined by a first sign sequence of a set of sign sequences. For example, the reference sequence may be an alternating concatenation of sign-adjusted Golay complementary pair sub-sequences. The received sequence is shifted to provide a plurality of time shifted sequences that are then cross-correlated with the sub-sequences to form a set of partial cross-correlations. The partial cross-correlations are sign-adjusted using the first sign sequence and combined to produce the cross-correlation between the reference sequence and the received sequence. The cross-correlations so produced may be used for channel signature (e.g. PHY-type) identification and/or channel impulse response estimation.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: June 23, 2015
    Assignee: BlackBerry Limited
    Inventors: Huan Wu, Yan Xin, Shouxing Qu, Arnold Sheynman
  • Patent number: 9042494
    Abstract: A digital broadcasting receiving system is provided. A receiving module receives an M number of symbols each carrying an N number of subcarriers of a control signal. A converting module performs FFT on respective kth subcarriers of an ith symbol and an (i+1)th symbol to generate an (i, k)th converted value and an (i+1, k)th converted value. A demodulating module performs differential demodulation on the (i, k)th and (i+1, k)th converted values to generate an (i, k)th demodulation value. A combining module soft-combines the (i, 1)th demodulation value through the (i, N)th demodulation value to generate an ith prediction value corresponding to the ith symbol. A determining module identifies a synchronization segment in the control signal according to the 1st prediction value to the (M?1)th prediction value.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: May 26, 2015
    Assignee: MSTAR SEMICONDUCTOR, INC.
    Inventors: Ching-Fu Lan, Hsin-Chuan Kuo, Tung-Sheng Lin, Tai-Lai Tung
  • Patent number: 9036756
    Abstract: There is disclosed a receiver and associated methods in which a received signal can be sampled at the symbol rate rather than oversampled. This reduction in the sampling frequency compared with conventional receivers lowers power consumption. Quality metrics in receiving the data (e.g. packet error rate, etc) are not adversely affected by setting a programmable phase shift in the sampling frequency. The programmable shift can be selected through a calibration process using a known sequence of symbols, such as the short training field in 802.11 standards.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: May 19, 2015
    Assignee: CAMBRIDGE SILICON RADIO LIMITED
    Inventors: Simon Chang, Erik Lindskog, Hong Wan, Rainer Herberholz
  • Patent number: 9036761
    Abstract: Methods for frequency multiplying include receiving a signal having an input frequency at a frequency multiplier comprising a pair of transistors; and selecting a harmonic in the signal by connecting the transistors to a common impedance through a respective collector impedance, wherein an output frequency at the harmonic between the collector impedances and the common impedance is an even integer multiple of an input frequency.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: May 19, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wooram Lee, Alberto Valdes Garcia
  • Patent number: 9036763
    Abstract: An all-digital phase locked loop includes a time to digital converter that determines a fractional portion of a phase count. The time to digital converter has a quantization error that may be caused by phase noise, delay errors or skew errors. Several methods and devices may reduce the quantization error. A noise source may add dithering to the reference clock at an input of the time to digital converter. A digital processor may use two successive rising edges of the oscillator signal to count time delays of the time to digital convertor to the reference clock, and uses these counts to determine a ratio of the time delays and the time period of the oscillator signal for controlling a digitally controlled oscillator. A radio frequency counter circuit detects whether the oscillator signal leads or lags the reference clock because of skew and generates a phase signal to correct the skew.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: May 19, 2015
    Assignee: Marvell World Trade Ltd., St. Michael
    Inventors: Olivier Burg, Miguel Kirsch
  • Patent number: 9031181
    Abstract: A multi-port information communication system includes a reference clock signal generator configured to generate a reference clock signal. The system also includes a phase controller configured to generate a plurality of information communication clock signals based on the reference clock signal by staggering a phase of each of the information communication clock signals. The phase controller includes a delay-locked loop configured to generate a plurality of delay-locked loop signals based on the reference clock signal, and a plurality of time delay elements. Each time delay element is configured to produce a respective one of the information communication clock signals by adding a respective delay to a respective one of the delay-locked loop signals. The system includes information communication devices each including a respective transmitter. Each of the transmitters is configured to operate in response to a respective one of the information communication clock signals.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: May 12, 2015
    Assignee: Marvell International Ltd.
    Inventor: Pierte Roo
  • Patent number: 9031182
    Abstract: A method for clock recovery and data recovery from a data stream on a communication channel includes sampling a data stream on the communication channel at a sampling frequency determined by a clock signal and generating a sampled signal. The method further includes determining a phase shift between the communication data stream and the sampled signal and modifying the phase of the clock signal on the basis of the phase shift to obtain a desired phase difference between the sampled signal and the data stream.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: May 12, 2015
    Assignee: Power-One Italy S.p.A.
    Inventors: Massimo Valiani, Davide Tazzari, Filippo Vernia
  • Patent number: 9014322
    Abstract: In an example embodiment, a phase-locked loop circuit may include a first circuitry to receive a reference signal and a source signal. The first circuitry may generate a correction signal for demonstrating a difference in phase between the reference signal and the source signal. The phase-locked loop may include a second circuitry to receive the correction signal. The second circuitry may generate a digital signal for demonstrating a phase-to-digital conversion of the correction signal. The phase-locked loop may include a third circuitry to receive the digital signal. The third circuitry may generate a control signal for demonstrating a converted voltage of the digital signal. The phase-locked loop may include a fourth circuitry to receive the control signal. The fourth circuitry may generate the source signal in response to the control signal.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: April 21, 2015
    Assignee: Finisar Corporation
    Inventors: The'Linh Nguyen, Steven Gregory Troyer, Daniel K. Case
  • Publication number: 20150098542
    Abstract: A method for a first electronic device processing data based on information from a second electronic device may comprise: receiving a first signal from the second electronic device; extracting a first clock based on the first signal; adjusting an oscillator based on the first clock so as to generate a second clock; and selecting one from the first and second clocks. In an embodiment of the present invention, the first electronic device may be configured to be hot plugged into the second electronic device. The method may further comprise processing a data stream from the second electronic device based on said selecting said one from the first and second clocks. The method may further comprise transmitting a data stream to the second electronic device based on said selecting said one from the first and second clocks.
    Type: Application
    Filed: October 4, 2013
    Publication date: April 9, 2015
    Applicant: M31 Technology Corporation
    Inventors: Yu-Sheng Yi, Ting-Chun Huang, Yuan-Hsun Chang
  • Patent number: 9001869
    Abstract: A device for high-speed clock generation may include an injection locking-ring oscillator (ILRO) configured to receive one or more input clock signals and to generate multiple clock signals with different equally spaced phase angles. A phase-interpolator (PI) circuit may be configured to receive the multiple coarse spaced clock signals and to generate an output clock signal having a correct phase angle. The PI circuit may include a smoothing block that may be configured to smooth the multiple clock signals with different phase angles and to generate multiple smooth clock signals. A pulling block may be configured to pull edges of the multiple smooth clock signals closer to one another.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: April 7, 2015
    Assignee: Broadcom Corporation
    Inventors: Mahmoud Reza Ahmadi, Siavash Fallahi, Tamer Ali, Ali Nazemi, Hassan Maarefi, Burak Catli, Afshin Momtaz
  • Patent number: 8995599
    Abstract: A phase-locked loop circuit includes phase detection circuitry to generate a first control signal based on a phase comparison between first and second periodic signals. An oscillator circuit causes a frequency of a third periodic signal to vary based on the first control signal. A frequency divider circuit divides the frequency of the third periodic signal by a frequency division value to generate a frequency of the second periodic signal. A delta sigma modulator circuit controls the frequency division value based on second control signals. First storage circuits store the second control signals based on third control signals in response to a fourth periodic signal. A second storage circuit stores an output signal based on a fourth control signal. The fourth periodic signal is generated based on the output signal of the second storage circuit.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: March 31, 2015
    Assignee: Altera Corporation
    Inventors: Tien Duc Pham, Leon Zheng, Sergey Shumarayev, Zhi Y. Wong, Paul B. Ekas
  • Patent number: 8994565
    Abstract: An analog to digital conversion includes a multiplexor circuit for receiving analog input signals and, responsive to a select input, an analog to digital converter circuit to convert a selected analog signal into a digital signal, a conversion starting device to send a conversion start signal on the basis of a trigger event, the conversion starting device being responsive to a select input, a sequencer to control the analog to digital converter circuitry to execute one sequence conversion on the basis of one conversion sequence instruction, and a FIFO register block to receive conversion sequence instructions and being able to queue each new received conversion sequence instruction if an actual conversion sequence is in progress and to control the sequencer to execute a new sequence conversion instruction after the conversion sequence is executed.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: March 31, 2015
    Assignee: STMicroelectronics S.R.L.
    Inventors: Gianluigi Forte, Dino Costanzo, StelloMatteo Bille'
  • Publication number: 20150071396
    Abstract: For each of a plurality of delayed phases, one of the plurality of delayed phases being the same as a phase of a reference clock and the others of the plurality of delayed phases delayed with respect to the phase of the reference clock, test parallel data transmitted in synchronism with the reference clock is received in synchronism with a delayed clock having the delayed phase and an adjacent delayed clock having a delayed phase adjacent to the delayed phase of the delayed clock, respectively; and a phase range containing a delayed phase with which the test parallel data has been received correctly and for which the result of the comparison indicates a match is determined from among the plurality of delayed phases; and the phase of a receive clock to be used for reception of parallel data is determined from the determined phase range.
    Type: Application
    Filed: August 13, 2014
    Publication date: March 12, 2015
    Inventor: Ryoichi INAGAWA
  • Patent number: 8976051
    Abstract: Aspects of the present disclosure relate to floating point timers and counters that are used in a variety of contexts. In some implementations, a floating point counter can be used to generate a wave form made up of a series of pulses with different pulse lengths. An array of these floating point counters can be used to implement a pool of delays. In other implementations, an array of floating point counters can be used to analyze waveforms on a number of different communication channels. Analysis of such waveforms may be useful in automotive applications, such as in wheel speed measurement for example, as well as other applications.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: March 10, 2015
    Assignee: Infineon Technologies AG
    Inventors: Ljudmil Anastasov, Jens Barrenscheen
  • Patent number: 8976054
    Abstract: A time-to-digital conversion circuit for converting a time difference between two input signals to a 1-bit digital value, and adjusting the time difference between the two input signals to generate two output signals includes: a phase comparator configured to compare phases of the two input signals with each other to generate the digital value; a phase selector configured to output one of the two input signals which has a leading phase as a first signal, and the other of the two input signals which has a lagging phase as a second signal; and a delay unit configured to output the first signal with a delay, wherein the time-to-digital conversion circuit outputs the signal output from the delay unit and the second signal as the two output signals.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: March 10, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Shiro Dosho, Masao Takayama, Takuji Miki
  • Publication number: 20150063516
    Abstract: A communication circuit includes: a plurality of receiving units each configured to receive a serial signal over a transmission path from another device; a plurality of serial-to-parallel converters each configured to convert the received serial signal into a parallel signal; and a clock phase controller configured to send a clock phase control signal to any of the plurality of serial-to-parallel converters, wherein one of the serial-to-parallel converters that has received the clock phase control signal is configured to shift a phase of a parallel-signal clock signal that is to be used for a parallel signal obtained by conversion, so that a phase of a parallel signal to be obtained by conversion performed by the one of the serial-to-parallel converters is different from a phase of a parallel signal to be obtained by conversion performed by another one of the serial-to-parallel converters.
    Type: Application
    Filed: July 25, 2014
    Publication date: March 5, 2015
    Applicant: FUJITSU LIMITED
    Inventor: Ryuichi Nishiyama
  • Patent number: 8971469
    Abstract: A master device and slave devices are connected with each other through an SDA and an SCL, and at least one of a serial communication data signal communicated through the SDA and a serial communication clock signal communicated through the SCL is latched with use of a noise removal clock signal whose frequency is higher than that of the serial communication clock signal, and is taken in.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: March 3, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masahiro Imai, Nobuaki Takahashi
  • Patent number: 8964922
    Abstract: Various embodiments of the present invention relate to systems, devices and methods of oversampling electronic components where high frequency oversampling clock signals are generated internally. The generated oversampling clock is automatically synchronous with the input clock and the input serial data in a serial data link, and is adaptive to predetermined parameters, such as bit depth and oversampling rate.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: February 24, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Matthew Felder, Mark Summers
  • Patent number: 8964925
    Abstract: Methods and systems to generate control signals for timing recovery of a signal received over baseband communications systems are disclosed. The timing control circuit uses a multi-rate DSP structure for the implementation of the DSP functions in the control loop for use in an ASIC and requires a reduced DSP clock rate, which in turn reduces the need for pipelining and/or high-speed libraries. Thus lower latency, better tracking performance and lower power consumption are achieved. An example embodiment involves splitting the timing error signal, supplied at a given update rate, into a sum and a difference component, and processing each component in separate circuit chains at half the update rate. The resultant half-rate control signals from each separate circuit chain are joined to provide a control signal at the full update rate. Thus, implementations of the present disclosure perform like a full-rate structure, but require a halved DSP clock rate.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: February 24, 2015
    Assignee: PMC-Sierra US, Inc.
    Inventor: Aryan Saed