Abstract: The subject technology provides for synchronized playback of different media content streams. The disclosed techniques may include determining, while certain audio content is being outputted, whether a triggering event has occurred at a media device. Responsive to a determination that the triggering event has occurred, audio information including identification information and a current output status of the audio content may be obtained, and a visual content stream for visual content corresponding to the audio content may be obtained. At the media device, the visual content stream may be processed based on the audio information to determine a starting time point indicating a time point within the visual content from which to start outputting the visual content. The visual content may be outputted such that the output of the visual content begins at the starting time point and is synchronized in time with the audio content.

Abstract: [Problem] To monitor a frequency difference between an input clock and a synchronous clock synchronized with the input clock. [Solution] A clock frequency monitoring apparatus that monitors the frequency of an input clock 18a includes a phase comparator 12 that compares a phase of a synchronous clock 18e phase-synchronized with the input clock 18a or a first frequency-divided clock 18f obtained by frequency-dividing the synchronous clock 18e with the phase of the input clock 18a, a filter 13 that low-pass filters an output signal of the phase comparator 12, an oscillator 14 that generates the synchronous clock 18e having a frequency corresponding to a control value from the filter 13, and a determiner 19 that determines that the frequency of the input clock 18a is abnormal when the variation amplitude of the output signal of the filter 13 is equal to or more than a predetermined range.

Abstract: An AVR device in accordance with one or more embodiments connects audio and video source devices to audio and video rendering devices. A front panel user interface including a display is integrated in the housing of the AVR device. Input-output (IO) modules are coupled to a backplane board in the housing to be connected to the source devices and the rendering devices. The IO modules include at least one network interface. System-on-Modules (SoMs) are mounted on the backplane board. The SoMs are configured to decode and process audio and video data received from the audio and video source devices for rendering by the audio and video rendering devices and execute an operating system generating a GUI displayed on the display of the front panel user interface. A video subsystem module on the backplane board is configured to route the audio and video data between the plurality of SoMs and the IO modules.

Abstract: Systems and methods for offloading computational operations. In some implementations a method includes determining whether a data storage device coupled to a computing device is capable of performing a set of computational operations. The data storage device may be hot swappable. The method also includes offloading the set of computational operations to the data storage device in response to determining that the data storage device is capable of performing the set of computational operations. The method further includes performing the set of computational operations on the computing device in response to determining the data storage device is not capable of performing the set of computational operations.

Abstract: A timing recovery apparatus for signal reception in a data transmission system comprises an equalizer to equalize a received signal and a phase detector connected after the timing recovery equalizer that generates a clock tone from absolute values of the received signal after equalization.

Abstract: The present disclosure relates to a high speed, differential input, single phase clock circuit. The circuit may include a cross-coupled PMOS connected with a cross-coupled NMOS via a pass gate. The circuit may further include a single-phase clock in communication with the cross-coupled PMOS and the cross-coupled NMOS. The circuit may also include a master and a slave each having an output node that charges and discharges to VDD or ground respectively, wherein there is no direct feedback from an output of the circuit to an input the circuit and there is no precharged state in the circuit.

Abstract: Certain aspects of the present disclosure generally relate to circuitry and techniques for digital-to-analog conversion. One example device for digital-to-analog conversion generally includes: a digital-to-analog converter (DAC) having an input coupled to an input node of the device; a first return-to-zero (RZ) DAC having an input coupled to an input node of the device; and a combiner, wherein an output of the first DAC is coupled to a first input of the combiner, and wherein an output of the first RZ DAC is coupled to a second input of the combiner.

Abstract: In one embodiment, a system includes a CATV node, a first device, and at least one micro distribution system. The CATV node transmits CATV RF signals to the first device, which converts the RF signals to optical signals. Each micro distribution system includes a micro node receiving the optical signals from the first device and converting the optical signals to RF signals. Each micro distribution system further includes at least two strings of taps independently coupled to the micro node and receiving the RF signals from the micro node. Each string of taps is terminated at an end by a low pass filter (LPF). For each string of taps, the received RF signals are passed from the micro node along the taps and blocked by the LPF, while a powering signal is passed along the taps and through the LPF.

Abstract: A shift register generates a synthesized pulse having a different pulse width according to which one of a first phase pulse and a second phase pulse is inputted, generates an internal shifted synthesized pulse and a shifted synthesized pulse from the synthesized pulse, and generates a detection signal by detecting a pulse width of the internal shifted synthesized pulse. The shift register outputs the shifted synthesized pulse as one of a first shifted phase pulse and a second shifted phase pulse based on the detection signal.

Abstract: An electronic system, an integrated circuit die and an operation method thereof are provided. The integrated circuit die includes a plurality of interface circuit slices and a merging circuit. The transmission data stream sent from the transmitter die is split into a plurality of sub-data streams. Each of the interface circuit slices provides a physical layer to receive the corresponding one of the sub-data streams. The merging circuit is coupled to the interface circuit slices to receive the sub-data streams. The merging circuit merges the sub-data streams from the interface circuit slices back to the original data corresponding to the transmission data stream to be provided to an application layer. The merging circuit aligns the sub-data streams from the interface circuit slices in timing to mitigate different delays of the interface circuit slices.

Abstract: Systems and methods for operating a digital-to-analog converter (DAC) are described. In an example, a device can receive a digital input. The device can generate a clock signal having frequency in radio frequency (RF) range. The device can combine the digital input with the clock signal to generate a first voltage signal. The device can convert the first voltage signal into a second voltage signal having at least two phases. The device can convert the second voltage signal into a current signal. The device can distribute the current signal to at least one current mode DAC.

Abstract: A predefined signal has been used to facilitate the detection of the clock rate difference between the transmitter and the receiver. First the predefined signal is to be detected by each of the sensors and its time frame boundary information is acquired by a detector. The detector is composed of a matched filter bank, an event detector and a state sequence detector. The phase error is derived with reference to a fixed reference stored. With each of the sensors updating its local clock to the same fixed reference they can be brought to an arbitrary close clock error with one another. Thus, by applying the method disclosed here the transmitter and all the receivers can have an arbitrary small clock rate error with respect to one another. The method described is really fast in the sense that the delay needed for the detection and adjustment is minimal.

Abstract: The present disclosure relates to systems and methods to maintain clock synchronization of multiple computers, or computer systems, through the exchange of communication messages that include clock and/or timing information.

Abstract: Provided herein are gap detection and compensation schemes for timing alignment systems. In certain embodiments, a timing alignment system includes a detector that generates one or more loop control signals based on comparing a reference clock signal to a feedback clock signal, a loop filter having a loop voltage that is adjusted based on the one or more loop control signals, and a gap detection and compensation circuit that processes the one or more loop control signals to detect a gap in at least one of the reference clock signal or the feedback clock signal. In response to detecting the gap, the gap detection and compensation circuit modifies the one or more loop control signals to provide an adjustment to the loop voltage.

Abstract: An in-phase/quadrature (I/Q) clock generator is described. The I/Q clock generated includes a poly-phase filter configured to generate a four-phase quadrature clock signal in response to a two-phase quadrature clock signal generated in response to a single-ended input clock signal. The I/Q clock generated also includes a phase interpolator configured to generate an output four-phase quadrature clock signal from the four-phase quadrature clock signal. The I/Q clock generated further includes a poly-phase filter tune circuit coupled to an output of the phase interpolator. The poly-phase filter tune circuit is configured to generate a control voltage for the poly-phase filter to tune the four-phase quadrature clock signal from the poly-phase filter.

Abstract: Apparatuses and methods for phase interpolators are provided. An example apparatus comprises a phase interpolator and a controller coupled to the phase interpolator. The controller is configured to provide a digital timing code to the phase interpolator, and the phase interpolator is configured to apply a correction to the received digital timing code based, at least in part, on phase interpolator error correction data from a data structure containing phase interpolator error correction data.

Abstract: This disclosure relates to a receiver comprising a clock and data recovery loop and a phase offset loop. The clock and data recovery loop may be controlled by a sum of gradients for a plurality of data interleaves. The phase offset loop may be controlled by an accumulated differential gradient for each of the data interleaves.

Abstract: A circuit includes a voltage-controlled oscillator (VCO) and a frequency divider. The frequency divider input is coupled to the VCO output. The circuit further includes a phase-frequency detector (PFD). A control output of the PFD is coupled to the VCO. A first PFD input is coupled to a first frequency divider output, and a second PFD input is coupled to a second frequency divider output. The first frequency divider output is configured to provide a first frequency divider signal and the second frequency divider output is configured to provide a second frequency divider signal 90 degrees out of phase with respect to the first frequency divider signal. The PFD is configured to detect an occurrence of at least two edges of a signal on the data input while the second frequency divider signal is continuously logic high across the at least two edges.

Abstract: A method for a Mobile Industry Processor Interface (MIPI) master device for improving clock recovery at a MIPI slave device includes: transmitting a symbol sequence including a plurality of consecutive symbols which include at least one of a first symbol value and a second symbol value to the MIPI slave device prior to transmitting packet data to the MIPI slave device, wherein the first symbol value and the second symbol value bring relatively larger encoding jitters than other symbol values.

Abstract: Limiting frequency overshoot in a timing recovery loop involves using a proportional-integral (PI) control system to discipline a frequency of an output signal of a voltage controlled oscillator (VCO) in accordance with a time reference signal. A control signal output of the PI control system is monitored to detect conditions which will prospectively cause an excess deviation of the VCO frequency. In response to detecting such a condition, an output of an integral error term generator of the PI control system is locked or held constant. This will have the effect of preventing the excess frequency deviation of the VCO.

Abstract: Systems and methods related to phase-locked loops circuitry and lock-detect circuitry are provided. Some of the systems and methods allow sharing of lock-detect circuitries between multiple phase-locked loops or other suitable circuitry. Others allow multiple circuitries to select from multiple lock-detect circuitries that may use different lock-detect techniques.

Abstract: An optical instrument including at least a first and second wavelength swept vertical cavity laser (VCL) sources. The wavelength sweeping ranges spanned by the first and second VCL sources may differ with a region of spectral overlap. The first and second VCL sources may be operable under different modes of operation, wherein the modes of operation differ in at least one of: sweep repetition rate, sweep wavelength range, sweep center wavelength, and sweep trajectory. A VCL source may also exhibit sweep-to-sweep variation. Apparatus and methods are described for aligning sample signal data from the first VCL and sample signal data from the second VCL to generate output digital data. The output digital data is aligned with respect to at least one of: wavelength, wavenumber, and interferometric phase. The apparatus and methods can also be used to phase stabilize successive sweeps from the same VCL source or wavelength swept source.

Abstract: A circuit and method for a switching converter that modifies the clock frequency when the panic comparator is activated is proposed. This solution for a switching converter is achieved by increases in the switching frequency in response to an undershoot condition. In summary, a switching converter circuit, comprising at least one phase functional block configured to provide an output voltage, a panic comparator configured to evaluate voltage excursion conditions of the output voltage, and a clock generator with pulse insertion function wherein the pulse insertion function is configured to increase the switching frequency during a voltage excursion condition to minimize or mitigate voltage excursions. In addition, a switching converter circuit, comprising a clock generator with a pulse width extender configured to provide a signal to said pulse insertion function logic.

Abstract: Systems and methods are provided for clocking scheme to reduce nonlinear distortion. An example system may comprise at least two processing paths, each comprising at least one circuit exhibiting nonlinear behavior. Nonlinearity may be managed during processing of signals, such as by assessing effects of the nonlinear behavior during the processing of signals, and controlling clocking applied via at least one path based on the assessed effects, to reduce the effects of the nonlinear behavior during the processing of signals, eliminating the need for post-processing corrections. The controlling of clocking may comprise adjusting timing of a clock applied in the at least path, such as by introducing a timing-delay adjustment to a clock when the clock is applied to a circuit after the circuit exhibiting nonlinear behavior. A timing-advancement may be applied to signals processed via the at least one path, particularly before the circuit exhibiting nonlinear behavior.

Abstract: A phase locked loop frequency synthesizer is arranged to provide a target frequency output signal for a radio transmitter or receiver. The synthesizer comprises: a voltage controlled oscillator (2) operating at a first frequency; a first, fixed frequency divider to provide a second frequency, a pre-scaler to provide a variable frequency division of said second frequency to produce a third frequency, said pre-scaler comprising: a second frequency divider (14) connected to said first output (12) and providing a second output at a second frequency; and a phase detector (4) controlling said voltage controlled oscillator (2) on the basis of a comparison between a reference signal and a signal dependent on said third frequency; wherein the synthesizer is configured so that said first output (10, 12) provides said target frequency output signal.

Abstract: A multi-bit flip-flop includes at least two storage stages. Each of the storage stages includes redundant latches to suppress state corruptions resulting from soft error upset at the storage stage. In addition, the multi-bit flip-flop includes a split clock path that routes different shared clock signals that control the timing of the latches. The shared split clock path reduces or eliminates the impact of soft errors on the clock signals, thereby further limiting the impact of such errors on data stored at the flip-flop. In particular, the split clock path can be distributed over disparate cells in a layout of multi-bit flip-flop, thereby reducing the likelihood that a transient charge will cause a soft error in all paths of the split clock path.

Abstract: A method is provided for compensating for impairment of an electrical signal output from a device under test (DUT), the impairment resulting from an impairment network. The method includes measuring an impaired electrical signal received at an electronic analyzer via the impairment network; applying a coded pulse sequence to the impairment network; estimating an impairment transfer function corresponding to the impairment based on the applied pulse sequence; and correcting the measured electrical signal using the impairment transfer function to determine the electrical signal output from the DUT.

Abstract: A microcontroller has a numerical controlled oscillator receiving a primary clock signal and is configured to provide an internal system clock of the microcontroller. A method for operating a microcontroller performs the following steps: Selecting a primary clock signal from a plurality of clock signals; feeding the primary clock signal to a numerical controlled oscillator; configuring the numerical controlled oscillator to generate a numerical controlled clock signal; and providing the numerical controlled clock signal as an internal system clock for the microcontroller.

Abstract: According to an embodiment, a regulator includes: a voltage control circuit to supply a voltage; a clock signal output circuit to output a clock signal controlled by the voltage supplied from the voltage control circuit; and a current control circuit to supply the voltage supplied from the voltage control circuit to the clock signal output circuit, the current control circuit make to flow a dummy current which is determined based on the voltage, and stopping flowing the dummy current at a timing when the clock signal output circuit outputs the clock signal.

Abstract: A method is provided for compensating for impairment of an electrical signal output from a device under test (DUT), the impairment resulting from an impairment network. The method includes measuring an impaired electrical signal received at an electronic analyzer via the impairment network; applying a stimulus signal to the impairment network; estimating an impairment transfer function corresponding to the impairment based on the applied stimulus signal; and correcting the measured electrical signal using the impairment transfer function to determine the electrical signal output from the DUT.

Abstract: Methods and apparatus relating to link power savings with state retention are described. In one embodiment, one or more components of two agents coupled via a serial link are turned off during idle periods while retaining link state in each agent. Other embodiments are also disclosed.

Abstract: A control circuit of a light-emitting element comprises a rectifying unit which full-wave rectifies an alternating current power supply, a clock generator which generates and outputs a clock signal (CLK), a first comparator which compares a comparison voltage (CS) corresponding to a current flowing to the light-emitting element and a reference voltage (REF), and a switching element which is set to an ON state in synchronization with the clock signal (CLK) and which is set to an OFF state when the comparison voltage (CS) becomes greater than the reference voltage (REF) at the first comparator, to switch the current flowing to the light-emitting element. In this structure, a period of the clock signal (CLK) generated in the clock generator is varied, to reduce or inhibit noise.

Abstract: The disclosure is a device and a method for Non Return to Zero (NRZ) Clock Data Recovery (CDR) calibration, which includes a CDR unit and a weight calculator unit. The CDR unit receives a compensative signal of an equalization filter to generate an error signal, a sampling clock signal, a transition sampling signal and a data signal. The weight calculator unit receives the error signal, the transition sampling signal and the data signal, and then uses a run length technique to generate weight data. The weight data controls a voltage control oscillator (VCO) which calibrates the phase and the frequency of the sampling clock signal.

Abstract: This disclosure relates to delay line test circuits and methods. In one aspect, an integrated circuit (IC) can include a plurality of delay lines, a selection circuit, a delay comparison circuit, and a control circuit. The plurality of delay lines can generate a plurality of delayed clock signals, and the selection circuit can include a plurality of inputs configured to receive at least the plurality of delayed clock signals. The selection circuit can generate a first output clock signal and a second output clock signal by selecting amongst signals received at the plurality of inputs based on a state of a selection control signal. The delay comparison circuit can compare a delay of the first output clock signal to a delay of the second output clock signal and can generate a delay comparison such as a pass/fail flag based on the result. The control circuit can generate the selection control signal.

Abstract: A method of measuring signal impairments is disclosed for use in an asynchronous Digital Signal Processing (DSP) based data and timing recovery circuit including an interpolator circuit. The method includes: calculating amplitude values for data and timing recovery; calculating an interpolation index for the interpolator circuit; and overriding the interpolation index. In another implementation, a method of measuring signal impairments in an asynchronous DSP-based data and timing recovery circuit including an interpolator circuit includes: calculating amplitude values for data and timing recovery; calculating a timing control signal; and overriding the timing control signal.

Abstract: In an exemplary system, a first sampling circuit is coupled to a clock module to receive values therefrom. A second sampling circuit is coupled to the clock module to receive the values therefrom. The first sampling circuit includes a first converter, a first phase interpolator, and a first sampler. The first converter is coupled to replace the values with first replacement values for input to the first phase interpolator. The second sampling circuit includes a second converter, a second phase interpolator, and a second sampler. The second converter is coupled to replace the values with second replacement values for input to the second phase interpolator.

Abstract: A semiconductor device includes an error detection unit suitable for receiving data and a cyclic redundancy check (CRC) code, and for outputting a detection signal by detecting a transmission error of the data, and a signal change unit suitable for generating error information based on the detection signal while changing a signal form of the error information based on a signal transmission environment of the data.

Abstract: Integrated circuits with high-speed communications capabilities are provided. Such types of integrated circuits may include clock data recovery (CDR) circuitry. The CDR circuitry may receive incoming data and may generate multiple clock signals that are used to latch the incoming data. The CDR circuitry may include data latching circuitry for separately latching even and odd data bits in alternating clock cycles. In particular, the data latching circuitry may be controlled using first, second, third, and fourth clock signals having different respective phase settings. The first and second clock signals may be used to capture even and odd data bits, respectively. The third and fourth clock signals may be used to sample data near the transition between the even and odd data bits. The phase of the first and second clock signals may be dynamically adjusted. The phase setting that yields the optimal link performance may be selected for normal operation.

Abstract: The present disclosure provides for a method and apparatus for efficient cross-correlation between a reference sequence and a received sequence in a wireless communication system. The reference sequence includes a concatenation of sign-adjusted sub-sequences, the sign adjustments determined by a first sign sequence of a set of sign sequences. For example, the reference sequence may be an alternating concatenation of sign-adjusted Golay complementary pair sub-sequences. The received sequence is shifted to provide a plurality of time shifted sequences that are then cross-correlated with the sub-sequences to form a set of partial cross-correlations. The partial cross-correlations are sign-adjusted using the first sign sequence and combined to produce the cross-correlation between the reference sequence and the received sequence. The cross-correlations so produced may be used for channel signature (e.g. PHY-type) identification and/or channel impulse response estimation.

Abstract: A digital broadcasting receiving system is provided. A receiving module receives an M number of symbols each carrying an N number of subcarriers of a control signal. A converting module performs FFT on respective kth subcarriers of an ith symbol and an (i+1)th symbol to generate an (i, k)th converted value and an (i+1, k)th converted value. A demodulating module performs differential demodulation on the (i, k)th and (i+1, k)th converted values to generate an (i, k)th demodulation value. A combining module soft-combines the (i, 1)th demodulation value through the (i, N)th demodulation value to generate an ith prediction value corresponding to the ith symbol. A determining module identifies a synchronization segment in the control signal according to the 1st prediction value to the (M?1)th prediction value.

Abstract: An all-digital phase locked loop includes a time to digital converter that determines a fractional portion of a phase count. The time to digital converter has a quantization error that may be caused by phase noise, delay errors or skew errors. Several methods and devices may reduce the quantization error. A noise source may add dithering to the reference clock at an input of the time to digital converter. A digital processor may use two successive rising edges of the oscillator signal to count time delays of the time to digital convertor to the reference clock, and uses these counts to determine a ratio of the time delays and the time period of the oscillator signal for controlling a digitally controlled oscillator. A radio frequency counter circuit detects whether the oscillator signal leads or lags the reference clock because of skew and generates a phase signal to correct the skew.

Abstract: There is disclosed a receiver and associated methods in which a received signal can be sampled at the symbol rate rather than oversampled. This reduction in the sampling frequency compared with conventional receivers lowers power consumption. Quality metrics in receiving the data (e.g. packet error rate, etc) are not adversely affected by setting a programmable phase shift in the sampling frequency. The programmable shift can be selected through a calibration process using a known sequence of symbols, such as the short training field in 802.11 standards.

Abstract: Methods for frequency multiplying include receiving a signal having an input frequency at a frequency multiplier comprising a pair of transistors; and selecting a harmonic in the signal by connecting the transistors to a common impedance through a respective collector impedance, wherein an output frequency at the harmonic between the collector impedances and the common impedance is an even integer multiple of an input frequency.

Abstract: A multi-port information communication system includes a reference clock signal generator configured to generate a reference clock signal. The system also includes a phase controller configured to generate a plurality of information communication clock signals based on the reference clock signal by staggering a phase of each of the information communication clock signals. The phase controller includes a delay-locked loop configured to generate a plurality of delay-locked loop signals based on the reference clock signal, and a plurality of time delay elements. Each time delay element is configured to produce a respective one of the information communication clock signals by adding a respective delay to a respective one of the delay-locked loop signals. The system includes information communication devices each including a respective transmitter. Each of the transmitters is configured to operate in response to a respective one of the information communication clock signals.

Abstract: A method for clock recovery and data recovery from a data stream on a communication channel includes sampling a data stream on the communication channel at a sampling frequency determined by a clock signal and generating a sampled signal. The method further includes determining a phase shift between the communication data stream and the sampled signal and modifying the phase of the clock signal on the basis of the phase shift to obtain a desired phase difference between the sampled signal and the data stream.

Abstract: In an example embodiment, a phase-locked loop circuit may include a first circuitry to receive a reference signal and a source signal. The first circuitry may generate a correction signal for demonstrating a difference in phase between the reference signal and the source signal. The phase-locked loop may include a second circuitry to receive the correction signal. The second circuitry may generate a digital signal for demonstrating a phase-to-digital conversion of the correction signal. The phase-locked loop may include a third circuitry to receive the digital signal. The third circuitry may generate a control signal for demonstrating a converted voltage of the digital signal. The phase-locked loop may include a fourth circuitry to receive the control signal. The fourth circuitry may generate the source signal in response to the control signal.

Abstract: A method for a first electronic device processing data based on information from a second electronic device may comprise: receiving a first signal from the second electronic device; extracting a first clock based on the first signal; adjusting an oscillator based on the first clock so as to generate a second clock; and selecting one from the first and second clocks. In an embodiment of the present invention, the first electronic device may be configured to be hot plugged into the second electronic device. The method may further comprise processing a data stream from the second electronic device based on said selecting said one from the first and second clocks. The method may further comprise transmitting a data stream to the second electronic device based on said selecting said one from the first and second clocks.

Abstract: A device for high-speed clock generation may include an injection locking-ring oscillator (ILRO) configured to receive one or more input clock signals and to generate multiple clock signals with different equally spaced phase angles. A phase-interpolator (PI) circuit may be configured to receive the multiple coarse spaced clock signals and to generate an output clock signal having a correct phase angle. The PI circuit may include a smoothing block that may be configured to smooth the multiple clock signals with different phase angles and to generate multiple smooth clock signals. A pulling block may be configured to pull edges of the multiple smooth clock signals closer to one another.

Abstract: A phase-locked loop circuit includes phase detection circuitry to generate a first control signal based on a phase comparison between first and second periodic signals. An oscillator circuit causes a frequency of a third periodic signal to vary based on the first control signal. A frequency divider circuit divides the frequency of the third periodic signal by a frequency division value to generate a frequency of the second periodic signal. A delta sigma modulator circuit controls the frequency division value based on second control signals. First storage circuits store the second control signals based on third control signals in response to a fourth periodic signal. A second storage circuit stores an output signal based on a fourth control signal. The fourth periodic signal is generated based on the output signal of the second storage circuit.

Abstract: An analog to digital conversion includes a multiplexor circuit for receiving analog input signals and, responsive to a select input, an analog to digital converter circuit to convert a selected analog signal into a digital signal, a conversion starting device to send a conversion start signal on the basis of a trigger event, the conversion starting device being responsive to a select input, a sequencer to control the analog to digital converter circuitry to execute one sequence conversion on the basis of one conversion sequence instruction, and a FIFO register block to receive conversion sequence instructions and being able to queue each new received conversion sequence instruction if an actual conversion sequence is in progress and to control the sequencer to execute a new sequence conversion instruction after the conversion sequence is executed.