Abstract: A hybrid circuit includes a resistor inserted serially between a transmission line and an output driver for transmitting a signal; and a reception signal extraction unit for extracting only a reception signal from a signal existing in a transmission path by using a signal obtained from both ends of the resistor. The reception signal extraction unit can be constituted by, for example, two transconductance amplifiers for converting the input voltage into a current and a load resistor in which flows the current of a result of adding the output currents of the two amplifiers.

Abstract: A system and a method of suppressing outstanding degradation of decoded audio quality due to a transmission error of audio coded data are provided without feedback information from a receiver, thereby reducing the increase of the number of necessary transmission bands and the arithmetic complexity on the receiving side. A code conversion and transmission apparatus 100 for inputting audio coded data includes first to N-th code conversion and transmission units 102 and 104 to 106 for converting audio data to N pieces of coded data, and transmitting the data at predetermined or adaptively variable time intervals to M transmission lines 130. The second to N-th audio code conversion and transmission units 104 to 106 codes a frame at a compression rate equal to or higher than the rate of input coded data.

Abstract: A method for verifying a spread spectrum function and a spread spectrum verification circuit are provided. Comparing an output frequency of the spread spectrum function with a reference frequency for the spread spectrum function tests an upper bound of the spread spectrum function. If the output frequency increases above the reference frequency, the upper bound of the spread spectrum function is verified. Comparing the reference frequency for the spread spectrum function with the output frequency of the spread spectrum function tests a lower bound of the spread spectrum function. If the output frequency decreases below the reference frequency, the lower bound of the spread spectrum function is verified.

Abstract: A circuit and method for cochlear implant telemetry where digital data is encoded into an RF signal. The RF signal is applied via a rectifier diode to a first switch matrix S1 and a second switch matrix S2, with S1 being coupled to a first sampling capacitor C1 and S2 being coupled to a second sampling capacitor C2. A local oscillator signal with period T is applied that controls S1 and S2, cyclically coupling C1 and C2 to the RF signal, a first input to a comparator, and ground. The comparator compares the first input to a DC reference voltage. The output of the comparator is then sampled via a flip flop clocked by the local oscillator, with the flip flop outputting a data bit stream representative of the envelope of the RF signal having encoded information.

Abstract: There is provided a device and method for transmitting packet data in a mobile communication system. A sub-code generator generates a plurality of sub-codes with the same or different code rates for the input of a PLP (Physical Layer Packet) information bit stream. A controller determines a minimum data rate by which the number of the modulation symbols of a sub-code generated by a predetermined modulation method is equal to or greater than the number of transmittable modulation symbols for each time period. A symbol pruner prunes part of the modulation symbols of the sub-code to make the number of the modulation symbols of the sub-code equal to the number of transmittable modulation symbols for the time period, if the number of the modulation symbols of the sub-code is greater than the number of transmittable modulation symbols for the time period.

Abstract: A digital direct access arrangement (DAA) circuitry may be used to terminate the telephone connections at the user's end that provides a communication path for signals to and from the phone lines. Briefly described, the DAA provides a programmable means for the DC termination for a variety of international phone standards. The invention may also be utilized with means for transmitting and receiving a signal across a capacitive isolation barrier. More particularly, a DC holding circuit is provided in which a programmable DC current limiting mode is available. In the current limiting mode, power may be dissipated in devices external to a DAA integrated circuit. Moreover, much of the power may be dissipated in external passive devices, such as resistors.

Abstract: Systems and methods for transmitting information at very high data rates through narrowband communication channels are provided. The systems and methods involve modulating a message signal with a novel return-to-zero, abrupt phase modulation technique and filtering the modulated signal with a sophisticated high-precision digital filter. The digital filter is designed based on fractal modeling of the frequency spectrum of the modulated signal. The systems and methods of the present invention enable data rates exceeding 5 Mbps to be delivered through frequency channels as narrow as 50 KHz under a variety of channel conditions.

Abstract: A peak voltage detector is used to detect the absolute value of the peak differential amplitude of a differential input signal. The peak voltage detector includes a differential amplifier receiving the differential input signal and generating a corresponding pair of differential output signals. The voltage detector also includes a capacitor on which an output signal is generated. A first differential comparator generates a first signal whenever the differential voltage from the differential amplifier is greater than the voltage of the output signal. A second differential comparator generates a second signal whenever the negative of the differential voltage from the differential amplifier is greater than the voltage of the output signal. A current source applies current to the capacitor responsive to receiving either the first or second signal. The amplitude of the feedback voltage is thus equal to the absolute value of the peak differential amplitude of the input signal.

Abstract: A clock and data recovery (CDR) circuit comprises a phase detector (PD) and a quadrature phase (QP) detector. A frequency detector (FD) is coupled to the PD and QP detector. The FD detects frequency difference between the output signals of the PD and QP detector and provides an FD output signal. A summer is coupled to the PD and FD for summing the PD and FD output signals, and for providing a summer output signal. The CDR further comprises a voltage-controlled oscillator (VCO) for receiving a direct current signal and providing a recovered clock signal. A polyphase filter is coupled to each of the VCO, PD, and QP detector. A re-timer is coupled to the polyphase filter and provides a re-timed data signal, wherein the CDR circuit is on-chip and the polyphase filter converts clock signals into phase reference signals.

Abstract: A method for verifying a spread spectrum function and a spread spectrum verification circuit are provided. Comparing an output frequency of the spread spectrum function with a reference frequency for the spread spectrum function tests an upper bound of the spread spectrum function. If the output frequency increases above the reference frequency, the upper bound of the spread spectrum function is verified. Comparing the reference frequency for the spread spectrum function with the output frequency of the spread spectrum function tests a lower bound of the spread spectrum function. If the output frequency decreases below the reference frequency, the lower bound of the spread spectrum function is verified.

Abstract: A system and method are provided for stopping a quantized signal from a noise-shaper with a significantly reduced inband transient, compared to a traditional random stop of a noise-shaped signal. The noise-shaped signal is stopped at a favorable time controlled by a detector that monitors the noise-shaped signal. The detector indicates the occurrence of a good time to stop the noise-shaper such that the transient due to the stop is minimized in a fashion that substantially reduces the inband disturbance.

Abstract: The 90-degree phase shifter of the invention has: a T flip-flop including transistors Q3 to Q6 and Q9 to Q12 that together constitute a dual differential circuit, input transistors Q1 and Q2 that receive at their bases an input signal, and input transistors Q7 and Q8 that receive at their bases a signal complementary to the input signal; variable current sources 14 to 17 connected respectively to the nodes between the individual input transistors and the dual differential circuit; and a 90-degree phase comparator 10 that compares the phase differences between the signals outputted from the T flip-flop to output signals commensurate with the deviations of those phase differences from 90 degrees. The variable current sources 14 to 17 are controlled by signals based on the signals outputted from the 90-degree phase comparator 10. This configuration more surely yields output signals with a phase difference of exactly 90 degrees.

Abstract: An information apparatus switches a display at a predetermined area which includes at least a part of a portion where an electromagnetic-wave emitting unit used for data communications with a data storage device is disposed, according to data communication processing with the data storage device, and emits sound generated according to the processing at corresponding timing.

Abstract: Briefly, some embodiments of the invention may provide devices, systems and methods for wireless combined-signal communication. For example, a method in accordance with an embodiment of the invention may include transmitting a combined signal over a combined channel by mapping a first block of said combined signal to be carried by a first sub-channel of said combined channel and mapping a second block, substantially identical to said first block, to be carried by a second sub-channel of said combined channel.

Abstract: A power control method for transceiver units conveying data over discrete tones. The method includes the steps of: determining a transmit power over a physical channel for each individual tone, such that this transmit power maximizes a weighted function of data rates achievable with this tone over the physical channel and over modeled neighboring channels, with the constraint that this transmit power conforms to a transmit power mask, summing up the data rates over the whole set of tones, adjusting the weights such that the total data rates over the modeled neighboring channels reach some target data rates, and such that the total data rate over the physical channel is maximized, with the constraint that each weight is identical over the whole set of tones.

Abstract: The present invention provides asymmetric digital subscriber line (ADSL) modems including a discrete multitone (DMT) modem module. The DMT modem module includes a digital signal processor (DSP) configured to process control signals for initializing the ADSL modem during installation associated with a host device and transmit the processed control signals to a host controller of the host device.

Abstract: An apparatus and method for soft-combining demodulated symbols in a mobile communication system. In the mobile communication system, a transmitting apparatus modulates symbols in different modulation schemes and a receiving apparatus demodulates the modulation symbols in correspondence with the modulation schemes. The soft symbol combining apparatus includes an RWF calculator, an RWF controller, and a soft symbol controller. The RWF calculator calculates an energy of a modulation symbol from each of the modulation schemes and determines relative ratios of the energies to be RWFs for the modulation schemes. The RWF controller multiplies soft metrics of the demodulated soft symbols by the RWFs. Finally, the soft symbol controller combines the multiplied soft metrics.

Abstract: A homodyne receiver is provided for receiving GSM and UMTS transmissions. The receiver may also be used for other transmission schemes. The receiver includes an electronically reconfigurable low pass filter and an off set generator for providing DC offset correction for offsets which may be generated as a result of coupling between a local radio frequency oscillator and the receiver front end.

Abstract: A method and system for the synchronization of the transmission of digitally converted analog modem signals between two or more modems using either RF over-the-air or A/C power line communication channels. This invention provides for modem speed optimization by minimizing or eliminating clock variance between the modems in a digital communication system. A fixed delay is created and maintained during modem operation. This invention is also adapted to function in a full-duplex communication system maintaining a fixed delay in both directions.

Abstract: A data transmitting/receiving apparatus and method for improving the reliability of data bits in a CDMA mobile communication system. High-priority bits are mapped to a high-reliability bit position and low-priority bits, to a low-reliability bit position in symbols. Thus system performance is improved at a transmission.

Abstract: An apparatus and method for synchronizing sampling frequencies of a receiver and a transmitter of a multi-carrier communication system is provided. The receiver includes an estimator for estimating a frequency offset by employing an additional angle rotation of a received signal in frequency domain. The apparatus includes a compensation loop filter for generating a first output in response to a frequency offset compensation, an adder for adding the estimated frequency offset and the first output to generate a second output, and a loop filter for generating frequency offset compensation according to the second output. The method repeatedly applies the apparatus to generate frequency offset compensation, and then feeds it back to an oscillator to compensate the sampling frequency of the receiver. The apparatus and method can also be applied to a communication system with a carrier frequency offset.

Abstract: An electronic apparatus has a communication device, memory which stores identification information for identifying an external device having been previously connected to the communication device, an operation switch, a connection establishing unit for establishing connection with the external device designated by identification information stored in said memory in response to the operation of said operation switch, and a receiver for receiving data transmitted from the external device with which the connection is established by the connection establishing unit via the communication device.

Abstract: Digital communication signals that encode information in the phase may be susceptible to phase error from many sources. The invention corrects for carrier and sampling phase errors, as well as additive phase noise. A digital phase locked loop simultaneously tracks the carrier phase error and the sampling phase error, and corrects the signal in the frequency domain. The invention may use the sampling phase error to advance or delay the sampling window used to convert the signal from the time domain to the frequency domain.

Abstract: A two-wire communication protocol between a controller device and a controlled device, wherein both devices are coupled by a clock line and a data line. The controller device sends control signals comprising N bits, N being greater than or equal to two, to the controlled device via the data line. Each bit of said control signals is latched onto the controlled device on consecutive edges of a clock signal sent by the controller device to the controlled device on the clock line.

Abstract: A device communicates with a host and includes a transmitter, a receiver and a clock generator that generates a signal having a local clock frequency. A clock recovery circuit communicates with the receiver and recovers a host clock frequency from data received from the host by the receiver. A frequency offset circuit communicates with the clock recovery circuit and the clock generator and generates a frequency offset based on the clock frequency and the recovered host clock frequency. A frequency compensator compensates a frequency of the transmitter using the frequency offset. The host and the device may communicate using a serial ATA standard. Frequency compensation can be performed during spread spectrum operation.

Abstract: Processing circuitry includes an analog filter and filter control circuitry and processes an analog signal having a varying data rate. The analog filter filters the analog signal based on a transfer characteristic to transfer a filtered signal. The filter control circuit processes a data clock signal corresponding to the varying data rate and a reference clock signal to generate a filter control signal to adjust the transfer characteristic in proportion to the varying data rate. The analog filter adjusts the transfer characteristic in proportion to the varying data rate in response to the filter control signal. The processing circuitry may be implemented in a tape, magnetic, or optical drive.

Abstract: In one embodiment, a method for constructing an application includes identifying one or more channel types for a design of the application. Each of the identified channel types specifies resource needs of a hardware function pertaining to the design. The method further includes creating channel instances of the identified channel types for an application project having sufficient hardware resources for hardware functions pertaining to the design, where each of the created channel instances is customized for the design.

Abstract: Method of transmission of data between at least two communication devices which are connected together over a data network. The communication devices are respectively connected to a coding device and the sent data are source-and channel-coded by a coding method respectively furnished within the coding devices. The data are converted within a converting device connected to the data network.

Abstract: A device and method are disclosed, whereby the normally complicated and difficult frequency determination is achieved by simply arranged and executed measures, namely by means of larger, smaller and/or equal comparisons and a counting of certain events. The invention further relates to arrangements whereby the noise signal level, or the influence thereof on the verification to be carried out is reduced.

Abstract: A baseband receiver having quadrature analog outputs and a plurality of analog control and status signals and a transmit modulator having analog quadrature inputs and a plurality of analog control and status signals are coupled to a transmit processor having a digital output and a plurality of digital control and status signals and to a receive processor having a digital input and a plurality of digital control and status signals by multiplexing analog to digital converters and digital to analog converters such that during a receive time the converters are used for a receive purpose and during a transmit time, the converters are used for a transmit purpose.

Abstract: A two-dimensional optimization between adaptive modulation and coding (AMC) and multi-code transmission targets the best bit rate at which a highest useable modulation and coding scheme (MCS) achieves a maximum allowed number of channelization codes or less. The optimized MCS and number of channelization codes at a best bit rate is communicated from a transmitter to a receiver, possibly also with power information for instance using a transport format combination indicator (TFCI). A user equipment may play the role of carrying out the optimization and signaling the result to the Node B or may instead receive the result as carried out by the Node B or RNC in response to a radio link quality measurement sent from the UE to the Node B.

Abstract: A dual-mode ultra wideband (UWB) communication transceiver is presented to implement two disparate systems for indoor and outdoor UWB operations. During an operation mode, the dual-mode UWB communication transceiver sends and receives indoor or outdoor UWB signals using indoor or outdoor programmable filters with a multichannel-based multicarrier modulator and downconverter. The dual-mode UWB communication transceiver along with novel transmitter and receiver architectures is able to selectively transmit and receive a very-high data rate with scalability and programmability in an indoor and/or outdoor environment.

Abstract: A skip-free retiming system and method for transmission of digital information in a plesiochronous data communication system is described. The system is capable of supporting an unlimited number of retimers in serial data path between a first and a last node. The retimers are configured to retime, amplify and retransmit a received data stream without altering the received data rate. Thus, the data rate from the first node is received at the same frequency at the last node, regardless of the number of retimers. In general, the retimer performs rate compensation on a retimer local clock, rather than on the data stream, so the attributes of the clean retimer clock can be applied to the data stream without changing the data rate.

Abstract: In digital communications, a multi-mode block-coded modulation/demodulation method carries out adaptive one-way transmission of a multi-mode digital signal by using, between at least two different modes, different settings for level number, level code, set-partitioning method and modulation method that are component elements of a multi-level block-coded modulation system.

Abstract: Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchronizing the data input and/or output communication, and a mode input for controlling the data input and/or output communication. A clock/mode signal connects to the clock input of one circuit and to the mode input of the other circuit. A mode/clock signal connects to the mode input of the one circuit and to the clock input of the other circuit. The role of the mode and clock signals on the mode/clock and clock/mode signals, or their reversal, selects one or the other of the data communication circuits.

Abstract: A data transmission device using electromagnetic wave radiation in a contactless transceiver system toward a contactless object, the data bits transmitted corresponding to the half cycle of an initial time interval during which electromagnetic waves are emitted at a predetermined carrier frequency and to a second splitting time interval during which there is a split in transmission of the electromagnetic waves at the predetermined carrier frequency. During said second splitting time interval, generation means (40, 42, 44, 46, 48) generate electromagnetic waves having a frequency which is double the predetermined carrier frequency resulting in an attenuation of the radiated field by the antenna greater than a predetermined value such as 30 dB.

Abstract: This invention provides a signal transfer technique capable of realizing stable high rate data transfer and the reduction of a layout area. A system (semiconductor device) for realizing a high rate data transfer circuit method includes: a transmission circuit which consists of a normal signal transmitter and a receiving amplifier starting signal transmitter; a receiving circuit which consists of a receiving amplifier and a receiving amplifier starting signal receiver; a normal signal line and a receiving amplifier starting signal line connected between the transmission circuit and the receiving circuit; and the like. The normal signal transmitter includes a circuit which changes an output level for a specific period in accordance with the level of a normal signal and a circuit which controls the normal signal line to allow the normal signal line to function between VDD and VSS.

Abstract: A valve controller is disclosed. The valve controller includes an interface circuit having an input for connection to a controller, a processor in data communication with the interface circuit which is operable to generate a control signal for controlling a valve position, and a control device operable to control the valve position in response to the control signal from the processor. The interface circuit includes a power extraction circuit connected to the controller and is further operable to generate a DC operating voltage for use in powering the interface circuit and the processor. The interface circuit includes a current sensor connected to the controller and is further operable to generate a measure of a current from the controller, the measure being used in controlling a device associated with the interface circuit. The interface circuit also includes a digital communications circuit connected to the controller and is further operable to transmit and receive communication signals.

Abstract: The invention is a system for selecting a peripheral, the peripheral receiving a first clock frequency. The invention comprises the following. A processing circuit receives a second clock frequency, where the first and second clock frequencies are different. The processing circuit is configured to transmit a select signal. A bridge circuit is coupled to the processing circuit and the peripheral, and is configured to receive the select signal and transmit a peripheral select signal to the peripheral. The bridge circuit is further configured to receive the second clock frequency but not the first clock frequency. A counter is coupled to the bridge circuit and is configured to process a count, the count being a predetermined number and based on the value of the first frequency.

Abstract: Embodiments of the present invention relate to a method for recovering the clock and data signals in a transmitted data signal In a computer network. The method comprises accessing a transmitted a data signal at a receiver in the network, locking the receiver on a data signal transmission frequency, then locking the receiver on a data signal transition phase in the transmitted data signal and adjusting the signal transition phase locking by reference to the transition density of the transmitted data signal. Embodiments adjust the transition phase locking by adjusting the tail current of a Gm cell in a phase locked loop in the receiver, based on the received data signal transition density.

Abstract: A system and method for the superimposition of differential signals on binary signals in a memory system. The technique can be performed on busses, and in many kinds of storage media. It can be accomplished in many ways depending on the noise that is to be tolerated, and depending on the sophistication of the encoding means.

Abstract: There is provided a method for managing the downloading and display of a video program using a mobile device in an networking environment that includes a first radio access network and a second radio access network that has a faster transfer rate than the first network. A layer of video program that has been encoded into multiple layers is downloaded via the first or second network. The downloaded video program is displayed at a playback rate that corresponds to a display quality. Excess portion of the downloaded video program that result when a rate at which the video program is displayed are buffered. The number of layers being downloaded and the playback rate at which the video program is displayed are increased to increase the display quality, when the buffered excess portions exceeds a threshold level.

Abstract: A digital delay lock loop (DLL) circuit for receiving parallel data and clock signals, deserializing the high speed parallel data to low speed data, and for improving setup and hold times. A DLL circuit for an N-bit datapath, includes a clock DLL configured to provide a clock signal pulse within an eye opening of each of N data signals. The DLL circuit further includes N data DLLs, each being configured to adjust a delay of a data signal to substantially center the eye opening of the data signal on the clock signal pulse.

Abstract: A method and system for the synchronization of the transmission of digitally converted analog modem signals between two or more modems using either RF over-the-air or A/C power line communication channels. This invention provides for modem speed optimization my minimizing or eliminating clock variance between the modems in a digital communication system. A fixed delay is created and maintained during modem operation. This invention is also adapted to function in a full-duplex communication system maintaining a fixed delay in both directions.

Abstract: The present invention provides an apparatus, system and method of peak-to-average reduction of an oversampled signal for a digital communication system. Peak detection 504 and width measurement 504 are advantageously combined in which a peak portion or multiple peak portions of an input signal that exceeds a predetermined threshold is detected and a width of the peak portion is determined. The peak detection and width measurement are further combined with a novel variable width shape generation methodology 506 in which a variable width shaping response is applied 510 to the peak portion responsive to the peak portion width. Additionally, a novel receiver technique 1390 can be included to reduce or eliminate the upstream BER impact using downstream oversampled shaping.

Abstract: A system and method is provided for controlling the mode of operation in a UWB receiver. In one variation, the system and method determines the mode of operation by reading a set number of samples of the signal, estimating mode parameters, calculating a mode probability, and then transitioning in a finite state machine between a track and an acquisition state depending on the value of the mode probability. Exemplary versions of the mode controller include a signal to noise ratio calculator, a signal and noise power estimator, and an AGC initialization circuit.

Abstract: A dual mode transmitter for GSM and UMTS operation is provided. The GSM and UMTS paths share an oscillator and an intermediate frequency stage. Also, with the exception of the final stage of power amplification, the transmitter is provided as an integrated device.

Abstract: A data communication receiver comprises an equalizer for adapting to each of a plurality of channels to open the eye for each channel in a Gigabit (1000BASE-T) transceiver. The eye is open for a first channel (A) and a transformation process applies the coefficients of that adaptation to open the eye for the other dimensions. The transformation process keeps the magnitude response constant.

Abstract: A method and signal processing apparatus for reducing the number of bits of a digital input signal (Mi), includes adding a pseudo-random noise signal (Na) to the digital input signal (Mi) to obtain an intermediate signal (Di), the pseudo-random noise signal (Na) being defined by noise parameters (Np), and quantizing the intermediate signal (Di), having a word length of n bits, to a reduced word-length signal (Me) having a word length of m bits, n being larger than or equal to m. The method further includes quantizing the intermediate signal (Di) using a first transfer function which is non-linear, the first transfer function being defined by non-linear device parameters (NLDp).

Abstract: In a communication system in which a transmitter transmits data over a communication channel of a fixed bandwidth to a receiver, the method according to which the transmit data rate is continuously adjusted to a rate which is substantially equal to a short-term average data rate. The channel capacity and/or other characteristics of the system, is continuously adjusted, through changes in transmit power, symbol rate and modulation format, to a level at which the ratio of received signal energy per bit to noise spectral density (Eb/N0) at the receiver is close to but above its minimum acceptable level, thereby matching the channel capacity and/or other characteristics of the system to the traffic. The system has further attributes which adjust the transmit data rate responsive to conditions involving at least one of data traffic levels, power reserve emergency, thermal load and message priority.