Abstract: A digital processing system P, configured as a regular tree with n+1 levels S0, S1, S2 . . . Sn and degree k, provided in the form of a circuit Pn on the level Sn and forms the root node of the tree, an underlying level Sn−q, q=1,2, . . . n−1, in the circuit P provided nested in the Kq−1 circuits Pn−q+1 on the overlying level Sn−q+1, each circuit Pn−q+1 on this level including k circuits Pn−q. A q=n defined zeroth level in the circuit Pn includes from Kn−1+1 to Kn circuits P0 which form kernel processors in the processing device P and on the level S0 and constitute the leaf nodes of the tree, the kernel processor P0 being provided nested in each of the circuits p1 on the level S1. Each of the circuits P1, P2, . . . Pn, includes a logic unit E which generally is connected with circuits P0, P1, . . . Pn−1. Each of the circuits P0, P1, . . . Pn has additionally identical interfaces I, such that IP0−IP1− . . .

Abstract: A digital communication interface for downloading software for upgrading the functionality of a telephone craftsperson's butt-in test set is configured to be powered externally by respectively different voltages ported from the host computer and the test set. Digital communication connectivity for software upgrade signals sourced from the host computer for delivery to the control processor of the test set, and for communication signals sourced from the test set for delivery to the host computer, is effected by a pair of opto-isolators which provide signal integrity isolation between the respectively different parameters of the host computer and the test set.

Abstract: An interface circuit transmits data via a serial interface to and from a processor. A first-in-first-out memory is disposed between the serial interface and the processor. A suitable method transmits data which are received and read into the memory serially bit by bit and are read out of it byte by byte by the processor, or, respectively, can be written byte by byte into the memory by the processor and can be transmitted from the memory bit by bit.

Abstract: A configurable universal asynchronous receiver/transmitter (UART) facilitates efforts to upgrade UART functionality in the field and replace older UART devices. In one example embodiment, an integrated circuit includes a universal asynchronous receiver/transmitter configured and arranged to operate in one of a plurality of modes, with each mode being selectable in response to mode-selecting data. The integrated circuit device includes an interface circuit electrically connected to the universal asynchronous receiver/transmitter and adapted to present the mode-selecting data to the universal asynchronous receiver/transmitter. The integrated circuit device also includes a selection circuit adapted to enable the mode-selecting data to pass from the interface circuit to the universal asynchronous receiver/transmitter.

Abstract: There is disclosed a method and apparatus for changing the frequency content of an input spectrum and a method and apparatus for reducing the perceptibility of a component of an input signal. The first aspect involves adjusting frequency components of the input spectrum in response to a time varying adjustment frequency spectrum to produce an output frequency spectrum including adjusted frequency components of the input spectrum. The time varying input spectrum may be produced by selectively addressing a number of individual sub-spectra at different times. In addition, the input spectrum may be divided into a plurality of sub-spectra and each sub-spectrum may be operated on separately by a different adjustment frequency spectrum at different times. In addition, a perceptual model may be used to enhance the adjustment of the input spectrum or sub-spectra.

Abstract: A method, corresponding apparatus and corresponding system for determining a dynamical quantity of a receiver of signals conveying information useful in estimating the dynamical quantity, the method including the steps of: providing a single-point solution, by solving for the dynamical quantity of the receiver using a single-point solution having as an input the information useful in estimating the dynamical quantity being determined; providing a plurality of filter solutions (such as predictive filter solutions), and each assuming a different motion model for the receiver; and combining the plurality of filter solutions to provide a first value of the dynamical quantity based on weights that take into account the likelihood of the suitability of each motion model, with the likelihood determined on the basis of agreement of the first value of the dynamical quantity compared with a second value of the dynamical quantity as indicated by a single-point solution.

Abstract: A method and apparatus for communicating information between a remote location and a user. Information from the remote location or the user is received by the inventive apparatus and processed by configurable circuitry to a form that can be received and used by the intended recipient. The reconfigurable circuitry can be changed manually by a human user or remotely through the receipt of appropriate signals. Accordingly, the apparatus can be reconfigured to be able to receive information that is transmitted in different forms from those forms that are receivable before reconfiguration.

Abstract: A FIR chip is used in a wireless subscriber unit. The subscriber unit includes a processor for transcoding an input signal to provide digital input symbols. A received output signal is demodulated. Digital output symbols are synthesized from the demodulated output signal processor and filtered digital input symbols are provided. An internal address decoder decodes to allow the processor to access internal functions of the FIR chip. A control and status register allows the processor to read the status of and control the internal functions of the FIR chip. A FIR filter filters the digital input symbols. A transmit timer controls timing which allows the processor to control the FIR filter. A receive timer generates timing signals for timing transcoding operations and synthesizing operations connected to the processor.

Abstract: A data traffic predictor for a modem, and a method for power management in a modem, are described. The data traffic predictor includes a data traffic monitor, a periodicity detector and a power mode controller. The data traffic monitor monitors incoming data to the modem. If the periodicity detector determines if the data is substantially periodic, which indicates that the data traffic is isochronous, the power mode controller changes the modem power mode to quiescent power mode operating at a minimum data rate to permit the isochronous data traffic to be carried. The apparatus and method of the present invention permit low level control of a modem's power mode, and permit the use of a quiescent power mode running at a reduced data rate, without sacrificing quick recovery time to a full on power mode when required.

Abstract: One embodiment of the invention is a subscriber unit for transmitting communication signals. The subscriber unit comprises a cipher stream generator which generates a cipher stream to encipher a digital data stream. A data stream mixer mixes the cipher stream with the digital data stream. An antenna radiates the mixed cipher and data stream as a communication signal. Another embodiment of the invention is a subscriber unit for receiving communication signals. The subscriber unit comprises a cipher stream generator for generating a cipher stream with the received communication signal to produce a decoded data stream. The cipher steam generator includes first and second linear feedback shift registers. Each has a clock input and an output. The outputs are combined to generate the cipher stream. The output of the second register is combined with a clock signal which is inputted to the clock input to the first register.

Abstract: An improved modem architecture and associated method are disclosed that integrate modem and line-isolation circuitry so as to achieve modem functionality and system-side isolation functionality on a single integrated circuit.

Abstract: A filter to apply a window function to a digital signal is provided. The filter has a memory for storing a basic set of values representing a single window. An adapter can generate from this basic set a plurality of adapted sets of values, where the adapted sets of values define window functions having different window sizes. The adapter has an input for receiving a control signal that allows the adapter to select the proper adapted set to suit the digital signal being processed. The application of the window function is effected on successive frames of the digital signal by using the adapted set of values generated by the adapter in response to the control signal. The filter has VAD applications, among others.

Abstract: A phase adjusting circuit for a semiconductor memory includes a D/A converter 20 which includes a D/A converting circuit 31 receiving code signals A1 to An, and a current mirror circuit 32 having an input transistor P1 connected to an output node S of the D/A converting circuit 31 and an output transistor P2 for supplying an output current lout. A switch circuit 34 is connected between a gate of the input transistor P1 and a gate of an output transistor P2, and a capacitor 36 is connected to the gate of an output transistor P2. The switch circuit 34 is turned off before the code signals A1 to An applied to the D/A converting circuit 31 change, and after a fluctuation of the potential on the output node S of the D/A converting circuit 31 has been settled, the switch circuit 34 is turned on, with the result that a hazard occurring in the D/A converting circuit 31 is prevented from being transferred to the current mirror circuit 32.

Abstract: In a Universal Mobile Telecommunications System (UMTS) based wireless system, a channelization code-tree is partitioned into two sets: a permanent set and shared a shared set. Those codes in the permanent set are assigned to low data rate users for the duration of a session, or connection. Those codes in the shared set are assigned to high data rate users on a frame-by-frame basis using a downlink shared (DSCH) channel. The partition boundary between the permanent set and the shared set can be dynamically shifted based on traffic conditions.

Abstract: In accordance with the preferred embodiment of the present invention, excess power is distributed to certain streams in order to increase the stream's signal quality, and thus, its encoding rate. Although certain streams will have their overall power, and thus their signal quality reduced, in the preferred embodiment of the present invention the reduction in signal quality is limited so that the encoding rate for these streams remains unchanged.

Abstract: A data transmission device for executing data transmission in environments where the noise level changes periodically minimizes delay of fast data. A multiplexing/synchronization control section receives data (in which the ratio between fast data and interleave data is fixed) which are supplied from an upper layer device at a prespecified data rate, and separates the data into fast data and interleave data. The fast data is supplied to a tone ordering section without changing its data rate. Meanwhile, an interleaving section executes interleaving to the interleave data, and a rate converter controls the data rate of the interleave data and supplies the interleave data to the tone ordering section.

Abstract: A communication system employs a HARQ-type retransmission scheme. Bits (701) received on a first transmission are stored and combined with the bits received on later transmissions thereby increasing the likelihood of a correct decoding on later transmissions. Similarly the bits received on the second or later transmissions are stored for combining with subsequent received bits. Specific information needed at the receiver is identified and requested from the transmitter. More particularly, information that is retransmitted in a second or later transmission in the HARQ scheme is determined from a reliability of individual constituent bits in the mother codeword or from an overall reliability of the received codeword. Based on these reliability metrics, the most unreliable set of the constituent bits are requested or, in the alternative, a specific number of constituent bits is requested.

Abstract: In a spread spectrum receiver, a first despread signal is produced by a despreading circuit corresponding to a first symbol rate. The despreading circuit is responsive to a command signal for subsequently producing a second despread signal corresponding to the second symbol rate. A symbol rate estimation circuit is provided for estimating, from the first despread signal, the transmitted symbol rate of the spread spectrum signal as one of the first and second symbol rates. If the transmitted symbol rate is estimated as the first symbol rate, the despreading circuit continues producing the first despread signal. If the transmitted symbol rate is estimated as the second symbol rate, the estimation circuit supplies the command signal to the despreading circuit to produce the second despread signal. A decoding circuit decodes the first and second despread signals.

Abstract: A multiplexing/synchronization control section receives data (in which the ratio between fast data and interleave data is fixed) which are supplied from an upper layer device at a prespecified data rate, and separates the data into fast data and interleave data. An interleaving section executes interleaving to the interleave data. The fast data and the interleave data, whose data rates have been controlled by a fast data rate converter and an interleave data rate converter respectively, are supplied to a tone ordering section to be assigned to carriers of a symbol (frame). In the case where the amount of data which can be assigned to each NEXT symbol is larger than or equal to a “specific amount” which corresponds to the fixed data rate of the fast data supplied from the upper layer device, the tone ordering section assigns fast data of the “specific amount” to each symbol regardless of whether the symbol is a FEXT symbol or a NEXT symbol.

Abstract: A circuit arrangement, program product and method in one aspect utilize three stage input staging logic to receive source synchronous data in a source synchronous communications system such as a PCI-compatible communication system. In another aspect, two stage input staging logic is supplemented by at least one holding latch disposed intermediate the output of the two stage input staging logic and a common clock synchronizing circuit to effectively increase the hold time of a staging latch in one of the latching stages prior to common clock synchronization. The holding latch may be clocked concurrently with at least one other staging latch in the input staging logic that is clocked later in a data phase than the staging latch that feeds the holding latch so that the data clocked into both such staging latches is available for common clock synchronization at roughly the same point in time.

Abstract: In one embodiment of the method of adaptively selecting an airlink coding scheme in a telecommunications network, a coding scheme operating region is determined based on a currently used coding scheme and measurements representative of a block error rate. A block error coding scheme is determined based on the determined coding scheme operating region. In another embodiment of the method of adaptively selecting an airlink coding scheme in a telecommunications network, a first coding scheme is determined based on measurements representative of one or more conditional channel quality metrics, and a second coding scheme is determined based on measurements representative of a block error rate. One of the first and second coding schemes is selected as the coding scheme.

Abstract: A clock synchronization system for synchronizing a first communications device and a second communications device to enable digital communication there between. A first device generates a first clock signal Fa. A second device generates a second clock signal Fb2. The second device includes a first PLL circuit and a second PLL circuit. The first PLL circuit is adapted to increase Fa by a factor K to produce a signal Fak. The second PLL circuit is adapted to increase Fak by a factor L to produce a signal Fbn. The second PLL circuit is further adapted to decrease Fbn by a factor N to produce the signal Fb2. The first PLL circuit and the second PLL circuit are adapted to adjust the values of K, L, and N such that a frequency lock is achieved between Fa and Fb2. enabling digital communication between the first device and the second device without requiring a predetermined phase lock between Fa and Fb2.

Abstract: Digital circuitry, for use for example in a mixed-signal device such as a digital-to-analog converter, has decoders (22, 24) which process a digital input word (D1˜Dm) to derive thermometer-coded signals (T, {overscore (T)}) for controlling one cell of an array of cells in the device. The decoders commence operation at the rising edge of a first clock signal (DIGCLK). Each cell has a first, D-type latch (26) clocked by a second clock signal (CLK2) that is delayed by a preselected delay time &Dgr;1 relative to the first clock signal, and a second, transparent latch (32) clocked by a third clock signal (CLK3) whose rising edge coincides with the rising edge of the first clock signal and whose falling edge coincides with the rising edge of the second clock signal. The rising edge of the third clock signal is not affected by jitter associated with a delay element (28) used to delay the first clock signal by &Dgr;1.

Abstract: A signal generator and signal receiver, as well as method of signal generation and transmission, in which selected unstable periodic orbits of a lossy chaotic system are identified and extracted, and portions of the orbits concatenated together to form a resultant signal. The selected orbits are known to the signal detector a priori. The signal detector detects the transmitted signal by correlation of the received signal with the known extracted orbits, also allowing the detector identify information which the generator imposed onto the signal.

Abstract: A method for data detection includes signal transition detection of an input signal. When a falling edge is detected, a rising edge in a negative signal is generated. When a rising edge is detected, a rising edge in a positive signal is generated. Data is latched from the bus for the rising edge of the positive/negative edge signal. A falling edge in the positive/negative edge signal is generated after a period of time. The steps are repeated for each detected signal transition. A data detection apparatus includes a QAEDN to generate a rising edge on the negative signal for detected falling edges. A memory unit latches data from the bus for rising edges of the negative signal. A QAEDP generates a rising edge on a positive edge signal in response to detected rising edges. A memory unit latches data from the bus for rising edges of the positive signal.

Abstract: Techniques to determine data rates for a number of data streams transmitted via a number of transmission channels (or transmit antennas) in a multi-channel (e.g., MIMO) communication system. In one method, the “required” SNR for each data rate to be used is initially determined, with at least two data rates being unequal. The “effective” SNR for each data stream is also determined based on the received SNR and successive interference cancellation processing at the receiver to recover the data streams. The required SNR for each data stream is then compared against its effective SNR. The data rates are deemed to be supported if the required SNR for each data stream is less than or equal to its effective SNR. A number of sets of data rates may be evaluated, and the rate set associated with the minimum received SNR may be selected for use for the data streams.

Abstract: A method and apparatus are provided for delivering data within a frame to a peer station, the frame having at least a first and a second symbol. The method comprises determining whether the data in the first symbol is greater than or equal to a coding-gain threshold, loading at least a portion of the data within at least the second symbol in response to determining the data in the first symbol is greater than or equal to the coding-gain threshold to provide a new frame, and transmitting the new frame.

Abstract: In accordance with one embodiment of the invention, an integrated circuit includes: a transceiver capable of transmitting and receiving signals complying with the standard Universal Serial Bus (USB) specification. The transceiver is further capable of transmitting and receiving signals at a frequency higher than the signals complying with standard USB specification. The transceiver is further capable of configuring itself between transmitting and receiving the higher frequency signals and the standard USB signals.

Abstract: In a CELP coder a comparison between a target signal and a plurality of synthetic signals is made. The synthetic signal is derived by filtering a plurality of excitation sequences by a synthesis filter having parameters derived from the target signal. The excitation signal which results in a minimum error between the target signal and the synthetic signal is selected. The search for the best excitation signal requires a substantial computational complexity. To reduce the complexity a preselection of a small number of excitation sequences is made by selecting a small number of excitation sequences resembling the most a backward filtered target signal. With this small number of excitation sequences a full complexity search is made. Due to the reduced number of excitation sequences involved in the final selection the required computational complexity is reduced.

Abstract: An apparatus generally having a threshold slicer, a state logic device and a converter. The threshold slicer may be configured to generate a (i) first signal having an initial state of a plurality of states in response to a preceding value and a present value from an input signal and (ii) a second signal having a plurality of levels in response to the preceding value and the present value. The state logic device may be configured to generate a third signal having a sequence of the plurality of states starting with the initial state in response to the first signal. The converter may be configured to generate an output signal having the plurality of levels in response to the plurality of states in the third signal.

Abstract: An improved transmitter capable of achieving high linearity with minimal power dissipation is disclosed, comprising a digital phase splitter and an output stage. The digital phase splitter includes a positive phase digital-to-analog converter (DAC) for converting the positive phase portion of a set of input digital data into an analog signal, and a negative phase DAC for converting the negative phase portion of the set of input digital data into another analog signal. The analog signals from the phase splitter are passed to the output stage for transmission onto a transmission medium. The transmitter may be operated in low power dissipation mode. Because the phases of the input digital signal are split in the digital domain prior to the output stage, the output stage experiences minimal crossover distortion. Consequently, the transmitter is able to minimize power dissipation without suffering from poor linearity performance.

Abstract: In a CELP coder a comparison between a target signal and a plurality of synthetic signals is made. The synthetic signal is derived by filtering a plurality of excitation sequences from a one dimensional codebook by a synthesis filter having parameters derived from the target signal. The excitation signal that results in a minimum error between the target signal and the synthetic signal is selected. In order to reduce the complexity of the search for the best excitation signal, the selection is done in two stages. First a preselection of a small number of excitation sequences is made by selecting only every L.sup.th codebook entry for preselecting a plurality of excitation sequences. Thereafter, with this small number of excitation sequences, a fill complexity search is made in which all excitation sequences surrounding the preselected ones are involved in the selection.

Abstract: In a CELP coder, a comparison between a target signal and a plurality of synthetic signals is made. The synthetic signal is derived by filtering a plurality of excitation sequences by a synthesis filter having parameters derived from the target signal. The excitation signal which results in a minimum error between the target signal and synthetic signal is selected. The search for the best excitation signal requires a substantial computational complexity. To reduce the complexity, a preselection of a small number of excitation sequences is made using a reduced complexity synthesis filter. With this small number of excitation sequences, a full complexity search is made. Due to the reduced number of excitation sequences involved in the final selection, the required computational complexity is reduced.

Abstract: An address generator and an address generating method are described. In the address generator, a first counter counts a plurality of clock pulses, generates a first group count, which indicates one of the group addresses of an interleaver block, at each clock pulse, and generates a carry after counting a predetermined number of clock pulses. A second counter receives the carry from the first counter, counts the plurality of carries, and generates a position count indicating one of the position addresses in each group. If the group count is one of the unavailable group count values representative of unavailable groups, or the group count is one of partially unavailable group count values representative of groups having both available and unavailable position addresses and the first position count is one of unavailable position count values representative of unavailable position addresses, a controller controls the first and second counters not to output the first group count and the first position count.

Abstract: An adaptive quality control loop for link rate adaptation based on modulation and/or coding schemes (also referred to as “MCS levels”) and one or more spreading codes that adaptively selects channel condition thresholds in real-time without measuring all the factors that affect selecting optimal channel condition thresholds. The adaptive quality control loop involves adjusting the channel condition thresholds with variable up and down steps based on target quality metrics along with measurements such as error detection results, relative frequencies of visiting each MCS level, and transmitted data rates, wherein the target quality metrics can be a block error rate or bit error rate target criterion. If the target quality metric is a block error rate target criterion, the variable step is determined using a desired MCS error rate based on MCS probabilities, MCS error rates and the block error rate target criterion.

Abstract: A parameter detection system and method, detects the receipt of a valid communication from an entity, determines the data rate of the communication from the entity, and determines other parameters of the communication from the other entity. The parameter detection circuit configures a precision time generator to provide a timing signal at the appropriate rate to sample data associated with said valid communication, and configure a receiver/transmitter with the determined parameters of the communication.

Abstract: The present invention provides a line termination circuit for matching the characteristic impedance of a transmission line, or more generally, a network. The present invention receives the voltage as present on the transmission line and attenuates it such that circuit components rated for lower voltages may be used to produce the reflected impedance. The attenuated voltage is placed across a scaled impedance which results in a reflected impedance substantially equal to the characteristic impedance of the transmission line. The line termination circuit uses a feedback loop to reflect the ground referenced scaled impedance across the transmission lines. The circuit generates a current having a value of one over the characteristic impedance of the network, which ensures that the reflected impedance, from the network, is substantially equal to the characteristic impedance of the network.

Abstract: A digital direct access arrangement (DAA) circuitry may be used to terminate the telephone connections at the user's end that provides a communication path for signals to and from the phone lines. Briefly described, the DAA provides a programmable means for the DC termination for a variety of international phone standards. The invention may also be utilized with means for transmitting and receiving a signal across a capacitive isolation barrier. More particularly, a DC holding circuit is provided in which a programmable DC current limiting mode is available. In the current limiting mode, power may be dissipated in devices external to a DAA integrated circuit. Moreover, much of the power may be dissipated in external passive devices, such as resistors.

Abstract: A device and method for initializing the state of a computer, including individual transmission lines within the computer. A signal sending circuit provides an output signal onto a transmission line. While the signal is propagated along the transmission line, a second signal is provided in series on the same transmission line. Simultaneously therewith, the value of the first signal is stored in a data storage element. Subsequent bits may be placed on the transmission line before the first bit is received at a second end of the transmission line. Each bit placed on the transmission line is stored in a respective data storage element. The value of the data in the data storage elements can be tested to determine the exact state of any transmission line in the system.

Abstract: Digital communication signals that encode information in the phase may be susceptible to phase error from many sources. The invention corrects for carrier and sampling phase errors, as well as additive phase noise. A digital phase locked loop simultaneously tracks the carrier phase error and the sampling phase error, and corrects the signal in the frequency domain. The invention may use the sampling phase error to advance or delay the sampling window used to convert the signal from the time domain to the frequency domain.

Abstract: A mobile communication apparatus having an antenna array and a mobile communication method performed in the mobile communication apparatus, wherein the mobile communication apparatus includes a base station and mobile station, each having an antenna array. The mobile station measures the downlink characteristics of a channel for each antenna from a signal received from a base station, determines long-term information in which the correlation property of the channel for each antenna has been reflected from the measured downlink characteristics, transforms the long-term information into a feedback signal, and transmits the feedback signal to the base station.

Abstract: A synchronized data capture circuit configured to synchronize capturing of data in a first plurality of data signals with a first plurality of timing signals to output a synchronized data capture signal. The synchronized data capture circuit includes a timer generator having a first timer generator output. The timer generator is coupled to receive the first plurality of timing signals and to serially output on the first timer generator output, as a first high frequency timing pulse stream, first timing pulses responsive to timing pulses of the plurality of timing signals. The first high frequency timing pulse stream has a timing pulse stream frequency that is higher than a timing input frequency associated with one of the first plurality of timing signals. The synchronized data capture circuit also includes first plurality of data driver circuits coupled to receive the first plurality of data signals and the plurality of timing signals.

Abstract: The invention relates to a method and equipment for network independent clocking in a telecommunication system, particularly in data transmission where the maximum data rate on a traffic channel is equal to the user data rate. In the invention a transmitter compares the network independent clock and the network clock to detect a slip and, upon detecting a slip, performs compensation of the network independent clock by changing the number of the redundant bits in user data. The user data is transmitted through a traffic channel to a receiver. The receiver, upon detecting the network independent clock compensation in the received user data, restores the original redundancy and temporarily adjusts the network independent clock so as to compensate for the change caused by the restoration of the redundancy in the outbound user data stream.

Abstract: A skip-free retiming system and method for transmission of digital information in a plesiochronous data communication system is described. The system is capable of supporting an unlimited number of retimers in serial data path between a first and a last node. The retimers are configured to retime, amplify and retransmit a received data stream without altering the received data rate. Thus, the data rate from the first node is received at the same frequency at the last node, regardless of the number of retimers. In general, the retimer performs rate compensation on a retimer local clock, rather than on the data stream, so the attributes of the clean retimer clock can be applied to the data stream without changing the data rate.

Abstract: A method and apparatus for increasing the allowable transmission rate of Digital Subscriber Lines (DSL(s)) in a binder group. The DSL(s) in the binder group are monitored to determine their actual transmission rate. The allowable transmission rate of individual DSL(s) is adjusted in order to make sure that it does not exceed some target level, but that in case many lines are inactive or in a keep-alive mode, that the transmission rate of the active lines can be substantially higher than the transmission rate based on all lines being active and transmitting at their maximum rate. Avantageously, the actual throughput for the binder group can be increased substantially above that allowed for a static assignment of transmission rates.

Abstract: The device for sending/receiving digital data is capable of processing different bit rates from a group of predetermined bit rates. It includes a channel coding/decoding stage including interleaving means MET and deinterleaving means MDET including a memory MM whose minimum size is fixed as a function of the maximum bit rate of said group and having a first memory space ESM1 assigned to the interleaving means and a second memory space ESM2 assigned to the deinterleaving means. The size of each of the two memory spaces is parameterable as a function of the bit rate actually processed by the device.

Abstract: A universal interface for communicating information to a proprietary physical interface. At least one output module is provided for transmitting information and an input module is provided for receiving the information. The output module and the input module are configured according to communication parameters of a predetermined type of physical interface to which the output module and the input module interface such that communication of the information is facilitated therebetween.

Abstract: A mixed waveform configuration for wireless communications including a first portion that is modulated according to a single-carrier modulation scheme and a second portion that is modulated according to a multi-carrier modulation scheme. The waveform is specified so that a channel impulse response (CIR) estimate obtainable from the first portion is reusable for acquisition of the second portion. The first portion includes a preamble and header and the second portion typically incorporates the payload.

Abstract: A method of bypassing vocoders in a digital mobile communication system, comprising the step of appending bypass mode data to data transmitted from a plurality of mobile stations, the bypass mode data instructing the vocoders not to perform encoding/decoding operations, and the step of transmitting the resultant data. According to the present invention, the unnecessary encoding/decoding operations are omitted for a mobile to mobile communication. Therefore, the present invention has the effect of removing the delay time and enhancing the voice quality.

Abstract: A ring oscillator includes an even-numbered plurality of ring coupled delay stages. Each delay stage includes a differential amplifier, a voltage clamping circuit, and a current source. The differential amplifier receives first and second input signals from a preceding delay stage. The differential amplifier provides a first output signal and a complementary second output signal at first and second nodes, respectively. The voltage clamping circuit is coupled between the first and second nodes to limit a peak-to-peak voltage swing of each of the first and second output signals. The current source is coupled to the differential amplifier and varies a bias current in accordance with a delay bias voltage.