Abstract: A method and signal processing apparatus for reducing the number of bits of a digital input signal (Mi), includes adding a pseudo-random noise signal (Na) to the digital input signal (Mi) to obtain an intermediate signal (Di), the pseudo-random noise signal (Na) being defined by noise parameters (Np), and quantizing the intermediate signal (Di), having a word length of n bits, to a reduced word-length signal (Me) having a word length of m bits, n being larger than or equal to m. The method further includes quantizing the intermediate signal (Di) using a first transfer function which is non-linear, the first transfer function being defined by non-linear device parameters (NLDp).

Abstract: A method and apparatus for buffering data samples in a software-based ADSL modem. The method includes receiving samples of data in a buffer and determining if the received samples of data will exceed the storage capacity of the buffer. Selected samples of data from the buffer are deleted in response to the storage capacity being exceeded. The selected samples of data that were deleted are then reconstituted.

Abstract: The present invention provides a burst mode power line data network system having at least one burst mode power line transmitter (BMPLT) and at least one burst mode power line receiver (BMPLR) for enabling signaling, telephony and data communications via power lines without using carrier frequencies. The BMPLT transmits line encoded bursts of information via a power line to the BMPLR which receives the line encoded bursts of information and has a maximum inter-packet idle time of only one bit between bursts. The invention permits the use of AC coupling in a receiver and results in outputting data with constant pulse widths irrespective of optical signal power levels, etc. In one embodiment, a receiver has a wide dynamic range, is highly stable, may be used over all frequencies of interest without developing high speed electronics or optical components, and has no sensitivity penalty as compared to existing burst mode/packet mode receivers.

Abstract: A method and apparatus is disclosed for improving performance of a communication receiver. In one embodiment a method and apparatus is configured to process a communication signal by adjusting the amplification level of the signal and monitoring for a corresponding change in the error rate which indicates the increased error rate is caused by an interference or jammer signal. A method and apparatus is disclosed which reduces the error rate if the error rate can be reduced by activating error reducing operations. In one embodiment current flow to a mixer is increased to reduce the error rate. The apparatus may be further configured to periodically monitor the error rate during periods when error reducing operations are active. If the monitoring determines the error rate has sufficiently decreased then the receiver operation is restored to normal operation. Phase offset adjustment may also occur to further reduce the error rate.

Abstract: Decoders process a digital input word to derive thermometer-coded signals for controlling one cell of an array of cells, commencing operation at the rising edge of a first clock signal. Each cell has a first latch clocked by a second clock signal, delayed by a preselected delay time ?1 relative to the first clock signal, and a second, transparent latch clocked by a third clock signal whose rising edge coincides with the rising edge of the first clock signal and whose falling edge coincides with the rising edge of the second clock signal. The rising edge of the third clock signal is not affected by jitter associated with a delay element used to delay the first clock signal by ?1. The falling edge is affected by such jitter, but is prevented from feeding through to final outputs because the second latch is non-transparent at that falling edge.

Abstract: A reverse data rate controlling method in a mobile communication system for transmission of packet data is provided. In an embodiment of the present invention, an RRL (Reverse Rate Limit) message includes an ignore RAB (Reverse Activity Bit) field to ensure a predetermined data rate for a particular access terminal (AT). In another embodiment of the present invention, an access probability is set for each data rate in the RRL message. Upon receipt of an RAB, an AT compares a random number with the access probability for its data rate and increases or decreases the data rate according to the comparison result.

Abstract: An information apparatus switches a display at a predetermined area which includes at least a part of a portion where an electromagnetic-wave emitting unit used for data communications with a data storage device is disposed, according to data communication processing with the data storage device, and emits sound generated according to the processing at corresponding timing.

Abstract: PL demodulation section 203 demodulates pilot signals of a received signal. SIR detection section 205 detects the reception quality of the demodulated pilot signals. fd detection section 206 detects a Doppler frequency using the demodulated pilot signals. Requested modulation method deciding section 207 decides a modulation method to be requested to the base station using the reception quality of pilot signals and the detected Doppler frequency. Command generation section 208 generates a command corresponding to the decided modulation method. Adaptive demodulation section 204 performs demodulation processing on the received signal using the demodulation method corresponding to the modulation method decided by requested modulation method deciding section 207. This makes it possible to maintain good reception quality even in a fading environment.

Abstract: The invention relates to a method and an apparatus for determination of parameters for a transmission path in a telecommunications system by a transmitting/receiving apparatus having a transmitter and a receiver. In order to determine transmission parameters, a transmission signal is transmitted via the transmission path at a predetermined transmission power level and at a predetermined baud rate (fT) and an echo signal is sampled. A correlation function is calculated from the echo signal and from a correlation signal in a correlation function stage, an envelope function for the correlation function is calculated in an envelope function stage, the envelope function is evaluated, and an output signal is produced as a function of the relative timing and amplitude of the line start echo and/or of the line end echo in an evaluation stage.

Abstract: A digital direct access arrangement (DAA) circuitry may be used to terminate the telephone connections at the user's end that provides a communication path for signals to and from the phone lines. Briefly described, the DAA provides a programmable means for the DC termination for a variety of international phone standards. The invention may also be utilized with means for transmitting and receiving a signal across a capacitive isolation barrier. More particularly, a DC holding circuit is provided in which a programmable DC current limiting mode is available. In the current limiting mode, power may be dissipated in devices external to a DAA integrated circuit. Moreover, much of the power may be dissipated in external passive devices, such as resistors.

Abstract: A serial communication method and system is provided for use with a battery management system. The system includes a port capable of sending and receiving pulses over a single conductor, serial interface logic compatible with a serial protocol and capable of generating and detecting signals on the port and communicating the signals with an internal bus in the battery management system wherein each signal in the serial protocol is defined by a specific number of pulses. In the serial protocol, a zero signal corresponds to a sequence of two pulses, a one signal corresponds to a sequence of three pulses, an acknowledge signal corresponds to a sequence of four pulses, and a start signal corresponds to a sequence of five pulses.

Abstract: A method of combining a channel quality estimate for the radio channel based on direct measurement of carrier and interferer energies, and a channel quality estimate for the radio channel based on channel decoder metrics, to obtain a final channel quality estimate in terms of carrier-to-interference (C/I) ratio for the radio channel, which is more reliable, consistent and accurate than that obtained with the individual methods. After computing a direct channel quality estimate and a decoder metric-based channel quality estimate for the radio channel, confidence levels, P(direct), P (metric), are assigned to the two estimates. P(direct) is multiplied with the direct channel quality estimate and P(metric) is multiplied with the decoder metric channel quality estimate. The respective products are added to obtain the final channel quality estimate in terms of the carrier-to-interference (C/I) ratio for the radio channel.

Abstract: An Elastic Buffer is provided to process data in a computer network and a write controller is provided to control memory storage operation of such an Elastic Buffer. The write controller may comprise a comparator mechanism which detects if link data from a source contains an IDLE signal; a Jabber counter mechanism which counts each cycle of a link clock in which an IDLE signal is not detected, and resets the count each time the IDLE signal is detected, and which asserts a DISABLE signal for a single link clock cycle if a count value reaches a programmed time-out value; and a logic gate which logically combines outputs from the comparator mechanism and the Jabber counter mechanism to generate a Write control signal for prohibiting a corresponding link data sequence from being stored in memory storage of the Elastic Buffer so as to prevent data overflow in the memory storage.

Abstract: A transmit and receive protection circuit for use in a communication system is disclosed. The protection circuit uses a four-diode gate in which the currents through an input portion and an output portion of the diode gate are individually controlled by resistors located in their respective portions. This arrangement allows the DC currents through each portion to be independently controlled. By using resistors to independently control the DC currents through each portion of the diode gate, better control over the individual DC currents can be achieved, leading to effective AC resistances which are more predictable. This arrangement results in a predictable low loss protection circuit at a minimal expense.

Abstract: The present invention provides a communication device, such as a modem, that is capable of detecting whether it is capable of operating in a mode that is compatible with one or more of the Spectrum Management Classes. The modem automatically selects a mode of operation that is compliant with one or more of the Spectrum Management Classes. The communication device also determines whether it is capable of operating in multiple modes that are compliant with multiple Spectrum Management Classes, and is capable of selecting the modes of operation that optimize the performance of the communication device. Furthermore, the communication device is capable of determining when it is not capable of operating in a mode that is compliant with at least one of the Spectrum Management Classes and which prevents operation of itself upon determining that it is not capable of operating in a mode that is compliant with at least one of the Spectrum Management Classes.

Abstract: A method of detecting the format of received information by measuring the time period during which information being received have a power that is at or above a defined threshold. The measured time period and the information rate of the received information are then used to determine an estimate information size value of the received information. The estimated information size value is then applied to an algorithm that determines the format of the received information. Therefore, the format of received information can be detected without the use of TFCI information.

Abstract: A system and method for calibrating power level during initial ranging of a network client device, such as cable modem facilitates communications between a network client device and a network device such as a cable modem termination system. The method includes dividing the dynamic range of the cable modem transmitter into a plurality of regions and attempting initial ranging in each of the different regions. If a response is not received from the network device, the method including adjusting the power level and reattempting the initial ranging in the different regions. Once a range response message is received from the network device the process of initial ranging is complete.

Abstract: Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchronizing the data input and/or output communication, and a mode input for controlling the data input and/or output communication. A clock/mode signal connects to the clock input of one circuit and to the mode input of the other circuit. A mode/clock signal connects to the mode input of the one circuit and to the clock input of the other circuit. The role of the mode and clock signals on the mode/clock and clock/mode signals, or their reversal, selects one or the other of the data communication circuits.

Abstract: A circuit or software generates a cipher stream. The software models components or the circuit comprises a first and a second plurality of linear feedback shift registers (LFSR). A first of the second plurality of LFSR has a clock signal as a clock input and others of the second plurality of LFSR each have an output of a previous one of the second plurality of LFSR as a clock input. A first of the first plurality of LFSR has the clock signal combined with an output of the first of the second plurality of LFSR as a clock input and others of the first plurality of LFSR each have an output of a previous one of the second plurality of LSFR combined with an output of another of the first plurality of LFSR as a clock input. An output of a last of the first plurality of LFSR and an output of a last of the second plurality of LFSR is combined to produce the cipher stream.

Abstract: A digital phase/frequency detector capable of being implemented with on-chip components and configured to detect signals having small modulation indices. Transition points within the signal are detected and the width between successive transition points measured and averaged. The average width measurements may be converted to width deviation values by subtracting out the width due to the carrier frequency. An interpolation may be performed between the current and previous values of the width deviation values to reduce quantization error. The interpolated values may be converted to frequency deviation values, and a predetermined number of the frequency deviation values may be averaged. The average frequency deviation values may then be equalized in order to reduce intersymbol interference. The resulting equalized values form soft estimates of the underlying source bits. Hard estimates of the source bits may then be derived from the soft estimates.

Abstract: A network transmitter for generating frames of data for transmission in a compatibility mode network including frames utilizing two modulation schemes is provided. The transmitter includes a first physical layer circuit generating frames utilizing a first modulation scheme and a second physical layer circuit generating frames utilizing a second modulation scheme. The second modulation circuit retrieves a compatibility mode header from the first physical layer circuit for generating compatibility mode frames.

Abstract: A method, article of manufacture and system to determine a bit rate of a signal is described.

Abstract: To provide a diffusion code generator capable of rendering interception and eavesdropping of communication difficult without influencing communication quality and transmission data. The spreading code generator generates orthogonal code list SP of a diffused information data rate cycle. Scrambling code generators generate M length code Sci, SCq of relatively long cyclicity respectively. Diffusion codes for in-phase components and orthogonal components are computed by ExOR circuits respectively, and diffusion code for in-phase components Ci and diffusion code for orthogonal components Cq are generated. A timer changes orthogonal code list SP currently set in a TTI cycle to another different type. In this case, switching by the timer is possible either only in a TTI cycle or in a cycle of T2=N*T1 (N: integer) taking opportunity of TTI or layer 1 synchronous interval unit T3.

Abstract: An apparatus for serial data communication between a plurality of IC chips with a reduced number of inter-chip signal lines. In the apparatus, one IC chip acts as a master, while the other chip(s) are slaved to it. In response to conditions internal to the master chip or in response to a request from at least one of the slave chips, the master chip generates a transfer control signal and a synchronization clock signal. The transfer control signal defines a transfer phase during which data transfer among the chips can take place. The chips take turns sending and receiving data in a multiplexed fashion, with sending and receiving parties designated by a count of synchronization clock signal cycles. The synchronization clock signal is generated at a high frequency, to allow fast data transfer.

Abstract: A type or brand of remote communication device is identified by measuring one or more characteristics associated with one or more signals sent by the remote communication device. The measured characteristics differ among different devices and/or manufacturers and are compared to known characteristics of one or more signals associated with known communication devices. Once the remote communication device is identified, the local communication device can enable one or more performance enhancing or deficiency compensation features based on the identity of the remote communication device.

Abstract: A 4-20 mA interface circuit for use, for example, in a valve controller, communicates with a two-wire loop. The interface circuit includes a power extraction circuit connected to the two-wire loop and operable to generate a DC operating voltage for use in powering the interface circuit and a related device, the power extraction circuit including a DC-to-DC converter that generates the DC operating voltage as a voltage having a smaller magnitude than a voltage between the two wires of the two-wire loop. The circuit also includes a current sensor connected to the two-wire loop and operable to generate a measure of an analog current through the two-wire loop, the measure being used in controlling a device associated with the interface circuit, and a digital communications circuit connected to the two-wire loop. The digital communications circuit is operable to inject a digital transmission signal on to the two-wire loop and to extract a digital reception signal from the two-wire loop.

Abstract: An encoder transforms at least a portion of a signal, counts the resulting transform coefficients having a zero value, and encodes the signal with the zero count. A decoder decodes the signal in order to recover the zero count. The decoder may also determine its own zero count of the signal as received and may compare the zero count that it determines to the recovered zero count. The decoder may be arranged to detect compression/decompression based upon results from the comparison, and/or the decoder may be arranged to prevent use of a device based upon results from the comparison.

Abstract: Interpolation filter circuit for a digital communication device for the filtering and clock-rate conversion of a digital input signal received from a data source with a symbol-clock data rate, having (a) an FIR filter (4), which filters the digital input signal received with the symbol-clock data rate in such a way that, in the passband frequency range of the interpolation filter circuit (1), the power spectral density characteristic of the filtered digital output signal emitted by the interpolation filter circuit essentially coincides with a prescribed desired characteristic of the power spectral density PSDdes; (b) a resampling filter (6) connected downstream of the FIR filter (4) for increasing the clock data rate of the digital input signal filtered by the FIR filter (4); and having (c) an IIR filter (8), which is connected downstream of the resampling filter and filters the resampled digital signal emitted by the resampling filter (6) in such a way that, in the cutoff frequency range of the interpolatio

Abstract: Disclosed is a zipper type Very high bit-rate Digital Subscriber Line (VDSL) system which comprises a transmitter including an inverse fast Fourier transformer for performing an inverse fast Fourier transform on input data, and a cyclic extension adder for adding a cyclic extension for each symbol to the data output from the inverse fast Fourier transformer and outputting the data to a transmission channel; and a receiver including a cyclic extension remover for removing the cyclic extension from the data received through the transmission channel, and a fast Fourier transformer for performing a fast Fourier transform on the data output from the cyclic extension remover.

Abstract: A switchable bandwidth optical receiver is implemented in a front-end of the receiver in at least one of three ways. A switchable impedance may be provided at the input to a preamplifier of the front end, the preamplifier of the front-end may have a switchable impedance therein, and/or a switchable filter may be provided at an output of the preamplifier.

Abstract: A microcontroller employs an asynchronous serial port for predictably updating a baud divisor during data reception. A write enable to the baud counter ensures that the current value of the baud count in the baud counter is greater than a predetermined number of clocks so that the working baud divisor to be loaded from the working baud divisor register is stabilized. The working baud divisor register is updated during data reception by the serial port by a software write to a visible baud divisor register provided the working baud divisor in the working baud divisor register is not being used to load the baud counter. A working baud divisor register thereby maintains a value guaranteed to be stable by the time a baud counter needs to be reloaded. A visible baud divisor register and the baud counter can be on different, possibly asynchronous clocks.

Abstract: The present invention relates to an arrangement for connecting antennas to ports of a transceiver unit in a base station. By using two circulators and a four port sputter a more flexible small base station is attained. The arrangement provides, at a low extra cost, the capability of adding an auxiliary transceiver unit to the base station.

Abstract: In a radio communication device of a CDMA system selectively operable in high and low power modes to receive a reception analog signal and to produce a demodulated signal, an A/D converter is controlled to reduce power consumption in the low power mode in comparison with the high power mode. The reduction of power consumption can be established by partially operating the A/D converter or by lowering a sample rate in the low power mode. A despreading portion connected to the A/D converter is also controlled in a manner similar to the A/D converter. Each of the high and the low power modes is indicated by a mode control signal produced by a CPU controller.

Abstract: The invention relates to methods and structures for connecting circuits and circuit elements processing electrical signals having very fast transition times, including sub-nanosecond transition times. It includes a connecting structure for connecting a multiplicity of signal lines at a common point to reduce unwanted reflections thereat; a single or multi-conductor female connector for receiving thin elements such as ribbon cable ends, printed circuit (PC) board edges, and the like; a structure for connecting together a multiplicity of ribbon cables terminating in such multi-conductor female connectors, and a further structure for connecting together a multiplicity of such multi-cable connectors to obtain maximum packing thereof, and minimum conductor lengths thereto, to obtain processing rates up to twenty-fold over what is available with present connecting methods and structures.

Abstract: A multiple data-rate receiver uses a signal rate detection technique that employs comparators to obtain information on the incoming data rate for enabling the appropriate receiver. Once a data rate is determined, only then is the appropriate receiver activated. Hence, power dissipation is kept to a minimum during the autonegotiation phase. This is a significant improvement over existing art which require two (or more) receivers to be active during the autonegotiation phase, consequently demanding high power dissipation. Because the autonegotiation phase can be lengthy, the present technique is preferable in many cases.

Abstract: Systems and methods for providing frequency compensation over a wide range of frequency drift are shown. The preferred embodiment utilizes a sweep mode function to provide frequency compensation over a range of frequency drift broader than the frequency drift accommodated by a phase lock loop, without increasing the noise characteristics of the phase lock loop. Accordingly, the preferred embodiment operates in a phase lock loop mode while frequency drift can be compensated for by the lock range of the phase lock loop circuitry. The preferred embodiment operates in sweep mode to step through a range of offset frequencies to position the phase lock loop mode where frequency drift can be compensated for by the lock range of phase lock loop circuitry. Additionally, a preferred embodiment of the present invention includes a drift mode in order to monitor frequency offset information, such as may be used in performing sweep mode functions and/or other control or management functions.

Abstract: An asynchronous sample rate estimator and a method for generating a rate estimate to track an asynchronous input sampled signal is disclosed. The present invention achieves lock quickly and maintains an optimum input buffer configuration and enhanced signal fidelity by responding quickly and accurately to changes in the incoming frequency. An asynchronous sample rate estimator receives and determines a measured sample period of an asynchronous input signal. Furthermore, a reciprocal frequency error signal and a current rate estimate signal are used to generate a rate estimate for tracking the read pointer to the write pointer of a FIFO buffer, as well as a phase correction signal for centering the write pointer in the FIFO buffer. An asynchronous sample rate estimator might also include an error gain generator for providing an error gain and a lock detector for indicating whether the system has achieved a locked condition.

Abstract: The invention provides a method for searching the frequency range of a digital data receiving device, said method including the steps in one embodiment of firstly identifying and disregarding analogue carrier frequencies in the range, then proceeding to estimate the initial starting frequency for a digital carrier by dynamic real-time pre-processing of the spectrum profile and then obtaining successive samples of the frequency range from the start position for the carrier until the center frequency for the carrier is located. In one embodiment the method includes the prediction of the center frequency estimations of all digital carriers for respective channels in the range prior to the search commencing. The method reduces the possibility of locking to analogue carriers, and can reduce the time required to perform a search in comparison to the current digital carrier frequency “search & lock” procedure.

Abstract: A circuit arrangement improves CPU efficiency by processing data through a FIFO circuit of a UART chip using a CPU adapted to detect, and respond with various options to, the current storage capacity of the FIFO circuit. In one example embodiment, a circuit arrangement includes a universal asynchronous receiver/transmitter (UART) chip having a FIFO circuit and an arithmetic logic unit (ALU) adapted to generate an N-bit variable binary signal, wherein the binary signal varies as a function of a current storage capacity of the FIFO circuit. The circuit arrangement further includes a control circuit communicatively coupled with the UART chip that is adapted to read the N-bit variable binary signal and, in response, to control the data flow through the FIFO circuit.

Abstract: A signal synchronization mapper for mapping an input data stream characterized by a first frequency (typically a SONET/SDH stream) into an output data stream characterized by a second frequency. A phase lock control loop containing a “delta-sigma” (&Dgr;-&Sgr;) modulator which functions as a voltage controller oscillator synchronizes the data rate of the output stream to that of the input stream in a manner which simplifies attenuation of jitter energy when the output data stream is desynchronized (demapped). The modulator generates an accurate pulse train by duty-cycle dithered modulation of the input stream, which the mapper interprets as stuff/nullide-stuff commands such that the mapping operation is lossless over time (i.e. the number of bits in equals the number of bits out over time) thus allowing utilization of a FIFO buffer without the need to monitor the buffer's depth or its pointers.

Abstract: A parallel interface is provided between a standard parallel port of a computer system and a modem so as to increase the data transfer rate between the two systems without modifying the hardware of the computer system and independently of the application program running on the computer system.

Abstract: A network device configured to detect a framing pattern includes a data scanner and a frame detector. The data scanner examines parallel bytes of data and detects portions of a framing pattern in the parallel bytes of data, identifies the phase of the framing pattern and outputs alignment information and phase information when a framing pattern has been detected. The frame detector receives the alignment information and phase information and determines whether framing patterns having the same phase relationship have been detected within a predetermined number of frames.

Abstract: A digital direct access arrangement (DAA) circuitry may be used to terminate the telephone connections at the user's end that provides a communication path for signals to and from the phone lines. Briefly described, the DAA provides a programmable means for the DC termination for a variety of international phone standards. The invention may also be utilized with means for transmitting and receiving a signal across a capacitive isolation barrier. More particularly, a DC holding circuit is provided in which a programmable DC current limiting mode is available. In the current limiting mode, power may be dissipated in devices external to a DAA integrated circuit. Moreover, much of the power may be dissipated in external passive devices, such as resistors.

Abstract: Cellular radiotelephone communication systems and methods downlink digital coded speech from a cellular radio exchange to a cellular radiotelephone base station and uplink downsampled (i.e. undersampled relative to the Nyquist rate of two samples per symbol) radiotelephone signals from the cellular radiotelephone base station to the cellular radio exchange. The downsampled radiotelephone signals are demodulated at the cellular radio exchange and the digital coded speech is modulated at the cellular radiotelephone base station. Diversity demodulation may be used at the cellular radio exchange, to diversity demodulate the downsampled radiotelephone signals at the cellular radio exchange.

Abstract: PL demodulation section 203 demodulates pilot signals of a received signal. SIR detection section 205 detects the reception quality of the demodulated pilot signals. fd detection section 206 detects a Doppler frequency using the demodulated pilot signals. Requested modulation method deciding section 207 decides a modulation method to be requested to the base station using the reception quality of pilot signals and the detected Doppler frequency. Command generation section 208 generates a command corresponding to the decided modulation method. Adaptive demodulation section 204 performs demodulation processing on the received signal using the demodulation method corresponding to the modulation method decided by requested modulation method deciding section 207. This makes it possible to maintain good reception quality even in a fading environment.

Abstract: Digital signals from a group of three or more circuits (104, 105, 106) are used to create an encoded or combined signal on a common transmission line (108). The encoded signal is then decoded at each different circuit to produce or recreate the digital signal asserted by each different circuit in the group. The encoded signal comprises a signal included in a set of unique signal values, with each signal in the set corresponding to a different combination of digital signals asserted by the group of circuits. Decoding the encoded signal at each circuit (104, 105, 106) in the group involves comparing the encoded signal to a particular reference voltage from a set of reference voltages. A particular reference voltage used in this comparison may be selected using one or more digital signals already decoded from the encoded signal.

Abstract: The arrangement has circuits (308) for forming a quantization window to a word, the quantization window being determined to be shorter that the word length, circuits (308) for reducing the word length by cutting the bits remaining outside the quantization window from the word circuits, (312) for determining the amount of saturation caused by the reduction of the word length, and circuits (316) for adjusting the position of the quantization window in the word to be reduced as a function of saturation.

Abstract: An arrangement to enable automatic baud rate speed negotiation between transceivers having different operating speed characteristics is implemented. When an event indicative of a possible baud rate mismatch occurs, control signals are generated and used to trigger a baud rate negotiation procedure. In the baud rate negotiation procedure, a predetermined pattern is transmitted, the baud rate of the respective transmitting transceiver is decoded, and the decoded baud rate is used to select an appropriate filtering for the transceiver.

Abstract: A method is provided for estimating a number of digital subscriber line nodes (220, 230) required to supply, from a line supply source (200), a geographically distributed network of substantially sequentially numbered twisted pair lines with digital subscriber line service. The method comprises the steps of: storing, in number order, data entries for every twisted pair line of the network, each data entry comprising a pair number and a line length of the respective twisted pair line in relation to the line supply source (200); sorting the entries stored in the database by line length; isolating those sorted entries whose twisted pair lines have a line length greater than a predetermined maximum line length in relation to the line supply source (200); sorting the isolated entries by number; and discriminating, from the sorted isolated entries, the presence of discrete groupings of substantially contiguous entries.

Abstract: A multi-drop bus input/output method and apparatus is disclosed. The apparatus comprises a multi-drop bus that has termination ends. The multi-drop bus also has a characteristic impedance. The multi-drop bus can be used for communication between devices. Devices that are attached to a termination end of the bus drive data onto the bus at the characteristic impedance. Devices that are attached to the bus, but not the termination ends, drive data onto the bus at one-half of the characteristic impedance. An end device terminates to ground with the characteristic impedance, and middle devices have high impedance, when not driving data.