Abstract: A fail-safe counter evaluator is provided to insure proper counting operations by fail-safe counters. The failsafe counter evaluator comprises a first microprocessor, a first counter, a second counter, a second microprocessor and a test channel. The first counter is configured as a counter in operation and disposed in the first microprocessor to receive externally generated count pulses. The second counter is disposed in the first microprocessor and configured to undergo a test. The test channel is configured to send an input test signal to the second counter based on test pulses from the second microprocessor. The first microprocessor and the second microprocessor are synchronized so that to coordinate a start and an end of the test. The second counter is evaluated after the test pulses have been sent to determine if the second counter is operating properly.

Abstract: System and method for generating hardware accelerators and processor offloads. System for hardware acceleration. System and method for implementing an asynchronous offload. Method of automatically creating a hardware accelerator. Computerized method for automatically creating a test harness for a hardware accelerator from a software program. System and method for interconnecting hardware accelerators and processors. System and method for interconnecting a processor and a hardware accelerator. Computer implemented method of generating a hardware circuit logic block design for a hardware accelerator automatically from software. Computer program and computer program product stored on tangible media implementing the methods and procedures of the invention.

Abstract: There is provided an improved method of managing the supply of electricity. The method comprises transferring, via contactless communication, first data from an electricity meter to a portable storage medium. The first data may be historical data collected by the electricity meter and related to the supply of electricity by the electricity meter. The method further comprises transferring, via contactless communication, second data from the portable storage medium to the electricity meter. The second data comprises instruction for the electricity meter to supply electricity.

Abstract: A dump cycle counting system is provided for a work machine. The system may include a payload carrier configured to contain a payload of material and a dump actuator configured to effectuate dumping of the payload out of the payload carrier. The system may also include a controller configured to control actuation of the dump actuator and a dump control device operatively coupled to the controller. The system may further include a load counter configured to record at least one dump cycle based on a command state of at least one of the dump control device and the controller.

Abstract: Timing circuitry may use control circuitry to control calibration circuitry to calibrate a counter so that an adder and a calibration period counter are not required. Concatenation circuitry may be used to concatenate a portion of the counter value and the calibration value to provide a calibrated value to the counter. The results from match circuitry may be used to provide status and control information to a calibration history bit and to an enable circuit. The counter may be an up counter or a down counter.

Abstract: A system that includes a controller for enabling an enumeration operation. The enumeration operation is performed by a controller (110) and logic elements (120) in a system, such that each logic element in the system assigns itself a unique identifier. Each logic element can then be controlled by another source or have a means to communicate with other logic elements in the system. The unique identifier enables greater system flexibility, thereby reducing cost and improving efficiency.

Abstract: The present invention relates to a counter circuit and method of controlling such a counter circuit, wherein a first counting section counts in accordance with a state-cycle, and a second counting section is clocked by the first counting section. At least one invalid counting state is introduced by controlling the second counting section to change its state before the first counting section has completed the state-cycle; and the at least one invalid counting state is then detected and corrected. Thereby, some redundancy is introduced in the counter, which can be used to detect and correct incomplete switching of counter states.

Abstract: A method and a circuit for detecting a malfunction of at least one first counter controlled by a first signal, in which a second counter, controlled by a second signal identical to the first signal or to its inverse, and counting in the reverse direction with respect to the first counter, is set with a value complementary to a setting value of the first counter; the respective current values of the first and second counters are added up; and the current sum is compared with at least one value representing the greatest one of the setting values or this greatest value plus one.

Abstract: An asynchronous counter that is capable of switching count mode includes flip-flops, and three-input single-output tri-value switches respectively provided between the adjacent pairs of the flip-flops. The tri-value switches switch among three values, namely, non-inverting outputs and inverting outputs of the flip-flops and a power supply level. Each of the tri-value switches switch among the three input signals according to two-bit control signals, and input a selected signal to a clock terminal of a subsequent flip-flop. When count mode is switched according to the control signals, a count value immediately before the mode switching is set as an initial value, and counting after the mode switching is started from the initial value.

Abstract: A self test for a counter system in an integrated circuit includes a clock coupled to counters in a plurality of counters. A first counter in the plurality of counters has a first counter output and a first counter rollover. A second counter in the plurality of counters has a second counter output, a second counter rollover less than the first counter rollover, and a second counter rollover signal that is active when the second counter has rolled over. A comparison circuit having inputs coupled to the first and second counter outputs, compares the first and second counter outputs to produce a counter error output signal. A latch latches the counter error output signal in response to the second counter rollover signal being inactive and the counter error output signal indicating a difference in the first and second counter outputs. Counters may be segmented to reduce a number of digits.

Abstract: A fault state detector for a ring counter is formed from unit current sources each switched under the control of a different one of the outputs of the ring counter. The currents switched in that manner are passed through a unit resistance to generate a voltage signal proportional to the number of asserted outputs from the ring counter. The voltage signal is compared to boundary reference values for valid states of the ring counter outputs and, if the voltage signal is not between the boundary reference values, a fault state is indicated.

Abstract: The present invention discloses wave frequency calibration method and device for remote controller, the device of the present invention comprises an oscillator for generating a base wave; a storage for storing a match value; a modifier for generating a modified signal; and a processor connected to the oscillator, the storage and the modifier, the processor change the match value until the modified signal disappear and store the most updated match value in the storage to assure the receiving end of the remote controller can receive the signal with correct frequency. Incorporating with a RC oscillator, the wave frequency calibration method and device for remote controller of the present invention will avoid the problem of the bias of wave, which enables the RC oscillator to be a oscillator that can be used commonly in a regular remote controller.

Abstract: A ripple counter circuit supports two modes of operation, a user mode and a test mode. In the user mode, the circuit functions as a standard ripple counter, counting in response to first edges (e.g., rising edges) on a clock input signal. In the test mode, the ripple counter circuit alternates between two states. In the first state, the bits all toggle from their initialization values to new values. In the second state, the circuit operates in the same fashion as the user mode. Therefore, the ripple counter circuit counts by one, returning all of the bits to their initialization values. This capability significantly simplifies the testing process, particularly for long ripple counters. Some embodiments of the invention include various control circuits coupled to provide an internal clock signal and/or an initialization signal.

Abstract: The invention provides an electrooptic device and an electronic apparatus, in which the electrical characteristics of many thin-film switching elements formed in a substrate to support an electrooptic material can be accurately inspected. The invention also provides a method for making the electrooptic device. In a TFT array substrate of a liquid crystal device, an inspection TFT is formed in one of dummy pixels disposed at the periphery of a pixel region. A pixel electrode connected to a drain region of the TFT functions as a first inspection pad. In an adjacent dummy pixel, the pixel electrode electrically connected to an extended portion of a data line functions as a second inspection pad. In another adjacent dummy pixel, the pixel electrode electrically connected to an extended portion of a scan line via a junction electrode functions as a third inspection pad.

Abstract: An apparatus comprises an edge detector, a memory and a pulse-input engine. The edge detector is configured to receive an input signal and a counter signal. The edge detector is further configured to send a set of time values based on the input signal and the counter signal. Each time value from the set of time values is uniquely associated with a detected edge transition from the input signal. The memory is coupled to the edge detector. The memory is configured to receive from the edge detector the set of time values. The memory is configured to store the set of time values. The pulse-input engine is coupled to the memory. The pulse-input engine is configured to measure a set of pulse-to-pulse delays based on the set of the time values stored in the memory.

Abstract: A measurement system and method for determining a revolution rate of a rotating gear is described. Such a rotating gear can be, for example, a turbine or compressor. The described measurement system and method, for example, can perform highly accurate measurements and can be a fault tolerant system providing high reliability. In one embodiment, an apparatus comprises an edge detector, a memory and a pulse-input engine. The edge detector is configured to receive an input signal and a counter signal. The edge detector is further configured to send a set of time values based on the input signal and the counter signal. The pulse-input engine is configured to measure a set of pulse-to-pulse delays based on the set of time values stored in the memory.

Abstract: There is described a method and system for calibrating measurements, in particular for calibrating a high resolution counter against an accurate real time calibrated clock signal. The method comprising obtaining the calibrated low resolution clock measurement and the corresponding high resolution counter measurement and calculating a range of possible corrections to the counter measurement to align it with the clock measurement. The correction range is adjusted to make it consistent with a previously stored correction range and a value is taken from it to calibrate the counter measurement. If the calculated range and the stored range are inconsistent then only the calculated range is used. A further measurement of the clock or counter is taken to double check.

Abstract: An integrated circuit includes an n-bit counter having a plurality of k subcounters where both n and k are integers. At least one of the subcounters includes a switchable device adapted to receive a carry-out signal from an adjacent subcounter as a first input, a test carry signal as a second input, and a control input, the switchable device being capable of providing one of its inputs as an output, the control input capable of controlling selection of the output which is a carry signal. The subcounter also includes an n/k-bit counter, the n/k-bit counter receiving the carry signal and providing n/k output bits, and logic for combining the n/k-bits output from the n/k bit counter with the carry-out signal from an adjacent subcounter to provide an output that is a carry-out signal from the subcounter. The logic introducing a single gate delay between the carry-out signal from the adjacent subcounter and the carry-out signal from the subcounter.

Abstract: A low power scannable asynchronous counter which is fully testable and which consumes low power in a functional mode consists of counter cells cascaded through NOR gate circuits to which clock signals are applied for each of the stages or cells. Each of the stages or cells comprises a flip-flop and a multiplexer which together operate as a toggle flip-flop only when all of the previous flip-flops are set. The result is that the flip-flop clock is forced high preventing any transition of the flip-flop internal clock tree for all stages or cells where the output is low. Thus, no power consumption of such stages takes place during functional operation. In the scan test mode, the counter operates as a shift register and it is fully testable.

Abstract: A reference clock signal oscillator generates a reference clock signal. A first programmable counter performs frequency dividing on the reference clock signal and outputs a reference signal resulting-from the frequency dividing. A voltage controlled oscillator generates an output clock signal, the frequency of which is controllable by input voltage control. A second programmable counter performs frequency dividing on the output clock signal and outputs a feedback signal resulting from the frequency dividing. A phase comparator compares the reference signal and the feedback signal, and outputs a phase difference signal which is based on the phase difference between the phases of the reference signal and the feedback signal. A driving circuit includes a charge pump and a loop filter and generates a signal to be applied to the voltage controlled oscillator based on the phase difference signal and performs filtering on the signal to be applied to the voltage controlled oscillator.

Abstract: A system for testing a digital counter of mn stages, in which the counter is organized into m segments, each of n bits, includes a two input exclusive OR gate connected between each of the m segments. One of the two inputs of each exclusive OR gate is obtained from the carry output of a lower order one of the m segments, and the output of each exclusive OR gate is connected to the carry input of the next higher order one of the m segments. The other inputs to the exclusive OR gates are obtained from a test signal enable input, which is driven high (binary "1") for the test mode of operation. The counter is fully exercised in the test mode in a parallel operation, with full testing of the carry bits from one segment to the next, without any interruption in the clock signal input stream.

Abstract: A method and system for testing a digital counter of mn bits comprises dividing the counter into m segments, each of n bits. For test purposes, the counter then is further divided into first and second m segment groups. Multiplex gates are used between the segments and are controlled by sensing the condition of the most significant bits of the most significant one of the m segments for applying clock pulses to verify specific connections between various bits of the counter for the first four cycles of clock pulses applied during the test mode. After these four cycles, gating circuits coupled with the most significant bits of the most significant one of the m segments are used to automatically switch the remainder of the test connections to the second group to verify all of the remaining connections in the counter, with full testing of the counter being accomplished in 2.sup.n +2 cycles of clock pulses.

Abstract: A method and circuit for selectively scaling a binary counter having N serially connected stages in which an output count from the counter is 2.sup.M times the number of clock signals that have been input to the counter. The first M stages of the counter are selectively held so that clock signals by-pass (or pass through) the first M stages without change. The M+1 stage receives each clock signal and is thereby caused to indicate that 2.sup.M clock signals have been received, when only one clock signal has, in fact, been received. The output of each stage is provided to a decoder array that provides the scaled count signal. The method and circuit find application in systems in which normal unscaled operation of the binary counter may be selectively replaced with high speed operation, such as during tests or during special operating modes. The circuit and method obviate the need for a separate high speed clock, or for adaptive circuitry in the decoder array.

Abstract: A decoded counter employing a shift register and a zero-detect circuit has the ability of returning to a correct state within a limited number of clock cycles if an invalid state is accidentally assumed by the counter. One of the flip-flops is provided with synchronous set while all the other flip-flops of the shift register are provided with synchronous reset. The output of the last flip-flop of the register drives a single set-reset line common to all the flip-flops and the pull-up line of the zero-detect circuit is connected to the input of the first flip-flop of the register. Optionally, one of the flip-flops may be provided with asynchronous set and the others with an asynchronous reset, for initializing the counter in a certain state through a single clear-load line.

Abstract: An n-bit counter (18) (where n is an integer.gtoreq.1) may be tested by first reconfiguring the counter during a test mode to generate successive first and second half-counts when the counter is successively clocked. During the test mode, a logical equality comparator (70) compares the half-counts to each other. When the half-counts are unequal (signifying a counter fault), the counter is inhibited from further counting. In this way, the counter is advantageously frozen at the faulty value. When the counter is inhibited from counting, its carry bit (CO) no longer toggles. Thus, by examining the counter carry bit, an indication can be had whether the counter is operating properly during the test mode.

Abstract: In an apparatus for testing a counter circuit, a test pattern is used to drive the counter circuit to obtain an output pattern. The output pattern is compared with an expected pattern in synchronization with the test pattern, thereby determining whether or not the counter circuit is normal. A phase between the output pattern and the expected pattern is initially adjusted by the testing apparatus.

Abstract: An N stage counter includes peripheral circuitry for testing the operability of the counter. The peripheral circuitry includes gating means coupled between certain stages of the counter for partitioning the counter into at least first and second counter sections during a testing mode. During the testing mode, the N counter stages are reset to an all zero condition and this resettability capability is detected. During the testing mode, the N counter stages are also set to a predetermined value and the settability of the counter stage to a non-zero condition is also detected. During one phase of the testing mode, the first section counts a predetermined number of clock cycles while all counts produced at the outputs of all the stages of the second section are totalled in a register means. During another phase of the testing mode, the second section counts a predetermined number of clock cycles while all the counts produced at the outputs of all the stages in the first section are totalled in the register means.

Abstract: Test circuitry for a counter of n number of bits is described. The circuitry includes that which divides the counter into s number of segments when the counter is being tested in a test mode. The invention also includes circuitry for detecting when each segment nears the last count and overriding test mode to reenable a between-segment clock path between the segments before the last count to permit the last count to ripple through the counter to test connections between the segments on the next clock cycle. Previous test implementations did not test the interface between segments because of the prohibitive cost in tester time. In one embodiment, assuming equal numbers of b bits per segment, to fully test a counter using previous techniques, 2.sup.(n-b) +2.sup.b clock cycles would be required. In this technique, only (s-2)+2.sup.b clock cycles are required.

Abstract: A new technique for testing the counting functionality, loading functionality, and operational speed of a binary counter is provided wherein additional logic is incorporated into the counter to enable the counter to be functionally tested with a minimum number of clock cycles. Thus, for an n-bit counter which is partitionable into k subcounters, the counting functionality and operational speed of the counter may be tested in at most 2.sup.n/k +2 clock cycles, and the loading functionality of the counter may be tested in at most 2.sup.n/k +1 clock cycles.

Abstract: A counter circuit includes counting stages of n bits where n is a natural number. The counter circuit also includes a logic decoding circuit for determining the inputs of the counting stages, a logic circuit for adjusting the number of simultaneous changes so that the number of simultaneous changes of the logic decoding circuit can be made uniform, and a logic circuit for adjusting the load capacitance of the counting stages so that the load capacitance can be made uniform. The counter circuit may also include a test logic circuit for creating a test wave form on the basis of the outputs from the logic circuits for adjusting the number of simultaneous changes and the logic circuits for adjusting the load capacitance. Accordingly, it is possible to detect a failure of the logic circuits for adjusting the number of simultaneous changes and the logic circuits for adjusting the load capacitance which does not effect the counting output.

Abstract: A counter circuit includes a plurality of one-bit counters connected in series. The counter circuit includes first and second input terminals which are supplied with a predetermined signal, respectively, in an operational test mode. The counter circuit further includes a unit for alternately supplying a carry signal to a carry signal input of each one-bit counter in series when the predetermined signals are applied thereto. The unit may be composed of a plurality of OR circuits. Each OR circuit is provided with one input connected to the carry signal output of a one-bit counter at the preceding stage of the series, the other input connected to either the first input terminal or the second input terminal, and an output connected to the one-bit counter at the next stage.

Abstract: A high resolution counter circuit measures the time interval between the occurrence of an initial and a subsequent electrical pulse to two nanoseconds resolution using an eight megahertz clock. The circuit includes a main counter for receiving electrical pulses and generating a binary word--a measure of the number of eight megahertz clock pulses occurring between the signals. A pair of first and second pulse stretchers receive the signal and generate a pair of output signals whose widths are approximately sixty-four times the time between the receipt of the signals by the respective pulse stretchers and the receipt by the respective pulse stretchers of a second subsequent clock pulse. Output signals are thereafter supplied to a pair of start and stop counters operable to generate a pair of binary output words representative of the measure of the width of the pulses to a resolution of two nanoseconds.

Abstract: A calibration generator for furnishing signals to tachographs, taximeters and other instruments used in fleet management systems. Calibrated frequencies and amplitudes are provided by the generator of the invention. A PLL controlled synthesizer, driven by a crystal oscillator, supplies frequencies under control from the operator. An alternative continuously controlled oscillator is also available for tests.

Abstract: A high speed digital counter that can be easily tested comprises a plurality of subcounters having an input for receiving an incrementing signal and a carry output for outputting a carry signal when the subcounter has reached its counting capacity. The carry output of each subcounter is gated to the input of a next more significant subcounter by an OR gate which receives as inputs the carry signal and a test signal. The OR gate performs an OR on these two signals and outputs the result to the input of the next more significant subcounter. The OR gate allows the test signal to access each subcounter separately, and thus, each subcounter may be tested individually.

Abstract: A process and apparatus for calibrating a particle counter is described. The process comprises the steps of forming a vector gas flow by an aerosol of particles of the same grain size, developing ions in the vector gas with both sign by a bipolar charger, certain particles being electrically charged to a stationary charge state in which the distribution of the number of charges fixed to each particle follows a Gaussian law (Gunn or Boltzmann), passing the charge aerosol into a mobility selector to attract the charged particles to electrodes therein and classify them as a function of the numbers p of their elementary electrical charges e and allowing the electically neutral particles to escape, collecting the neutral particles and passing the neutral particles into the particle counter to be calibrated, the particles counter displaying a value N'.sub.o ; counting the values of N.sub.p and N.sub.

Abstract: This invention relates to a method of testing an n-bit programmable counter. It is desired to test the n-bit programmable counter in fewer than 2.sup.n cycles. Accordingly, a counter value output on the counter is coupled to a variable increment rate input on the counter. Each bit of the counter is reset to a binary 0 initial state. A binary 1 state is loaded into a carry-in bit of the counter and the counter is iteratively doubled, by means of the coupling between the counter value output and the variable increment rate input, until a carry-out bit of the counter assumes the binary 1 state to thereby allow the counter to be fully tested in n+1 iterations. The counter value output and the variable increment rate input are decoupled from the counter when the counter is not being tested. The counter is provided with a parallel load input to allow simultaneous resetting of each bit. Intermediate counter values may be checked to provide a means for localizing errors within the counter.

Abstract: A hubodometer (10) for attachment to a vehicle's wheel structure for sensing a rotation of the wheel structure and for converting the sensed rotation to a distance travelled. The hubodometer comprises an outer housing (12) having a permanent magnet (28) affixed thereto for generating a magnetic field and a coupler (14) for coupling the housing to the wheel structure such that the outer housing rotates therewith. The hubodometer further comprises an anti-rotation mechanism (16) rotatably coupled within the outer housing, the mechanism having a plurality of components (18,20,22,24,30) coupled thereto, the components being stabilized against rotation thereby. The components include an electronic controller (20) and a plurality of magnetic field sensors (30). The plurality of sensors are disposed relative to the housing such that as the magnet rotates thereabout all of the plurality of magnetic field sensors do not simultaneously sense the magnetic field.

Abstract: A counting device determines the number of similar articles, or parts, passing a detector. The device is especially useful in packaging small parts into containers, and in insuring that each package contains the correct number of parts. The counter is preferably of the type in which the parts interrupt a beam of light, changing the current through a photoelectric cell. When the current in the photoelectric cell falls below a predetermined threshold level, the device generates a pulse which indicates the presence of a part. The pulses are counted electronically. The device preferably includes a microprocessor which can efficiently control the counting, calibration, and diagnostic operations. The microprocessor stores information relating to the threshold current level, for a given type of part. The value of the threshold can be determined by a separate calibration procedure.

Abstract: A multi-stage M-bit binary counter is disclosed including S counter stages in which each counter stage includes an N-bit counter (M=S.times.N). During a test operation, the stages are decoupled for individual operation, a count value is loaded into the N-bit counter provided in each of the stages, and the N-bit counters of each stage are clocked 2.sup.N times to check independently the function of the N-bit counters. The stages are then coupled together to function as a multi-stage M-bit counter and a single clock pulse is supplied to the M-bit counter to check the carry propagation between stages. If the N-bit counters are of a type which only generate an output when fully incremented or decremented and the actually count value cannot be read from the M-bit counter, then the stages are decoupled together for a second time and the N-bit counters are clocked an additional 2.sup.N times.

Abstract: A method and apparatus for testing operation of an n-bit counter with carry inputs in an electronic system. The n-bit counter is divided into a high section and a low section. An external carry is forced to the lowest significant bit of the high section. All states of both sections of the counter are clocked, each state of each of the sections being clocked simultaneously with a corresponding state of the other of the sections. The natural carry is selected so that, at the next clock cycle, when the low section is set at the highest count, the highest significant bit of the low section is carried to the lowest significant bit of the high section.

Abstract: The fault monitoring function of an executive monitor contained in a microwave landing system is verified by evaluating a history of the parametric information sampled by an executive monitor and storing in memory the number of out of tolerance parametric signals received from an antenna means over a predetermined time period, replacing the stored number of out-of-tolerance parametric signals with a predetermined number that will be beyond a second predetermined limit if another out-of-tolerance parametric signal is added to said number, adding one such internally generated out-of-tolerance parametric signal to said predetermined number, generating an alarm if said sum is beyond the second predetermined limit, and restoring the previously stored number of out-of-tolerance parametric signals received from the antenna means if the alarm was generated, and shutting the system down if an alarm was not generated.

Abstract: An iterative and continuous normalizer for ensuring that the ejector rate of the slave channels in a fungible product sorter are operating at the same rate as a channel selected as the master channel. A distributed trip level value applied to a master channel comparator results in a rate of ejection of non-standard products that are counted to a predetermined count, at which time a master channel counter output is produced. In similar fashion, a slave channel output is produced; however, the comparator in the slave channel operates to an adjusted trip level value, which is the distributed trip level value adjusted by a multiplying factor. This multiplying factor is produced by a multiplier controlled by an up/down counter, in turn controlled up or down by whether the slave channel counter output or master channel counter output arrives first.

Abstract: A look ahead terminal counter and a method for generating a terminal count output signal are disclosed. The counter comprises a plurality of counter registers connected to counter enable circuitry for sequencing the registers at a predetermined counter rate. Terminal count enable circuitry is connected to the counter circuitry, e.g. at the input ports of the counter registers, and is operative to generate a terminal count enable signal when those input ports are at a predetermined state. The terminal count enable signal and clock signal are communicated to an output register operative to generate a terminal count output signal when a clock signal is received during the simultaneous presence of the terminal count enable signal.

Abstract: A register of the type used on as address counter in a dynamic RAM is tested by a method which does not require cycling through every possible value of the register contents. The counter is first loaded with a fixed value, all 1's or all 0's, and the contents checked by an AND or OR gate, producing a one-bit output which is monitored off-chip. Then, the carry feedback path to the counter register is altered, as by inverting all but the LSB, and the contents again checked, using the one-bit output via the AND or OR. In this manner, the operation of the counter is tested in three cycles.

Abstract: A multi-mode counter network and a method of testing the operation of the multi-mode counter network are disclosed. The multi-mode counter network comprises a counter circuit formed of a plurality of counter registers and a multiplexer circuit formed of a plurality of multiplexers wherein said multiplexers are connected to and associated with one of the registers and are operative to selectively vary the input signal communicated to the associated register such that the registers operate in one of a plurality of operational modes. By controlling the selection of the input signal communicated to the registers the network may be alternately configured to perform traditional counting functions or may be configured to provide a serial signal path for communicating a test pattern through the registers and multiplexers to test the operation of the multiplexers and registers. The test pattern is communicated through the circuit, bypassing counter enabling circuitry, and thus independent of the network counter rate.

Abstract: A logic circuit having a test data loading function, comprising at least one J-K flip-flop. Each J-K flip-flop includes a test data latching logic circuit. In response to an enable signal, test data is selected in place of the usual J and K input data to be latched. In a complex logic circuit including such flip-flops, a test can be effected in a short time.

Abstract: Basic block shift registers are cascaded to form a fully programmable linear feedback shift register. Each of the basic block shift registers comprises a plurality of flip-flops, each of which includes control logic circuits. A polynomial equation is first fed into the linear feedback shift register for setting the respective flip-flops into predetermined logic states, which are used to encode messages to be shifted by the programmable linear feedback shift register. The number of flip-flops in the programmable linear feedback shift register can be varied, in accordance to the polynomial equation. Likewise, the polynomial equation also determines the number of times the programmable linear feedback shift register is to circulate the encoded messages.

Abstract: A digital integrated circuit incorporates a plurality of multi-port flip-flop circuits which are interconnected by a plurality of gate circuits. A separate source of clock pulses is provided for each of the ports of the multi-port flip-flop circuits, and each clock pulse source is selectively effective to cause the multi-port flip-flop circuits to perform independent functions. During operation under one source of clock pulses, the flip-flops perform their ordinary function as D type flip-flops. During operation under another source of clock pulses, the flip-flops function as one or more shift registers in order to set the flip-flops to a predefined initial state in accordance with serial input data, and/or to provide serial output data in response to the state of the flip-flops following a preceding operation.

Abstract: An electronic integrator for integrating a linear voltage signal utilizes a voltage-to-frequency converter for converting the voltage to input frequency. A binary counter counts pulses of the input frequency. The binary counter generates a first operating frequency which is applied to a scaling circuit and another calibration frequency which has a much higher rate than the operating frequency. Both, however are proportional to the input frequency. The scaling circuit scales the operating frequency to a selected extent to form a counting signal. Using the double pole switch, either the calibration frequency or the counting frequency are applied to a pulse counter which is either used to integrate the input voltage signal by counting up pulses of the scaled counting signal, or the integrator can be calibrated using the calibration frequency which quickly increments the pulse counter.

Abstract: A testable time delay apparatus includes means for testing component operation during any stage of system function and means for continuously monitoring and testing component functions. The device is particularly useful in critical process control applications such as in a nuclear reactor control system.