Identifying Or Correcting Improper Counter Operation (e.g., Error Checking, Monitoring; Preventing Or Correcting Improper Counter Operation) Patents (Class 377/28)
  • Patent number: 10838794
    Abstract: A fault detection circuit includes a system controller and a fault detection controller. The system controller includes at least one memory device to control at least one electrical system. The fault detection controller communicates with the system controller to detect at least one fault of the system controller and to control operation of the system controller based on comparison between a frequency of detected faults corresponding to the system controller and at least one frequency threshold value.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: November 17, 2020
    Assignee: HAMILTON SUNSTRAND CORPORATION
    Inventor: Lon R. Hoegberg
  • Patent number: 9760438
    Abstract: A data storage apparatus is provided which has a plurality of data storage units, each respective data storage unit configured to store a respective data bit of a data word. Stored data value parity generation circuitry is configured to generate a parity bit for the data word in dependence on the data bits of the data word stored in the plurality of data storage units. The stored data value parity generation circuitry is configured such that switching within the stored data value parity generation circuitry does not occur when the data word is read out from the plurality of data storage units. Transition detection circuitry is configured to detect a change in value of the parity bit.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: September 12, 2017
    Assignee: ARM Limited
    Inventors: Vikas Chandra, Robert Campbell Aitken
  • Publication number: 20140098927
    Abstract: Disclosed is a apparatus and method for detecting a cut-off frequency of a pulse signal, the apparatus including an input processor configured to generate a second pulse signal at a time when a rising edge and a falling edge of a first pulse signal appear, in a case the first pulse signal, which is a pulse signal of a monitoring object, is inputted, a counter configured to count a clock signal relative to the second pulse signal generated by the input processor, a reset processor configured to reset the counter at every predetermined (set) period, and a detector configured to generate and output a cut-off frequency of a detection signal, in a case an output value of the counter exceeds a predetermined (set) threshold during the predetermined period.
    Type: Application
    Filed: August 23, 2013
    Publication date: April 10, 2014
    Applicant: LSIS CO., LTD.
    Inventor: Kang Hee PARK
  • Patent number: 8644447
    Abstract: A digital frequency divider including a parallel output register, a presettable asynchronous counter and a decoder. The parallel output register contains a desired count value. The presettable asynchronous counter has its preset data inputs coupled to the output of the parallel output register. The decoder receives its input from the data outputs of the presettable asynchronous divider and its output coupled to the load input of the presettable asynchronous counter.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: February 4, 2014
    Assignee: STMicroelectronics International N.V.
    Inventors: Chandra Bhushan Prakash, Balwinder Singh Soni
  • Publication number: 20110293062
    Abstract: A sequence generator implemented on a receiver is synchronized with a sequence generator at a transmitter. The receiver receives k n-state symbols, with k>1 and n>1 wherein each of the k n-state symbols is associated with a generating state of the sequence generator at the transmitter. A processor in the receiver evaluates an n-state expression that generates an n-state symbol that is associated with a synchronized state of the receiver. Coefficients related to the n-state expression are stored on a memory and are retrieved by the processor. The synchronized state in one embodiment is part of a code hop. The sequence generator in the receiver may be part of a descrambler, of a communication device, of a data storage device and/or of an opening mechanism.
    Type: Application
    Filed: May 31, 2011
    Publication date: December 1, 2011
    Applicant: Ternarylogic LLC
    Inventor: Peter Lablans
  • Patent number: 8032674
    Abstract: A method for maintaining flow control in a buffer memory coupled to a storage controller is provided. The storage controller includes, first and second counters that are used to monitor when data is read from a buffer memory and when data is transferred from the buffer memory to the host. The method includes, incrementing first and second counter values when data is placed in the buffer memory; decrementing a first counter value when data is read from the buffer memory; and decrementing the second counter value when data is sent to a host. The method further includes, pausing a first channel logic between a transport module and a storage disk when there is no data in the buffer memory; and pausing a second channel logic between a disk and the buffer if there is no space in the buffer memory.
    Type: Grant
    Filed: July 19, 2004
    Date of Patent: October 4, 2011
    Assignee: Marvell International Ltd.
    Inventors: Kha Nguyen, William C. Wong, Mouluan Jang, Jane X. Wang
  • Patent number: 8014487
    Abstract: A counter circuit and method of controlling such a counter circuit, including a first counting section that counts in accordance with a state-cycle, and a second counting section clocked by the first counting section. At least one invalid counting state is introduced by controlling the second counting section to change its state before the first counting section has completed the state-cycle; and the invalid counting state is then detected and corrected. Thereby, some redundancy is introduced in the counter, which can be used to detect and correct incomplete switching of counter states.
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: September 6, 2011
    Assignee: NXP B.V.
    Inventor: Remco C. H. Van De Beek
  • Patent number: 7894961
    Abstract: A dump cycle counting system is provided for a work machine. The system may include a payload carrier configured to contain a payload of material and a dump actuator configured to effectuate dumping of the payload out of the payload carrier. The system may also include a controller configured to control actuation of the dump actuator and a dump control device operatively coupled to the controller. The system may further include a load counter configured to record at least one dump cycle based on a command state of at least one of the dump control device and the controller.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: February 22, 2011
    Assignee: Caterpillar Inc
    Inventors: Mark Robert Blackburn, Robert Todd, Roger Tansley
  • Patent number: 7869558
    Abstract: Timing circuitry may use control circuitry to control calibration circuitry to calibrate a counter so that an adder and a calibration period counter are not required. Concatenation circuitry may be used to concatenate a portion of the counter value and the calibration value to provide a calibrated value to the counter. The results from match circuitry may be used to provide status and control information to a calibration history bit and to an enable circuit. The counter may be an up counter or a down counter.
    Type: Grant
    Filed: May 12, 2009
    Date of Patent: January 11, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Evgeni Margolis
  • Patent number: 7738621
    Abstract: A counter with overflow prevention capability includes a counting unit configured to count an output code in response to an input signal and an overflow preventing unit configured to control the counting unit to stop counting the output code when a current value of the output code is a maximum value but a previous value thereof is not the maximum value.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: June 15, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Dae-Kun Yoon, Kyung-Hoon Kim, Dae-Han Kwon, Taek-Sang Song
  • Patent number: 7735031
    Abstract: A system that includes a controller for enabling an enumeration operation. The enumeration operation is performed by a controller (110) and logic elements (120) in a system, such that each logic element in the system assigns itself a unique identifier. Each logic element can then be controlled by another source or have a means to communicate with other logic elements in the system. The unique identifier enables greater system flexibility, thereby reducing cost and improving efficiency.
    Type: Grant
    Filed: August 20, 2007
    Date of Patent: June 8, 2010
    Assignee: International Business Machines Corporation
    Inventors: Valerie Hornbeck Chickanosky, Kevin William Gorman, Emory D. Keller, Michael Richard Ouellette
  • Patent number: 7688932
    Abstract: A method and a circuit for detecting a malfunction of at least one first counter controlled by a first signal, in which a second counter, controlled by a second signal identical to the first signal or to its inverse, and counting in the reverse direction with respect to the first counter, is set with a value complementary to a setting value of the first counter; the respective current values of the first and second counters are added up; and the current sum is compared with at least one value representing the greatest one of the setting values or this greatest value plus one.
    Type: Grant
    Filed: January 9, 2008
    Date of Patent: March 30, 2010
    Assignee: STMicroelectronics SA
    Inventor: Philippe Roquelaure
  • Patent number: 7684957
    Abstract: A counting device includes a counting unit, period measuring unit, frequency distribution unit, representative value unit, and correction value unit. The counting unit counts signals input during an interval. The signals have a single frequency when the physical quantity is constant. The period measuring unit measures the period of a signal interval. The frequency distribution unit generates the frequency distribution of signal periods from the measurement result. The representative value unit calculates the representative value of the distribution of periods from the frequency distribution. The correction value unit obtains a total sum Ns of frequencies in a class not more than a first predetermined multiple of the representative value and a total sum Nw of frequencies in a class not less than a second predetermined multiple of the representative value from the frequency distribution, and corrects the count result on the basis of the frequencies Ns and Nw.
    Type: Grant
    Filed: January 24, 2008
    Date of Patent: March 23, 2010
    Assignee: Yamatake Corporation
    Inventor: Tatsuya Ueno
  • Patent number: 7664220
    Abstract: An interlocked counter including a synchronous counter, a logic gate for judging end-value, a logic gate for amplifying an interlocking signal, at least one latch circuit for the interlocking signal, a logic gate for the interlocking signal, and a logic gate for an enable signal, wherein behavior of the synchronous counter is stopped when a count number arrived at an end value, by that the synchronous counter counts a number of pulses of a clock signal when the synchronous counter inputted an enable signal, the logic gate for judging end-value generates an interlocking signal when the count number outputted by a synchronous counter coincided with the end value, the logic gate for amplifying interlocking signal amplifies the interlocking signal in order to output to an external part, and the logic gate for enable signal generates the enable signal when the interlocking signal is not generated.
    Type: Grant
    Filed: July 17, 2007
    Date of Patent: February 16, 2010
    Assignee: Ecchandes Inc.
    Inventor: Yoshiaki Ajioka
  • Publication number: 20090238323
    Abstract: A real time clock comprises a counter which stores a count value, the count value representing a time signal. The counter may be written, for example by a host processor (not shown), such that the time signal can be set to any desired value. The real time clock comprises a check register that stores a check value. The content of the check register (i.e. the check value) is modified each time a write operation is performed on the counter. For example, the content of the check register can be updated by a control signal each time a write operation is performed on the counter. The check value stored in the check register is used for determining whether a write operation performed on the counter is an authorized write operation or an unauthorized write operation. The check value may be incremented each time a write operation is performed, replaced with a new random number each time a write operation is performed, or a combination of both.
    Type: Application
    Filed: May 8, 2008
    Publication date: September 24, 2009
    Inventors: Holger Haiplik, Clive Robert Graham
  • Patent number: 7573969
    Abstract: A counting device includes a set of memory cells, which are configured to store respective bits of a count code. A controller is coupled to the memory cells so as to increment, in response to occurrences of a count input, the count code in the set of the memory cells from an initial value up to a preset bound in each of a plurality of successive iterations, and to shift the bits of the count code that are respectively stored in the memory cells in each of the iterations relative to a preceding iteration.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: August 11, 2009
    Assignee: Sandisk Il Ltd.
    Inventors: Eran Shen, Rotem Sela, Aviad Zer, Oren N. Honen, Ido Shilo
  • Patent number: 7526059
    Abstract: A counting device includes a set of memory cells, including multiple groups of the memory cells configured to store count words of a count code, which include a less significant word and a more significant word. A controller assigns first and second groups of the memory cells to store the less significant word and the more significant word. The controller increments the less significant word from an initial value up to a first limit in each plurality of successive first iterations and increments the more significant word from an initial value up to a second limit in each of a plurality of successive second iterations in response to reaching the first limit. Upon reaching the second limit, the controller makes a new assignment of the groups of the memory cells that are to store the less significant word and the more significant word.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: April 28, 2009
    Assignee: Sandisk IL Ltd.
    Inventors: Eran Shen, Boris Dolgunov
  • Publication number: 20080317189
    Abstract: The output bits of a binary ripple counter are used to control the sampling of those output bits, thereby ensuring accurate sampling. A sampler is provided with adjustable delay elements that permit accurate sampling regardless of: delay mismatch between the sampler and a data path of the counter; the length of the counter; operating speed; or PVT variations.
    Type: Application
    Filed: June 20, 2008
    Publication date: December 25, 2008
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jingchen Zhuang, Robert Bogdan Staszewski
  • Publication number: 20080247500
    Abstract: In order to provide an IF counting method for realizing an IF counter with a smaller circuit configuration, an IF counter comprises a countdown IF counting unit 1 for counting frequency-divided IF signals, an IF count time period determination unit 2 for determining a count time period, an IF count upper limit presetting unit 3 for providing the countdown IF counting unit 1 with an initial value, a lower-order m-bit comparison unit 5 for comparing the lower-order m bits of the value counted by the countdown IF counting unit 1 with information preset in the IF count upper/lower limit difference presetting unit 3 and a determination unit 6 for determining whether the count value is within a prescribed range, according to the higher-order (n+1?m) bits of the value counted by the countdown IF counting unit 1 and the comparison result of the lower-order m-bit comparison unit.
    Type: Application
    Filed: January 7, 2005
    Publication date: October 9, 2008
    Applicant: Kabushiki Kaisha Toyota Jidoshokki
    Inventors: Shigetaka Goto, Hiroshi Miyagi
  • Publication number: 20080181354
    Abstract: A counting device includes a counting unit, period measuring unit, frequency distribution generating unit, representative value calculation unit, and correction value calculation unit. The counting unit counts the number of signals input during a counting interval. The number of signals has a linear relationship with a physical quantity. The signals have a substantially single frequency when the physical quantity is constant. The period measuring unit measures the period of a signal every time a signal is input during the counting interval. The frequency distribution generating unit generates the frequency distribution of signal periods from the measurement result. The representative value calculation unit calculates the representative value of the distribution of periods of signals from the frequency distribution.
    Type: Application
    Filed: January 24, 2008
    Publication date: July 31, 2008
    Inventor: Tatsuya Ueno
  • Patent number: 7321651
    Abstract: A method, an apparatus, and a computer program are provided for generating an error detection state and correction of code patterns. Generally, conducting full speed testing of the dI/dt circuit in a low bandwidth lab environment is difficult. A circuit, however, can be employed that periodically detects the functionality of the dI/dt circuit to indicate success or failure. When errors are detected, the circuit allows for erroneous codes to be replaced with accurate ones. Using this circuit, conducting full speed testing of the dI/dt circuit in a low bandwidth lab environment can be more easily achieved.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: January 22, 2008
    Assignee: International Business Machines Corporation
    Inventors: David W. Boerstler, Eskinder Hailu, Jieming Qi
  • Patent number: 7154983
    Abstract: The present invention provides an overflow detector for a FIFO. The FIFO includes a plurality of registers each having an input and an output, a plurality of write signals each respectively coupled to a clock, one of the plurality of registers, and a plurality of read switches each respectively coupled to an output of one of the plurality of registers, each of the plurality of read switches being controlled by a respective read signal. The overflow detector includes a plurality of clocked registers each of which is coupled to receive a write signal and its corresponding read signal, wherein each clocked register records a read signal and is clocked by the corresponding write signal.
    Type: Grant
    Filed: November 1, 2002
    Date of Patent: December 26, 2006
    Assignee: Broadcom Corporation
    Inventor: Jun Cao
  • Patent number: 7120220
    Abstract: A non-volatile counter circuit includes a state machine having a first input for receiving one or more control signals, a second input for receiving a current count value, a third input for receiving historical information, and an output for providing a next count value and an up/down control signal, and a non-volatile counter having an input coupled to the output of the state machine, and an output for providing a non-volatile count value. The non-volatile counter can be implemented onto a single integrated circuit using ferroelectric memory technology. The non-volatile counter circuit includes a first power supply node and a second power supply node for receiving power for operating the non-volatile-counter circuit through a first power supply or a second power supply, or both. The first and second power supplies can be low energy power supplies such as that provided by a sensor, or can be conventional power supplies.
    Type: Grant
    Filed: December 23, 2004
    Date of Patent: October 10, 2006
    Assignee: Ramtron International Corporation
    Inventors: Xiao-Hong Du, Craig Taylor
  • Patent number: 7092479
    Abstract: Ripple counter circuits in integrated circuit devices can have fast terminal count capability. A terminal count circuit can be configured to mask selected unstable counter bits generated by a ripple counter circuit using an indication that a terminal state of the ripple counter circuit has been reached. Related methods are also disclosed.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: August 15, 2006
    Assignee: Integrated Device Technology, Inc.
    Inventors: David Reid, Timothy Gillespie
  • Patent number: 7085341
    Abstract: A nonvolatile counter. A nonvolatile storage is organized in digits having non-uniform bases. Circuitry is provided to increment a count value represented by the digits in response to an increment command.
    Type: Grant
    Filed: July 8, 2003
    Date of Patent: August 1, 2006
    Assignee: Intel Corporation
    Inventor: Steven E. Wells
  • Patent number: 6950490
    Abstract: A fault state detector for a ring counter is formed from unit current sources each switched under the control of a different one of the outputs of the ring counter. The currents switched in that manner are passed through a unit resistance to generate a voltage signal proportional to the number of asserted outputs from the ring counter. The voltage signal is compared to boundary reference values for valid states of the ring counter outputs and, if the voltage signal is not between the boundary reference values, a fault state is indicated.
    Type: Grant
    Filed: January 5, 2004
    Date of Patent: September 27, 2005
    Assignee: National Semiconductor Corporation
    Inventors: Yongseon Koh, Jitendra Mohan
  • Patent number: 6937688
    Abstract: A state machine, a counter, and related method for gating redundant triggering clocks according to the initial states is provided. The state machine includes a plurality of state units and a clock gating circuit. Each of the state unit is triggered by a clock to generate a corresponding varying state, and the clock gating circuit is capable of selectively withholding a triggering clock to at least one state unit according only to an initial state, such that the selected state unit(s) will not be triggered by the triggering clock while the rest of the state units are triggered by the triggering clock to update their corresponding states.
    Type: Grant
    Filed: December 5, 2002
    Date of Patent: August 30, 2005
    Assignee: VIA Technologies Inc.
    Inventors: Yung-Huei Chen, Shan-Ting Hong
  • Patent number: 6882697
    Abstract: A digital counter with a dial position having a hardware part which determines the n lowest-value bits of the dial position and a software part which determines the remaining higher-value bits of the dial position includes first and a second software parts as the software part with the dial position being a combination of the first software part and the hardware part when the hardware part is in a first counting range, and being a combination of the second software part and the hardware part when the hardware part is in a second counting range.
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: April 19, 2005
    Assignee: Tektronix International Sales GmbH
    Inventor: Holger Galuschka
  • Patent number: 6828817
    Abstract: The invention provides an electrooptic device and an electronic apparatus, in which the electrical characteristics of many thin-film switching elements formed in a substrate to support an electrooptic material can be accurately inspected. The invention also provides a method for making the electrooptic device. In a TFT array substrate of a liquid crystal device, an inspection TFT is formed in one of dummy pixels disposed at the periphery of a pixel region. A pixel electrode connected to a drain region of the TFT functions as a first inspection pad. In an adjacent dummy pixel, the pixel electrode electrically connected to an extended portion of a data line functions as a second inspection pad. In another adjacent dummy pixel, the pixel electrode electrically connected to an extended portion of a scan line via a junction electrode functions as a third inspection pad.
    Type: Grant
    Filed: January 22, 2003
    Date of Patent: December 7, 2004
    Assignee: Seiko Epson Corporation
    Inventor: Shin Fujita
  • Patent number: 6826249
    Abstract: Described are fast synchronous counters with reduced combinatorial logic. In one embodiment, a four-bit shift register is configured in a ring and preset with a data pattern (e.g., 1000). The register is then rapidly shifted into any of four unique states. Combinatorial logic connected to the shift register converts the four unique states into a two-bit binary signal representative of the four states. In the general case, counters in accordance with this embodiment represent N-bit binary numbers using 2N synchronous storage elements. Two or more counters can be combined to produce larger synchronous counters. An up/down counter in accordance with yet another embodiment is connected to a multi-path delay line to create a variable delay circuit. The switching speed of the delay circuit is independent of the number of delay settings. Also advantageous, the delay circuit scales linearly, in terms of power consumption and area, with changes in delay granularity.
    Type: Grant
    Filed: October 10, 2002
    Date of Patent: November 30, 2004
    Assignee: XILINX, Inc.
    Inventor: Ahmed Younis
  • Patent number: 6792065
    Abstract: A digital counter that uses non-volatile memories as storage cells, wherein the storage cells are sub-divided into two groups, one for the implementation of a rotary counter that keeps track of the less significant part of the count and a binary counter that keeps track of the more significant part of the count. The rotary counter implements a counting method that maximizes the count that can be obtained before the endurance limit of the memory is reached by making sure that each change of state of each cell is recorded as one count and that all cells in the rotary counter experience two change of state in every cycle. The binary counter records the number of cycles the rotary counter has gone through.
    Type: Grant
    Filed: January 21, 2003
    Date of Patent: September 14, 2004
    Assignee: Atmel Corporation
    Inventor: Kerry D. Maletsky
  • Patent number: 6704387
    Abstract: A method and apparatus for providing of normalizing a bit count is provided. The method comprises counting bits for a first frame, and normalizing a target bit in a target frame using the bits of the frame. The method then comprises counting to the normalized target bit in the target frame.
    Type: Grant
    Filed: September 11, 2001
    Date of Patent: March 9, 2004
    Assignee: Oak Technology, Inc.
    Inventor: Xiao Lin
  • Patent number: 6687325
    Abstract: A nonvolatile counter. A nonvolatile storage is organized in digits having non-uniform bases. Circuitry is provided to increment a count value represented by the digits in response to an increment command.
    Type: Grant
    Filed: June 23, 1999
    Date of Patent: February 3, 2004
    Assignee: Intel Corporation
    Inventor: Steven E. Wells
  • Patent number: 6661864
    Abstract: A counter circuit includes a plurality of flip flop circuits (FF circuits) sequentially connected for receiving a common clock signal, and two-input logic gates each having an input connected to an output of a corresponding FF circuit and the other input connected to an output of a common FF circuit, and of which output signal is supplied to an FF circuit positioned at the post stage of the corresponding FF circuit. A booby trap is realized by the two-input logic gates. The value input to each of the FF circuits is determined by logical operation of at most two logical values, so that the counter circuit can be adapted to the increasing frequency of a clock signal CLK. Thus, the counter circuit with the booby trap, capable of performing high-speed operation can be provided.
    Type: Grant
    Filed: August 15, 2001
    Date of Patent: December 9, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Masahiko Ishiwaki
  • Patent number: 6578161
    Abstract: A counting apparatus comprising an execution detection circuit for detecting the execution of a predetermined operation; plural memory circuits for commonly storing the information on the number of execution at each detection of the execution; a destruction detection circuit for detecting, at the storage of the information, whether the information stored in each memory circuit is destructed; and a correction circuit adapted, upon detection that the information of a memory circuit is destructed, to correct the destructed information with the information of another memory circuit.
    Type: Grant
    Filed: September 7, 1999
    Date of Patent: June 10, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hideto Kohtani, Tsuyoshi Muto
  • Patent number: 6519311
    Abstract: The present invention provides an overflow detector for a FIFO. The FIFO includes a plurality of registers each having an input and an output, a plurality of write signals each respectively coupled to a clock, one of the plurality of registers, and a plurality of read switches each respectively coupled to an output of one of the plurality of registers, each of the plurality of read switches being controlled by a respective read signal. The overflow detector includes a plurality of clocked registers each of which is coupled to receive a write signal and its corresponding read signal, wherein each clocked register records a read signal and is clocked by the corresponding write signal.
    Type: Grant
    Filed: March 21, 2002
    Date of Patent: February 11, 2003
    Assignee: Broadcom Corporation
    Inventor: Jun Cao
  • Patent number: 6486717
    Abstract: The oscillator 40 with cycle time correction includes a low accuracy oscillator 30A generating a clock CLK3, a counter 41 counting the clock CLK3 and cleared by activation of a clear signal CLR1, a register 42 storing a count CN of the counter 41 as a reference value RV in response to activation of a capture signal CAP; a comparator 43 activating a coincidence signal EQ when CN=RV, a control register 44 including a bit outputting a clear signal CLR2, a bit outputting an enable signal EN and a bit outputting a capture signal CAP, and logic circuits 45 and 46 activating the clear signal CLR1 when the clear signal CLR2 is active or when the enable signal EN and the coincidence signal EQ are both active.
    Type: Grant
    Filed: August 18, 2000
    Date of Patent: November 26, 2002
    Assignee: Fujitsu Limited
    Inventors: Toshiaki Kinoshita, Kunio Aduma
  • Patent number: 6473484
    Abstract: A digital counter and method for counting are implemented which minimize fatigue-related failure in the storage element for the count value. The counting sequence is chosen such that the transitions within individual storage elements are the same for each element within a complete counting cycle. The invention extends to software or microcontroller implemented methods for counting, including encoding and decoding applications.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: October 29, 2002
    Assignee: Microchip Technology Incorporated
    Inventor: Robert P. Mather
  • Patent number: 6473722
    Abstract: A fault detection system applies known data to the input of a circuit being inspected for faults and examines the circuit output for expected results. Faults in a circuit are detected by receiving unexpected results at the circuit output. A fault detection circuit provides a fault signal that is enabled only when a reset line is activated. Activation of the reset line also prompts the known data to be applied to the circuit input. The known data can be derived from memory storage units that provide a known output upon activation of the reset signal. Accordingly, the system does not require parity bits or excessive hardware to provide fault detection for almost all modes of failure in a given circuit.
    Type: Grant
    Filed: December 18, 1998
    Date of Patent: October 29, 2002
    Assignee: NEC Corporation
    Inventor: Hirotaka Nakano
  • Patent number: 6459752
    Abstract: A system and a method are characterized in that the method of detection can be configured by varying a size and/or a position of a time slot to be taken into consideration for the detection and/or by varying relevant bits of the counts to be compared. This makes it possible to individually adapt the detection method to various or varying requirements at any time and with a minimum of expenditure required.
    Type: Grant
    Filed: September 4, 2001
    Date of Patent: October 1, 2002
    Assignee: Infineon Technologies AG
    Inventors: Peter Rohm, Patrick Leteinturier
  • Patent number: 6396894
    Abstract: The present invention provides an overflow detector for a FIFO. The FIFO includes a plurality of registers each having an input and an output, a plurality of write signals each respectively coupled to a clock, one of the plurality of registers, and a plurality of read switches each respectively coupled to an output of one of the plurality of registers, each of the plurality of read switches being controlled by a respective read signal. The overflow detector includes a plurality of clocked registers each of which is coupled to receive a write signal and its corresponding read signal, wherein each clocked register records a read signal and is clocked by the corresponding write signal.
    Type: Grant
    Filed: January 29, 2001
    Date of Patent: May 28, 2002
    Assignee: Broadcom Corporation
    Inventor: Jun Cao
  • Patent number: 6385274
    Abstract: A watchdog timer includes an instruction decoder, a delay circuit and a counter. The instruction decoder decodes a watchdog timer initialization instruction regularly executed to generate an instruction pulse for initializing the count of the counter. The delay circuit delays the rising edge of the instruction pulse, and supplies the delayed instruction pulse to the counter as a signal for initializing the count. The delay circuit prevents the pulse signal from being supplied to the counter when the operation frequency of the microcomputer is high or when the supply voltage to the microcomputer is low, so that the count of the counter overflows, and the overflow signal causes the microcomputer to be reset. This makes it possible to reset the microcomputer before it runs away, thereby solving a problem of a conventional watchdog timer in that the microcomputer can produce, if it runs away, an unexpected signal from its port before it is reset, and hence can impair the security of the system.
    Type: Grant
    Filed: June 8, 2000
    Date of Patent: May 7, 2002
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric System LSI Design Corporation
    Inventor: Tomonori Nohara
  • Patent number: 6292524
    Abstract: A counting apparatus having excellent fail-safe characteristics can be used in a rotation-stopped detection apparatus. As a first feature, timing of a high-frequency signal P2 is carried out by a counter 1 after completion of a counting of pulse signals P1. When the frequency of the timing output for the high-frequency signal is a predetermined value, a judgment signal, indicating that the counting is normal, is generated by a frequency discriminating circuit 30. As a second feature, a counter 100 is preset using a preset signal. Then, after verifying by an output from a self hold circuit 102 that the counter 100 has been reset, a counting output is generated from a self hold circuit 104. As a third feature, the counting apparatus is used as timer circuits 203, 300, 400, and the generation frequency of a rotation detection pulse signal IP based on a sensor signal, is obtained to thereby detect a rotation-stopped condition of a rotating body.
    Type: Grant
    Filed: June 20, 2000
    Date of Patent: September 18, 2001
    Assignee: The Nippon Signal Co., Ltd.
    Inventors: Masayoshi Sakai, Koichi Futsuhara
  • Patent number: 6266625
    Abstract: There is described a method and system for calibrating measurements, in particular for calibrating a high resolution counter against an accurate real time calibrated clock signal. The method comprising obtaining the calibrated low resolution clock measurement and the corresponding high resolution counter measurement and calculating a range of possible corrections to the counter measurement to align it with the clock measurement. The correction range is adjusted to make it consistent with a previously stored correction range and a value is taken from it to calibrate the counter measurement. If the calculated range and the stored range are inconsistent then only the calculated range is used. A further measurement of the clock or counter is taken to double check.
    Type: Grant
    Filed: March 23, 1999
    Date of Patent: July 24, 2001
    Assignee: International Business Machines Corporation
    Inventor: Andrew Johnson
  • Patent number: 6215838
    Abstract: An apparatus for eliminating noise is disclosed. The present invention includes a counter, which counts in a first direction when an input signal is active, and in a second direction otherwise. A determining device is used to determine a predetermined first threshold value, and assert an output signal while such value is reached. The present invention also includes a limiting device, which prevents the counter from counting beyond or below a predetermined limit value.
    Type: Grant
    Filed: November 4, 1999
    Date of Patent: April 10, 2001
    Assignee: Elan Microelectronics Corp.
    Inventors: Yen-Yi Liu, Chiung-Ching Ku, Jyn-Guo Hwang, Strung-An Tarng
  • Patent number: 6215839
    Abstract: A low jitter fractional divider with low circuit speed constraint is disclosed, which lowers the frequency of a high frequency clock signal to perform a fraction division in the condition of low frequency. A compensation circuit, which has an adjust buffer and a down-counter, is provided for adjusting the output clock signal of the fractional divider to have a jitter substantially equal to the jitter occurred in high frequency, such that a low jitter can be achieved without being limited by the circuit speed.
    Type: Grant
    Filed: November 16, 1999
    Date of Patent: April 10, 2001
    Assignee: Sunplus Technology Co., Ltd.
    Inventor: Wen-Chang Lin
  • Patent number: 6148055
    Abstract: A counting apparatus having excellent fail-safe characteristics can be used in a rotation-stopped detection apparatus. As a first feature, timing of a high-frequency signal P.sub.2 is carried out by a counter 1 after completion of a counting of pulse signals P.sub.1. When the frequency of the timing output for the high-frequency signal is a predetermined value, a judgment signal, indicating that the counting is normal, is generated by a frequency discriminating circuit 30. As a second feature, a counter 100 is preset using a preset signal. Then, after verifying by an output from a self hold circuit 102 that the counter 100 has been reset, a counting output is generated from a self hold circuit 104. As a third feature, the counting apparatus is used as timer circuits 203, 300, 400, and the generation frequency of a rotation detection pulse signal I.sub.P based on a sensor signal, is obtained to thereby detect a rotation-stopped condition of a rotating body.
    Type: Grant
    Filed: June 19, 1997
    Date of Patent: November 14, 2000
    Assignee: The Nippon Signal Co., Ltd.
    Inventors: Masayoshi Sakai, Koichi Futsuhara
  • Patent number: 6101233
    Abstract: Counter circuits causing no noise at the time of operation are provided. Three stage of D-type flip-flops (FF1 to FF3) are connected in series. A delay element (11) delays a signal (S2) that is Q output of the flip-flop (FF1) by a delay time (d2) to output a delay signal (S2D), and a delay element (12) delays a signal (S3) that is Q output of the flip-flop (FF2) by a delay time (d3) to output a delay signal (S3D). Here, the relationship among the delay time (d2, d3) and a clock cycle (Tc) is set so as to satisfy the condition of {Tc>d2>d3}. NOR gate for three inputs (G1) receives delay signals (S2D, S3D) and a signal (S4) i.e., Q output of the flip-flop (FF3), and performs NOR operation on these signals (S2D, S3D and S4), thereby outputting a signal (S1) to D input of the flip-flop (FF1).
    Type: Grant
    Filed: September 2, 1998
    Date of Patent: August 8, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toru Nakura, Kimio Ueda
  • Patent number: 6084935
    Abstract: A digital counter and method for counting are implemented which minimize fatigue-related failure in the storage element for the count value. The counting sequence is chosen such that the transitions within individual storage elements are the same for each element within a complete counting cycle. The invention extends to software or microcontroller implemented methods for counting, including encoding and decoding applications.
    Type: Grant
    Filed: August 13, 1998
    Date of Patent: July 4, 2000
    Assignee: Microchip Technology Incorporated
    Inventor: Robert P. Mather
  • Patent number: 6072849
    Abstract: A programmable n stage shift counter divider circuit includes a plurality of n flip-flops arranged in cascade from a first stage to an nth stage. The data inputs of each of the flip flops are coupled with the output of the next preceding stage through corresponding OR gates. A source of preload signals is coupled with the second inputs of the OR gates; and a combined trap detector and terminal count detector has inputs coupled with the outputs of the last n-1 stages of the shift counter circuit and an output coupled with the source of pre-load signals to operate it.
    Type: Grant
    Filed: August 4, 1998
    Date of Patent: June 6, 2000
    Assignee: VLSI Technology, Inc.
    Inventor: D. C. Sessions