Abstract: A dynamic MOS random-access memory is described which includes a circuit for permitting checking of the on chip refresh counter. The memory also includes a refresh generator, the frequency of which automatically varies to compensate for temperature variations. Other innovations include an arbitration circuit, a hidden refresh function and unique accessing of redundant lines.

Abstract: A fail safe digital timer is provided by having a pair of similar counters counting the output of a single clock means. The clock means provides clock pulses and complimentary clock pulses to the two counters and the outputs of the counters are compared. If the two counters are properly operating the comparison will provide a continuous stream of pulses at a frequency equal to the frequency of the clock means for the timer. The failure of any of the components in the system cause the output of the comparator means to either become a constant logic 1 or a constant logic 0.