Counter Controlled Counter Patents (Class 377/44)
  • Patent number: 10177773
    Abstract: In accordance with an embodiment, a circuit includes an input clock terminal, an output clock terminal, a first input data terminal, and a set of input data terminals having a number of terminals. A divide-by-two block is coupled to the output clock terminal. A modular one-shot clock divider is coupled between the input clock terminal and the divide-by-two block. The modular one-shot clock divider is further coupled to the set of input data terminals. An intermediate clock generation block is coupled between the input clock terminal and the modular one-shot clock divider. The intermediate clock generation block includes a first digital logic block coupled between the input clock terminal and the modular one-shot clock divider. The first digital logic block is further coupled to the first input data terminal, and a clock-blocking block is coupled between the divide-by-two block and the first digital logic block.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: January 8, 2019
    Assignee: STMicroelectronics International N.V.
    Inventors: Nitin Gupta, Jeet Narayan Tiwari
  • Patent number: 9774333
    Abstract: A counter circuit includes a first Johnson counter circuit and a second Johnson counter circuit coupled in cascade. Each Johnson counter circuit includes a clock input, a data input, a first clock data output, a second clock data output and a feedback from the second clock data input to first data input. The clock input of the first Johnson counter circuit is configured to receive an input clock signal. The clock input of the second Johnson counter circuit is connected to the second clock data output of the first Johnson counter circuit. A ripple counter circuit has a clock input and additional clock data outputs. The clock input of the ripple counter circuit is connected to the second clock data output of the preceding Johnson counter circuit.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: September 26, 2017
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventor: Cedric Tubert
  • Patent number: 9454471
    Abstract: An electronic counter is provided having a sequence of memory cells and increment logic. Each memory cell of the sequence is non-volatile and supports a one state and a zero state. The one state can also be referred to as a ‘programmed state’, the zero state as an ‘erased state’. The counter is configured to represent at least part of a current counting-state of the counter as a pattern of one and zero states in the memory cells of the sequence of memory cells, and increment logic configured to advance the pattern of one and zero states to a next pattern to represent an increment of the counter.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: September 27, 2016
    Assignee: NXP B.V.
    Inventors: Martin Feldhofer, Franz Amtmann, Soenke Ostertun, Alicia da Conceicao
  • Patent number: 9151772
    Abstract: To include a pulse counting unit, a pulse timing unit, an overflow detection unit that holds a detected matter in an overflow register, a capture unit that holds an output of the pulse counting unit in a pulse counting register and holds an output of the pulse timing unit in a pulse timing register, and a computation unit (frequency calculation unit) that reads the pulse counting register, the pulse timing register, and the overflow register to calculate a frequency computation value, and when the pulse timing unit has overflowed, the computation unit adds a predetermined constant acquired by a period of a capture clock a period of a timing clock to pulse timing data at the previous interrupt to obtain pulse timing data acquired by a period of time from the last pulse edge a period of the timing clock.
    Type: Grant
    Filed: March 16, 2010
    Date of Patent: October 6, 2015
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Hiroshi Yoshikawa
  • Patent number: 9042508
    Abstract: A counter configured to perform counting at both edges of an input clock to output an additional value or a subtraction value for a previous count value and a next count value includes a first latch circuit that latches the input clock, a second latch circuit that latches an output from the first latch circuit, a holding section that holds data of the 0th bit of a count value, and a correction section that performs count correction on data of the first and subsequent bits of the count value on the basis of an output of the second latch circuit.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: May 26, 2015
    Assignee: SONY CORPORATION
    Inventor: Yasuaki Hisamatsu
  • Patent number: 8983023
    Abstract: An n-bit counter is formed from cascading counter sub-modules. The counter includes combinatorial control logic coupled to a lower order counter sub-module. The control logic is arranged to clock gate at least one higher order counter sub-module dependent on a logical combination of outputs of the lower order counter sub-module and where the control logic uses pipelining to store at least one previous control logic output for use in determining a later control logic output.
    Type: Grant
    Filed: July 4, 2013
    Date of Patent: March 17, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Naman Gupta, Amol Agarwal, Gaurav Goyal
  • Patent number: 8964931
    Abstract: A counter is provided, where, as the number of events that occur increases, the frequency in which the events are counted is scaled.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 24, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Joseph Daniel Gleason
  • Patent number: 8832488
    Abstract: A method and apparatus for digital I/O expander chip with multi-function timer cells have been disclosed. A series of match reload registers load a series of match registers which are driven by a master counter. The status of the match registers can be retrieved through ports. The master counter is reloaded on rollover by a count limit register. The master counter has increment/decrement control and the rollover can be used in an interrupt control block to generate an interrupt request.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: September 9, 2014
    Assignee: Digi International Inc.
    Inventors: Norman L. Rogers, Monte J. Dalrymple, Lynn S. Wood, Steve J. Hardy
  • Patent number: 8761332
    Abstract: A prescaling counter includes a prescaling unit and a counter. The prescaling unit includes a programmable divider that is arranged to divide an event clock that includes signaled events to generate a prescaled clock in response to a prescaling value. The counter includes a register that includes a lower count register and an upper count register for generating a count result. The counter is arranged to increment the lower count register in response to the prescaled clock and to increment the upper count register in response to a terminal condition in the lower count register. The prescaling value is generated in response to the upper count register.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: June 24, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Lothar K Felten, Lars Lotzenburger
  • Publication number: 20140086378
    Abstract: A prescaling counter includes a prescaling unit and a counter. The prescaling unit includes a programmable divider that is arranged to divide an event clock that includes signaled events to generate a prescaled clock in response to a prescaling value. The counter includes a register that includes a lower count register and an upper count register for generating a count result. The counter is arranged to increment the lower count register in response to the prescaled clock and to increment the upper count register in response to a terminal condition in the lower count register. The prescaling value is generated in response to the upper count register.
    Type: Application
    Filed: September 24, 2012
    Publication date: March 27, 2014
    Applicant: Texas Instruments, Incorporated
    Inventors: Lothar K. Felten, Lars Lotzenburger
  • Patent number: 8643440
    Abstract: An electric circuit includes: a reference signal generation circuit that generates a reference signal based on a first oscillation signal that is an oscillation signal of a first oscillation circuit that vibrates a first vibrator; and a counter circuit that counts a second oscillation signal that is an oscillation signal of a second oscillation circuit that vibrates a second vibrator based on the reference signal, and outputs a count signal, wherein the count signal is a change of the count value in the second oscillation signal.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: February 4, 2014
    Assignee: Seiko Epson Corporation
    Inventors: Takayuki Kondo, Masayoshi Todorokihara, Yoshihiko Nimura, Takeo Kawase
  • Patent number: 8639366
    Abstract: A control device for generating a second trigger with a delay of a predetermined time from generation of a first trigger, the control device having: a counter for counting numbers from 0 to n?1 at a frequency with cycles of a first period; a control section, which operates at a frequency with cycles of a second period that is longer than the first period, for calculating a remainder of a division by adding a number of counts of the counter corresponding to the predetermined time to a count value of the counter at the time of generation of the first trigger and by dividing a result of the addition by n; and an output section for outputting the second trigger at a time when the count value of the counter becomes equal to the remainder.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: January 28, 2014
    Assignee: Konica Minolta Business Technologies, Inc.
    Inventors: Yuta Tachibana, Norihiko Nakano, Hiroyuki Watanabe, Tomonobu Tamura
  • Publication number: 20130114782
    Abstract: A display panel drive device includes: a ring counter circuit that includes a first ring counter having a plurality of flipflops connected in cascade, configured to operate in synchronization with a first clock signal with a first-stage one of the plurality of flipflops being set by an initial signal, and outputs signals using outputs of the plurality of flipflops; a shift register having a plurality of flipflops connected in cascade, configured to operate in synchronization with a second clock signal lower in frequency than the first clock signal with a first-stage one of the plurality of flipflops being set by the initial signal; and an output section configured to perform a logical operation between one of outputs of the ring counter circuit and one of outputs of the shift register, to generate a scanning line drive signal for a display panel.
    Type: Application
    Filed: January 3, 2013
    Publication date: May 9, 2013
    Applicant: PANASONIC CORPORATION
    Inventor: PANASONIC CORPORATION
  • Patent number: 8406370
    Abstract: According to one embodiment, S (S is an integer equal to or larger than two) number of sub counters each count S number of clocks of different frequencies, and a clock switching unit is provided for each sub counter and starts a counting operation of a sub counter of a next stage after finishing a counting operation in a sub counter of a local stage.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: March 26, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazuki Hizu
  • Patent number: 8300250
    Abstract: Print jobs received at a printer are assigned a reference which is incorporated as a visible representation of the reference in the printed print job. When the user recovers the print job, the reusable print job addendum. is fed back into the printer, for reuse in later print jobs.
    Type: Grant
    Filed: April 23, 2008
    Date of Patent: October 30, 2012
    Assignee: International Business Machines Corporation
    Inventors: Alexandre Chabrol, Benoit Granier, Aurelien Jarry, Arnaud Mante
  • Patent number: 8199872
    Abstract: A system includes a memory and a counter circuit associated with the memory and configured to receive a clock signal and a plurality of input bits, and configured to output a plurality of output bits to the memory. The counter circuit includes a first counter configured to receive a part of the plurality of input bits and to output a part of the plurality of output bits and a first signal, a control circuit configured to receive the clock signal and the first signal, and to output a second signal, and a second counter configured to receive another part of the plurality of input bits and the second signal, and to output another part of the plurality of output bits.
    Type: Grant
    Filed: April 20, 2011
    Date of Patent: June 12, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Yasuhiro Oda
  • Publication number: 20120121060
    Abstract: A counter is efficiently implemented in non-volatile memory by using two binary counters and selectively using one or the other as a current counter. Writes to the binary counters are minimized by using two linear counters and using the state of the binary counters to determine which binary counter contains the current count. Write operations can be performed to the “not current” binary counter with the final write operation being to the linear counters. The linear counter write operations can be in program-only mode so that a power failure will not result in a loss of counts.
    Type: Application
    Filed: November 17, 2010
    Publication date: May 17, 2012
    Applicant: ATMEL CORPORATION
    Inventors: Randall Wayne Melton, Brad Phillip Garner, Kerry David Maletsky
  • Patent number: 8014487
    Abstract: A counter circuit and method of controlling such a counter circuit, including a first counting section that counts in accordance with a state-cycle, and a second counting section clocked by the first counting section. At least one invalid counting state is introduced by controlling the second counting section to change its state before the first counting section has completed the state-cycle; and the invalid counting state is then detected and corrected. Thereby, some redundancy is introduced in the counter, which can be used to detect and correct incomplete switching of counter states.
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: September 6, 2011
    Assignee: NXP B.V.
    Inventor: Remco C. H. Van De Beek
  • Patent number: 7965809
    Abstract: A counter circuit adding a first value indicated by a plurality of bits and a second value in response to a clock signal, a first part of the plurality of bits being lower order than a second part of the plurality of bits, the counter circuit including a first counter configured to add the first part of the plurality of bits and the second value in response to the clock signal to output a third value regarding a result of adding the first and the second values, a second counter configured to add the second part of the plurality of bits and a fourth value in response to the clock signal, and a clock transmission control circuit coupled to the first and second counters to receive the clock signal and the third value, and to control whether or not to supply the clock signal to the second counter in accordance with the received third value.
    Type: Grant
    Filed: August 3, 2010
    Date of Patent: June 21, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Yasuhiro Oda
  • Patent number: 7941687
    Abstract: A method and apparatus for digital I/O expander chip with multi-function timer cells have been disclosed. A series of match reload registers load a series of match registers which are driven by a master counter. The status of the match registers can be retrieved through ports. The master counter is reloaded on rollover by a count limit register. The master counter has increment/decrement control and the rollover can be used in an interrupt control block to generate an interrupt request.
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: May 10, 2011
    Assignee: Digi International Inc.
    Inventors: Norman L. Rogers, Monte J. Dalrymple, Lynn S. Wood, Steve J. Hardy
  • Patent number: 7813468
    Abstract: Reduction in power consumption of a counter circuit for continuous operation is demanded. Therefore, provided is a counter circuit including: a first counter of m bits for counting and storing a value of a predetermined bit width according to an input clock; a clock transmission control circuit for controlling whether to transmit the input clock based on a value output according to a counting result of the first counter; and a second counter of n bits for counting and storing another value of the predetermined bit width according to the input clock transmitted from the clock transmission control circuit.
    Type: Grant
    Filed: February 5, 2009
    Date of Patent: October 12, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Yasuhiro Oda
  • Patent number: 7735031
    Abstract: A system that includes a controller for enabling an enumeration operation. The enumeration operation is performed by a controller (110) and logic elements (120) in a system, such that each logic element in the system assigns itself a unique identifier. Each logic element can then be controlled by another source or have a means to communicate with other logic elements in the system. The unique identifier enables greater system flexibility, thereby reducing cost and improving efficiency.
    Type: Grant
    Filed: August 20, 2007
    Date of Patent: June 8, 2010
    Assignee: International Business Machines Corporation
    Inventors: Valerie Hornbeck Chickanosky, Kevin William Gorman, Emory D. Keller, Michael Richard Ouellette
  • Patent number: 7702061
    Abstract: A multi-bit counter is provided. The multi-bit counter includes a plurality of asynchronous base counter cells coupled in series, the asynchronous base counter cells having a plurality of input terminals. The multi-bit counter also includes at least one logic gate coupled to at least one of the input terminals of at least one of the plurality of asynchronous base counter cells, a reload signal being input into the asynchronous base counter cells, a clock signal being input into the asynchronous base counter cells, and an input voltage being input into the asynchronous base counter cells, wherein the multi-bit counter is synchronous with the clock signal.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: April 20, 2010
    Assignee: Integrated Device Technology, Inc.
    Inventors: Zhuyan Shao, Juan Qiao
  • Patent number: 7688465
    Abstract: An information managing apparatus assigns identification information to print information and manages the print information based on the identification information. A receiving section receives a plurality of items of data. A first counter is defined in a non-volatile first memory. A second counter is defined in a volatile second memory. An identification information producing section produces the identification information for each of the plurality of items of data based on a count of the first counter and a count of the second counter. An identification information managing section manages the plurality of items of data based on the identification information. The second counter counts up by a value every time the receiving section receives an item of data, and the first counter counts up when the image forming apparatus is turned on, and when the second counter overflows.
    Type: Grant
    Filed: January 13, 2006
    Date of Patent: March 30, 2010
    Assignee: Oki Data Corporation
    Inventor: Masayuki Maeda
  • Patent number: 7519846
    Abstract: Methods and apparatuses for detecting an in-band reset using digital circuitry. A first counting circuit is coupled to receive a first clock signal and to generate output signals based on a number of cycles of the first clock signal. A second counting circuit is coupled to receive a second clock signal and the output signals from the first counting circuit. The second counting circuit generates output signals based on number of cycles of the second clock signal. A comparison circuit is coupled with to receive the output signals of the second counting circuit and to generate a reset signal if the output signals from the second counting circuit correspond to a pre-selected range.
    Type: Grant
    Filed: December 28, 2005
    Date of Patent: April 14, 2009
    Assignee: Intel Corporation
    Inventors: Timothy Frodsham, Zale T Schoenborn, Sanjay Debral, Muraleedhara H. Navada
  • Patent number: 7359475
    Abstract: A counter circuit includes a counter section having flip-flops of a plurality of stages. The flip-flops from a first stage to an (N-1)th (N is an integer more than 2) stage synchronously count a clock signal. A mask circuit section controls supply of the clock signal to the flip-flop of an N stage based on outputs of the flip-flops from the first stage to the (N-1)th stage.
    Type: Grant
    Filed: January 10, 2006
    Date of Patent: April 15, 2008
    Assignee: NEC Electronics Corporation
    Inventor: Masaya Yamaguchi
  • Patent number: 7342990
    Abstract: A wake-up circuit includes a counter, a register circuit, a first logic circuit, an oscillator, a flip flop, and a second logic circuit. The wake-up circuit receives a standby signal to stop the oscillator working and to wait for the wake-up signal to reactivate the oscillator again. When the duration of the wake-up signal is shorter than an expected time of the counter, the oscillator stops working again and re-enters the saving mode. When the duration of the wake-up signal is longer than the expected time of the counter, the counter controls the flip flop to output a preset signal to the register circuit, and as a result that keeps the oscillator working even after the wake-up signal is removed by the first logic circuit operating, and then the second logic circuit operates with flip-flop to set the counter returning to a normal state to wait for a next standby signal to feed in.
    Type: Grant
    Filed: February 3, 2006
    Date of Patent: March 11, 2008
    Assignee: Neotec Semiconductor Ltd.
    Inventor: Fomin Uladzimir
  • Patent number: 7319751
    Abstract: A method of encrypting a data unit, the method comprising the steps of dividing the data unit into a series of data blocks, and for each data block, applying a block cipher function to a data block counter value to generate an encrypted block counter value, performing a logical operation to combine the encrypted block counter with the data block, and applying a block cipher function to the combined data.
    Type: Grant
    Filed: October 11, 2002
    Date of Patent: January 15, 2008
    Assignee: F-Secure Oyj
    Inventor: Alexey Kirichenko
  • Patent number: 7231012
    Abstract: A programmable frequency divider capable of operating in a normal mode and a fractional mode divides the input clock frequency by any integer ‘N’ provided at the input. In the normal mode the input is divided by the integer ‘N’. The divided output signal has a 50% duty cycle if the input clock has a 50% duty cycle. In the fractional mode, fractional division can be achieved from dividing by 1.5 to dividing by 255.5 in steps of 0.5.
    Type: Grant
    Filed: November 29, 2005
    Date of Patent: June 12, 2007
    Assignee: STMicroelectronics Pvt. Ltd.
    Inventors: Ashish Panpalia, Puneet Sareen
  • Patent number: 7190756
    Abstract: Integrated circuit counting apparatuses are described. More particularly, a hybrid counter (203) including an asynchronous counter (310) front end and a synchronous counter (311) back end is described. The asynchronous counter (310) including at least one asynchronous counter stage (341, 342, 343) having an asynchronous level-mode state machine (381, 382). The asynchronous level-mode state machine formed of Differential Cascode Voltage Switch Logic.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: March 13, 2007
    Assignee: Xilinx, Inc.
    Inventors: Alireza S. Kaviani, Carlos M. Vasquez
  • Patent number: 7058839
    Abstract: In a first aspect, a counter is maintained in main memory, and a corresponding counter having a smaller number of bits is maintained in cache memory. The counter in cache memory is incremented and when a certain count threshold is reached, the corresponding counter in main memory is updated using the cache memory counter value. This arrangement economizes on the use of main memory access bandwidth.
    Type: Grant
    Filed: April 11, 2002
    Date of Patent: June 6, 2006
    Assignee: International Business Machines Corporation
    Inventor: Kerry Christopher Imming
  • Patent number: 6961402
    Abstract: Described are fast synchronous counters with reduced combinatorial logic. In one embodiment, a four-bit shift register is configured in a ring and preset with a data pattern (e.g., 1000). The register is then rapidly shifted into any of four unique states. Combinatorial logic connected to the shift register converts the four unique states into a two-bit binary signal representative of the four states. In the general case, counters in accordance with this embodiment represent N-bit binary numbers using 2N synchronous storage elements. Two or more counters can be combined to produce larger synchronous counters. An up/down counter in accordance with yet another embodiment is connected to a multi-path delay line to create a variable delay circuit. The switching speed of the delay circuit is independent of the number of delay settings. Also advantageous, the delay circuit scales linearly, in terms of power consumption and area, with changes in delay granularity.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: November 1, 2005
    Assignee: Xilinx, Inc.
    Inventor: Ahmed Younis
  • Patent number: 6925139
    Abstract: The present invention relates to an integrated circuit comprising a first clock circuit delivering a first clock signal, a second clock circuit delivering a second clock signal, a first counting circuit for delivering a time base signal using a clock signal and a counting value, and means for applying the first clock signal and a first counting value to the first counting circuit, so as to produce a first time base signal. According to the present invention, the integrated circuit comprises means for producing a second time base signal using the second clock signal and a second counting value, and means for calibrating the second counting value such that it is equal or proportional to the number of periods of the second clock signal occurring during a determined time interval equal to a period or to a whole number of periods of the first time base signal. Application particularly to the management of a timer in a microprocessor.
    Type: Grant
    Filed: January 15, 2004
    Date of Patent: August 2, 2005
    Assignee: STMicroelectronics S.A.
    Inventors: Sandrine Lendre, Franck Roche, Olivier Plourde
  • Patent number: 6862332
    Abstract: A master clock signal source (10) generates a master clock signal having a frequency equal to N times the bit rate of received data, where N is a positive integer. A modulo-N counter (12) counts the master clock signal. An edge detecting circuit (4) detects a transition of the received data from a H level to a L level. A counter (8) counts the master clock signal and resets the modulo-N counter (12) if the count counted during a time period in which three edge representative signals occur is 2N. In accordance with the count in the modulo-N counter 12, a clock generating unit 14 generates a clock signal.
    Type: Grant
    Filed: February 25, 2002
    Date of Patent: March 1, 2005
    Assignee: TOA Corporation
    Inventor: Ken'ichi Ejima
  • Patent number: 6836853
    Abstract: A value for a first counter is maintained. A value for a second counter based on a content of a non-volatile memory is maintained. Updates to the value for the first counter and to the value for the second counter are controlled.
    Type: Grant
    Filed: December 31, 1999
    Date of Patent: December 28, 2004
    Assignee: Intel Corporation
    Inventors: Lance W. Dover, Andrew H. Gafken
  • Patent number: 6731176
    Abstract: The present invention provides a synthesizer having an efficient lock detect signal generator, an extended range VCO that can operate within any one of a plurality of adjacent characteristic curves defined by a plurality of adjacent regions, and a divide circuit implemented using only a single counter along with a decoder. This allows for a method of operating the synthesizer, methods of establishing or reestablishing a lock condition using the extended range VCO, and a method of designing a plurality of divide circuits which each use the same single counter and each use a different decoder.
    Type: Grant
    Filed: March 13, 2002
    Date of Patent: May 4, 2004
    Assignee: Atheros Communications, Inc.
    Inventors: David K. Su, Chik Patrick Yue, David J. Weber, Masound Zargari
  • Patent number: 6700946
    Abstract: Methods and systems for automatic generation of an at-speed binary counter are described. The binary counter includes a slow counter that increments when a fast counter overflows to keep up with a fast clock. A framework to automatically generate a Hardware Description Language (HDL) for an at-speed binary counter is also described.
    Type: Grant
    Filed: February 8, 2002
    Date of Patent: March 2, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Kamran Zarrineh, Kenneth House, Joseph R. Siegel
  • Patent number: 6597246
    Abstract: A phase-locked loop (PLL) includes a down counter having a detection circuit configured to determine when the counter reaches its terminal count. The down counter also includes a control line configured to alter the terminal count detected by the detection circuit by an off-set.
    Type: Grant
    Filed: May 14, 2001
    Date of Patent: July 22, 2003
    Assignee: DSP Group, Inc.
    Inventors: Eric L. Unruh, Scott G. Gibbons
  • Publication number: 20030108142
    Abstract: A conventional up/down Gray code counter has both a logic circuit section for up counting and a logic circuit section for down counting, and thus has a large circuit scale. To overcome this inconvenience, an up/down Gray code counter of the invention has a one-way Gray code counter that can count only in one, up or down, direction and a highest bit selecting circuit that receives the highest bit of the data output from the one-way Gray code counter and that then outputs the bit selectively either intact or after inverting it.
    Type: Application
    Filed: December 7, 2001
    Publication date: June 12, 2003
    Inventor: Mutsumi Hamaguchi
  • Publication number: 20020172320
    Abstract: An integrated circuit chip includes performance counters. Each one of the performance counters counts data events. There are a plurality of registers associated with the performance counters. At least one of the registers controls the stopping, starting and counting of an associated performance counter. A command trigger issues a command to the register upon the detection of a hardware event. The command initiates the starting, stopping or counting of the counter associated with the register.
    Type: Application
    Filed: March 28, 2001
    Publication date: November 21, 2002
    Inventor: James S. Chapple
  • Patent number: 6448827
    Abstract: The present invention provides a three-phase pulse width modulation waveform generator having at least an up-down counting circuitry which comprises: an up-down counter for performing an up-count or a down-count upon an external input of a count clock signal; and a count controller having an output side connected to an input side of the up-down counter for sending the input side of the up-down counter a count enable signal which enables the up-down counter to perform the up-count or the down-count.
    Type: Grant
    Filed: November 27, 2000
    Date of Patent: September 10, 2002
    Assignee: NEC Corporation
    Inventor: Hidetoshi Tojima
  • Patent number: 6393088
    Abstract: An event counter circuit including an input signal coupled to a frequency divider circuit that can be cleared by an external signal, a multiplexer coupled to the divider circuit driven by an output edge and its inverse, and a counter circuit coupled to the multiplexer driven by outputs of the multiplexer.
    Type: Grant
    Filed: January 16, 2001
    Date of Patent: May 21, 2002
    Assignee: Wavecrest Corporation
    Inventors: Mark J. Emineth, Steve McCoy, Jan Wilstrup, Chris Kimsal
  • Patent number: 6326824
    Abstract: An initial value generation circuit generates an initial value taking into consideration the a time delay when a signal is transmitted through the signal wires between a pilot device and other devices, and a processing delay caused in respective devices. When a device receives a system synchronizing signal form another device, the device sets an initial value in a counter. Thereby, the counter value of a counter in a pilot device and counter values of counters in the other devices are made to coincide with each other.
    Type: Grant
    Filed: July 27, 2000
    Date of Patent: December 4, 2001
    Assignee: Fujitsu Limited
    Inventors: Koji Hosoe, Jun Funaki, Toshiyuki Shimizu, Michio Numata
  • Patent number: 6222900
    Abstract: There is provided a counter device comprising a master counter for counting an input signal applied thereto and a plurality of local counters disposed in a plurality of functional blocks, respectively, each for counting the input signal applied thereto, and for holding a count value corresponding to a plurality of bits of a count value of the master counter. A bus is disposed for each of the plurality of functional blocks to refer to remaining bits of the count value of the master counter.
    Type: Grant
    Filed: November 9, 1999
    Date of Patent: April 24, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Tetsuya Hara
  • Patent number: 6163181
    Abstract: A frequency divider circuit, and a digital PLL circuit including the same, which can suppress jitter occurring in an output signal, including a first circuit module which drives D-FFs connected in series using an input signal as a reference clock signal and divides the input signal by a frequency division ratio selected by a frequency division ratio determining signal to produce a first divided signal; a second circuit module which drives D-FFs connected in series using the first divided signal as a reference clock signal and divides the first divided signal by a frequency division ratio corresponding to the number of D-FFs connected in series to produce an output signal; and an OR circuit which produces a frequency division ratio determining signal based on the outputs of the D-FFs of the second circuit module and a frequency division ratio selecting signal.
    Type: Grant
    Filed: September 16, 1998
    Date of Patent: December 19, 2000
    Assignee: Sony Corporation
    Inventor: Seiichi Nishiyama
  • Patent number: 6097782
    Abstract: A multi-ratio frequency divider, which is implemented in a BiCMOS (bipolar-complementary metal oxide semiconductor) circuit, includes a dual-modulus counter for dividing by P+1 and P. P+1 is a power of two and there is not necessary an additional flip-flop responsive to high input frequency, which consumes power due to bipolar transistor devices. An output from the counter is further divided by a variably set value. When its count reaches another set value, the division ratio of the dual-modulus counter is switched to another division ratio. When the further divided counter reaches the variably set value, a new cycle starts. The total division ratio of the multi-modulus frequency divider is a combination of the variably set division values, both being binary bit data. No decoder is necessary for converting an input division ratio to the set values.
    Type: Grant
    Filed: July 17, 1998
    Date of Patent: August 1, 2000
    Assignee: Nortel Networks Corporation
    Inventor: Navid Foroudi
  • Patent number: 6088421
    Abstract: A method and apparatus for monitoring an event is disclosed. In one embodiment, a ratio counter is provided which includes a first counter having a first count and a second counter having a second count. The method increments the first count of the first counter on an occurrence of an event by a first device and shifts the ratio counter to the right by a predetermined number of bits when the first count reaches a maximum count. The method further takes a ratio between the first count and the second count where the ratio indicates the relative occurrence of the event by the first device and a second device. In another embodiment, the method decrements the second count of the second counter when the first count reaches a maximum count. In yet another embodiment, the method decrements the first count of the first counter and the second count of the second counter when the first count reaches a maximum count.
    Type: Grant
    Filed: July 28, 1998
    Date of Patent: July 11, 2000
    Assignee: Intel Corporation
    Inventors: Ravi S. Rao, Elliot D. Garbus
  • Patent number: 6067273
    Abstract: The present invention is directed to a circuit for detecting the end of a burst count in a semiconductor memory device. The circuit is responsive to a plurality of burst counter output bits and a plurality of burst length selection bits. The circuit is comprised of an array of individual semiconductor devices responsive to the burst counter output bits and the burst length selection bits for producing a transition in an output signal when the burst counter output bits are at a logical combination determined by the burst length selection bits. A method for detecting the end of a burst count in a semiconductor memory device is also disclosed.
    Type: Grant
    Filed: July 29, 1999
    Date of Patent: May 23, 2000
    Assignee: Micron Technology, Inc.
    Inventor: Donald Morgan
  • Patent number: 6049358
    Abstract: A counter control circuit of a counter for measuring a pulse period of a video synchronization signal includes a main control unit having a synchronization signal input Sync, and a control signal producing unit including a stop signal generator, a latch signal generator, and a start signal generator. The outputs of the stop, latch and start signal generators are supplied to the counter for controlling the counter to count clock pulses fed from a clock generator in response to receipt of a start signal and output a count value in response to receipt of a latch signal. The main control unit produces sequential control signals during the input of the video synchronization signal differentiated by the clock pulses. The counter control circuit allows the counter to measure a pulse period of an input synchronization signal in a stable state that results in an accurate count value, since the count operation is first stopped and the count value is latched by the clock signal.
    Type: Grant
    Filed: July 7, 1997
    Date of Patent: April 11, 2000
    Assignee: SamSung Electronics Co., Ltd.
    Inventor: Sung-Gon Jun
  • Patent number: 6026139
    Abstract: Integrated counter-based instrumentation for generating a frequency distribution representation such as a histogram. An integrated circuit device includes an event counter to count a number of a predetermined type of events detected in each of a plurality of measurement periods during a first sub-experiment period. A frequency counter coupled to the event counter is to be incremented at the end of each measurement period if the number counted by the event counter meets a first test. A count stored in the frequency counter is provided to a frequency distribution data store at the end of the first sub-experiment period.
    Type: Grant
    Filed: June 16, 1998
    Date of Patent: February 15, 2000
    Assignee: Intel Corporation
    Inventors: Frank T. Hady, C. Brendan S. Traw