Abstract: A speed independent system is used for obtaining a preselected number of samples from an object moving along a fixed path, such as a railroad train passing through a sensing zone along the section of track. The sensing zone is defined by a pair of wheel sensors. Upstream of the sensing zone a third sensor is positioned. The distance between the third sensor and the closer of the pair of sensors comprises a reference distance which is the length of the sensing zone multiplied by a known multiple. The time for the train to pass through the reference distance is obtained and then divided by a divisor comprising the product of the known multiple and the desired number of samples to obtain a single interval. During the time the train passes through the sensing zone consecutive intervals are counted off to obtain the desired number of samples.

Abstract: A clock pulse control device for address allocation of a read-only memory in a small size sequence controller in which data stored in the read-only memory are read out sequentially to operate an output relay during a time interval in accordance with the stored data, and the relay controls a load. Clock pulses generated by a frequency-dividing clock pulse generator (30) are applied to presetable down counters (33) and (34) in which the clock pulses are divided down to pulses each having a time period corresponding to the preset value. The divided pulses are applied to a binary counter (29). The outputs of the binary counter (29) are delivered to the read-only memory provided outside from address lines (Q1)-(Q7) via a connector (10) to allocated addresses of the read-only memory sequentially. Predetermined data are stored in the read-only memory in advance and the data of the allocated addresses are delivered to operate the output relay.

Abstract: A sequence of or controls pulse-transfer stages supplies or controls pulses between a start limit and a stop limit in the sequence. The device whose position is to be encoded selects and controls a responsive means in a limiting stage. Each stage has a pulse-control device responsive to the selector or in itself incorporates the selector-responsive pulse-control function, being arranged to serve in different embodiments as a start limit or as a stop limit. In one example, the start limit is the initial stage of the sequence and the selected stage is the stop limit. In an alternative, the selected stage is the start limit and a pulse-transfer stage at or near the end of the sequence is the stop limit. An encoding counter counts pulses between the start and stop limits. The pulse-control devices have a prescribed physical arrangement, which is a circle in the case of a shaft position encoder, so that the counter provides a code that represents the position of a shaft.

Abstract: A frequency synthesizer or a circuit for deleting cycles from a wave source includes a dual modulus counter responsive to a reference frequency source of the synthesizer or waves of the source. The dual modulus counter selectively decreases the number of cycles of the source by the factors K.sub.2 and (K.sub.2 +1). A frequency divider divides the frequency of the source by a third factor L to derive an output wave. The dual modulus counter is activated so it divides by K.sub.2 +1, whereby the dual modulus counter derives an output signal having a frequency F.sub.0 =F.sub.in /K.sub.2 (1-1/L), where F.sub.in equals the frequency of the source, L is an integer and K.sub.2 is an integer greater than L.

Abstract: Hashing of a key data signal is accomplished by utilizing a pseudo random number signal generator for generating a randomized signal in response to the key data signals and an output register for serially receiving the generated pseudo-random signal and for providing segments of the serially-received signal at its output. A counting circuit responsive to a preselected number of shift signals provides an output valid signal when the preselected number of shift signals has occurred and further shifts the pseudo-random number signal generator an amount corresponding to the preselected number of shift signals. The method of the present invention utilizes the steps of presetting the pseudo-random number generator and the counting circuit to an initialized state. The counting circuit is then loaded with a predetermined count whereupon key data is entered into the pseudo-random number generator so as to randomize the key data.

Abstract: A television base signal and test signal generator comprises a first memory for storing n eight-bit words (n being a positive whole number) located by a pair of indices (i, j) and a second memory for storing t four-bit words (t being a positive whole number) located by an index k. A first counter and a second counter supply respectively the index i associated with the word to be read in the first memory and the index k associated with the word to be read in the second memory. The index j associated with the word to be read in the first memory corresponds to the value of the four-bit word supplied by the second memory. The two memories are programmed so that at all times the eight bits of the word read in the first memory define entirely the desired base signals and test signals.

Abstract: A monolithically integrable semiconductor circuit having an input section into which respective electrical signals which are to be evaluated and which have been provided by groups of binary pulses are serially feedable, includes a clock-controlled shift register in the input section, the shift register being operable by shift pulses from the controlling clock thereof. The shift register has a plurality of register cells corresponding in number at least to the number of binary digits of the groups of binary pulses. The semiconductor circuit also includes a logic circuit, at least two of the register cells having an output operatively connected to the logic circuit for controlling the logic circuit.

Abstract: This disclosure relates to a timing circuit for a digital display, which circuit includes a series of counters, each having four stages such that each counter will drive the next stage only when it has progressed from zero to seven. By reading out the state of each stage of the respective counters, selected counts can be decoded from only two of the respective stage readouts.

Abstract: A method is provided for measuring a single-shot time interval using startable oscillators to replicate indefinitely the time interval for averaging. Also provided is a circuit for automatically selecting a proper ratio of division to ensure that the interval being measured is less than the period of replication.

Abstract: To record an indicating signal on a record medium, the actuation of a cue signal recording switch is detected, and then the count of a cue signal cycle counter is sensed to determine if it has reached a preselected count. This counter is incremented by one count until the preselected count has been reached, whereupon it is reset to an initial count, and a cue counter is incremented by one count. Then, the count of the cue counter is sensed to determine if it is less than a particular count and, if so, a cue signal is recorded. If the cue count is not less than the particular count, the recording of the cue signal is terminated, thus representing one type of indicating signal. Recording of the cue signal continues until the cue counter reaches its particular count, even if the cue signal recording switch is deactuated. The foregoing steps are repeated substantially periodically in accordance with the programmed instructions of a processor.

Abstract: A plurality of counters are connected with a plurality of correction terminals for independently correcting counts of the counters. An initializing circuit is connected between initializing terminals of the counters and the correction terminals. An initializing signal generator is connected between an input line from the power source and the correction terminals, for initializing the counters to predetermined counts only when signals are simultaneously applied to the correction terminals.