Abstract: A method for identifying a measured value of a velocity or speed of an object where a measured value call-in can occur at any time. A chronological spacing of measuring pulses of a speed sensor is measured and a measured value is formed therefrom. The measurement is carried out until either a measured value call-in occurs, a maximum number of measuring pulses is registered, or a maximum measuring duration is exceeded. When no measuring pulse or only one measuring pulse is registered, a distinction is made in the formation of the measured value as to whether a measuring duration corresponding to a minimum velocity or minimum speed is upwardly or downwardly crossed. An initial counter reading is stored at every measuring start and at every first registered measured pulse. A final counter reading is stored at every further registered measuring pulse until either a measured value call-in occurs or the maximum measuring duration is exceeded.

Abstract: A method of measuring the duration of a selected pulse in a pulse train produces a pulse count enable logic signal in response to a start pulse to enable a first down counter to count transition points in the pulse train. The pulse count enable logic signal has a duration at least as long as two sequences of pulses in the pulse train. The first down counter counts down from a predetermined initial count representative of the selected pulse in the pulse train and enables a second counter when the count corresponding to that selected pulse is reached. The second counter is used to count high speed clock pulses until the end of the selected pulse in the pulse train. The final output count of the second counter is then used to calculate the duration of the selected pulse.

Abstract: A programmable counter or frequency divider includes the combination of a fixed modulus prescaler (110) and a programmable divider (120, 130, 140, 150, 160) in which the prescaler provides more than a single clock phase to the programmable divider and the programmable divider utilizes the multiple clock phases to allow operation in a true fractional-integer mode. The overall combination of the prescaler and programmable divider functions as a programmable divider for which the minimum increment in the overall divider modulus is less than the prescaler modulus, but the maximum clock frequency usable is the maximum clock frequency of the prescaler.

Abstract: A circuit for synchronizing digital signals with alternating current includes a first counter that repetitively starts a first counting sequence at a predetermined phase point in each AC line cycle and effects the sequence at a high frequency rate thereby generating a total count during each line cycle. The total count is then divided by a dividing integer to produce a count number. A second counter repetitively starts a second counting sequence at the predetermined phase point and effects the second sequence at the high frequency rate up to the count number continuously during each line cycle. A decoder responsive to the second counter produces a digital output signal at one or more predetermined points in preselected second counting sequences during each line cycle.

Abstract: A circuit for generating clock signals includes a reference clock signal generator and a 1/N frequency divider for generating 1/N frequency divided clock signals. An up-counter counts the 1/N frequency divided clock signals until the occurrence of a first event. A programmable counter receives both an inverted count result as an initial value from the up-counter and the reference clock signals and counts the reference clock signals up to a predetermined count. When the programmable counter reaches the predetermined count it outputs a carry signal and is reset back to the initial value. As the programmable counter again counts from the initial value to the predetermined count, it again outputs a carry signal. These plurality of carry signals can be counted to provide a count corresponding to the amount of time between the occurrence of plurality of events.

Abstract: A dividing mechanism for use in frequency synthesizers: comprising:a two modulus divider system having a first and second counter for providing respective programmable count totals A, M, and first counter being coupled to a dual modulus device providing moduli of n and n+1 whereby the two modulus divider system provides a division ratio of (Mn+A) for incoming signals:first and second input means for receiving first and second programming number signals N, Q, synchronization means for receiving a strobe signal from a further counter which provides a count total P, and logic interface means responsive to said first and second input means and said synchronization means to provide programming number signals A, M to said two modulus divider system, the logic interface means being such that in the absence of said strobe signal the two modulus divider system provides a count total C.sub.

Abstract: A counter/timer circuit for a microcontroller includes a central register and two auxiliary registers each having transfer outputs and counting inputs. Bistable output storage elements are each connected to a respective one of the transfer outputs. Interrupt request flags are also each connected to a respective one of the transfer outputs. Start/stop elements are each connected to a respective one of the counting inputs. Input control blocks are each connected to a respective one of the start/stop elements. First reload, capture and compare units are connected between one of the auxiliary registers and the central register, and second reload, capture and compare units are connected between the other of the auxiliary registers and the central register.

Abstract: A signal distinction circuit comprises a clock signal generating circuit for generating a clock signal whose frequency is longer than that of a pulse signal corresponding to a discrimination signal applied to a counter as an actuating signal; and an arithmetic circuit for operating the pulse signal and the clock signal, and generating an output signal according to the presence or non-presence of the discrimination signal so as to forcibly drive a detecting circuit to which an output signal of the counter is applied, whereby the detecting circuit can be forcibly driven irrespective of the condition of the counter when the discrimination signal is not applied thereto.

Abstract: As the incrementer of the invention comprises a shift register for its lower order bits, while its higher bit portions are constructed in the same way as a conventional incrementer, the incrementer can give output signals directly to a memory and the like without the necessity of decoding the same, and the incrementer is free from carry propagation delay possibilities, which assures an improved rate of operation of the incrementer as a whole.

Abstract: A high resolution event occurrence time counter includes a free running counter which is responsive to a clock signal and which provides count data that varies in response to the clock signal. A first register stores the count data of the free running counter. The first register provides first register data representative of the count data stored in the register. A second register stores the first register data and provides first time of arrival data representative of the first register data stored in the second register. A third register stores the count data of the free running counter. The third register provides second time of arrival data representative of the count data which is stored in the third register. A clock edge encoder determines whether an event occurred during the first half cycle of the clock signal or during the second half cycle.

Abstract: A synchronous programmable binary counter has a parallel section and a serial section, with the length (in bits) of the serial section being the same as the modulus of the parallel section. The parallel section counts on system clocks and produces two outputs. A parallel terminal count output is produced each time the parallel section count reaches a programmed value. A frame output is generated every time the parallel section reaches its maximum count and starts counting again. The serial counter section decrements its programmed value by one each time it receives a frame signal from the parallel section. This subtraction is accomplished by a half-adder and associated borrow flip-flop. The borrow flip-flop is set by each arrival of the frame signal. Between frame signals, the decremented programmed value is circulated in a shift register as the serial subtraction process is performed.

Abstract: A timer which can be used to provide interrupt signals at predetermined but variable periods for multi-tasking microcomputers or serial data acquisition in pagers comprises a plurality of modulo counters. Each modulo counter has selectable clock inputs and has an output coupled via switches to a NOR gate and to the other modulo counters. Programmable configuring means control the switching means to configure the counters so as to produce desired outputs at the logic gate. The configuring means can also reset the modulus of the modulo counters to any desired value. Thus, the timer produces variable interrupt signals with little or no overhead processor time.

Abstract: Sampling pulses for determining a series of measurement periods are each synchronized, by a synchronizing circuit, with one of a plurality of input signal pulses to be measured. A first counter responds to the synchronized sampling pulse to start the counting of the input signal pulses. When the first counter has counted a predetermined number M of input signal pulses, a second counter starts counting the input signal pulses at the initial value M and stops the counting in response to the next synchronized sampling pulse. The count value of the second counter is applied to a display during the next counting of the input signal pulses by the first counter up to the predetermined number.

Abstract: An electronic signal synchronization apparatus useful with radars and other electronic systems requiring synchronizing signals provides, for a range of N pulses, M sets of synchronizing signals which occur at M different range event pulse counts. The signal synchronization apparatus comprises a microprocessor and a synchronizer, the latter including a range pulse counter, a range memory, an event counter and an event memory. The range memory, preferably a RAM, is connected for outputting an event count enabling signal each time the range counter reaches an event pulse count. The event counter increments one count each time a count enabling signal is received from the range memory. At each event count, the event memory outputs the corresponding set of synchronizing signals. At the Nth range pulse count, the event memory provides an END OF RANGE signal which resets the range and event counters to thereby enable the counters to repeat the counting as many times as is necessary.

Abstract: A unique timing system is provided which allows for a user to program timing events with variable periods and edges from a fixed frequency clock, and having resolution greater than that of the fixed reference frequency. Delay elements, which are inherently expensive, inaccurate, and require repeated calibration, are minimized.

Abstract: An angular position detector for an internal combustion engine includes a toothed wheel with a missing tooth and a sensor providing a pulse train as the teeth pass the sensor. To provide an accurate datum position signal a micro-computer receives the pulse train and outputs the datum signal when the period between successive pulses is significantly shorter than the preceding period.

Abstract: The digital phase-locked loop circuit extracts the clock signal from a serial flow of coded data by operating so as to determine the phase of the received signal and comparing this phase with that of a locally-generated signal. The error signal obtained from the comparison is digitally filtered and used to correct the phase of local signal. The error with respect to the signal extracted from a prior data stream is stored and used to effect corrections even in the absence of the data flow at the input or in presence of long zero sequences.

Abstract: A look ahead terminal counter and a method for generating a terminal count output signal are disclosed. The counter comprises a plurality of counter registers connected to counter enable circuitry for sequencing the registers at a predetermined counter rate. Terminal count enable circuitry is connected to the counter circuitry, e.g. at the input ports of the counter registers, and is operative to generate a terminal count enable signal when those input ports are at a predetermined state. The terminal count enable signal and clock signal are communicated to an output register operative to generate a terminal count output signal when a clock signal is received during the simultaneous presence of the terminal count enable signal.

Abstract: A pulse generator with adjustable pulse frequency, pulse width and pulse delay contains a start-stop oscillator (1) whose oscillator pulses are counted by a counter (2) in adjustable counting cycles. After each counting cycle, the oscillator (1) is shut down for an adjustable time interval. The pulses of the output signal of the pulse generator are produced at the occurrence of a predetermined count value, and the end of these pulses is essentially determined by a second predetermined count value. As the oscillator (1) has a fixed operating frequency and for the purpose of frequency interpolation is periodically shut down during short time intervals and then restarted, a pulse generator is obtained having very small frequency deviations over a wide frequency spectrum.

Abstract: An improved duty cycle timer provides a duty cycle control signal having alternate "on" and "off" intervals of different logic states. The timer utilizes integrated circuitry having first and second independent clock sources respectively driving first and second multistage, binary counters. One counter measures the "off" interval and the other counter measures the "on" interval. Each counter provides a signal representative of the completion of the interval which it measures, and that signal is connected to a resetting input of the opposite counter for initiating the measuring interval of that opposite counter. Typically, one interval is longer than the other. The duty cycle control signal is provided by the output of one of the counters. In an illustrated embodiment, the duty cycle timer controls operation of a defrost mechanism for a refrigeration circuit and the "off" interval is longer than the "on" interval.

Abstract: A multi-mode counter network and a method of testing the operation of the multi-mode counter network are disclosed. The multi-mode counter network comprises a counter circuit formed of a plurality of counter registers and a multiplexer circuit formed of a plurality of multiplexers wherein said multiplexers are connected to and associated with one of the registers and are operative to selectively vary the input signal communicated to the associated register such that the registers operate in one of a plurality of operational modes. By controlling the selection of the input signal communicated to the registers the network may be alternately configured to perform traditional counting functions or may be configured to provide a serial signal path for communicating a test pattern through the registers and multiplexers to test the operation of the multiplexers and registers. The test pattern is communicated through the circuit, bypassing counter enabling circuitry, and thus independent of the network counter rate.

Abstract: The root mean square value of sensed current within a protected circuit is calculated. A frequency multiplying circuit produces a pulse stream having a frequency proportional to the square of the amplitude of an analog signal representation of the circuit current. A root mean square value over a prescribed interval is developed from the squared current value.

Abstract: An electronic integrator for integrating a linear voltage signal utilizes a voltage-to-frequency converter for converting the voltage to input frequency. A binary counter counts pulses of the input frequency. The binary counter generates a first operating frequency which is applied to a scaling circuit and another calibration frequency which has a much higher rate than the operating frequency. Both, however are proportional to the input frequency. The scaling circuit scales the operating frequency to a selected extent to form a counting signal. Using the double pole switch, either the calibration frequency or the counting frequency are applied to a pulse counter which is either used to integrate the input voltage signal by counting up pulses of the scaled counting signal, or the integrator can be calibrated using the calibration frequency which quickly increments the pulse counter.

Abstract: In a data processor system, a method for transferring data to and from a random access memory (RAM) with a serial data interface and having accessible word location includes the steps of generating a timing pulse consisting of contiguous time slots each defined by the Nth count of a counter, generating an initial address signal in the first occurring contiguous time slot of the timing pulse with the initial address signal including a read/write command signal, incrementing the initial address signal at each Nth count of the counter to form data address signal, accessing memory locations in the RAM with the initial address signal followed by said data address signals, supplying data words to or reading data words from the RAM at the word locations accessed by the data address signals in response to each Nth count of the counter and when the data address signal contains a write command or a read command signal, respectively.

Abstract: To distinguish between the two fields in a television signal, television synchronizing pulses are applied to a pulse interval detector. The output signal of the pulse interval detector assumes a first signal state when pulse intervals are measured which are located between first and second limit values, and a second signal state when the pulse intervals are outside these limit values. The pulse interval detector is connected to a time measuring element which counts the pulse intervals of the synchronizing pulse when the first signal state is present. The time measuring element produces a field identification signal in dependence on the fact whether, for example, the first signal state is present for a longer period of time for one field than for the other field.

Abstract: Counter circuit apparatus which sequentially re-allocates lower-order counting operation in order to extend counter life. The counter is comprised of a plurality of lower order counters and at least one higher order counter. A count selection circuit is coupled to the plurality of counters which controls the counting thereof in response to applied event input signals. A map control circuit is coupled between the higher order counter and the count selection circuit which controls the count selection circuit in response to signals derived from the higher order counter. The map control circuit sequentially enables a predetermined one of the lower order counters to count individual ones of the applied event input signals. A count unscrambling circuit is coupled to the plurality of lower order counters and the map control circuit which produces an ordered count output signal that is indicative of the number of event input signals counted by the counter.

Abstract: A test signal generator for generating signals for use in a high definition television, the apparatus including means for storing a plurality of pattern segments which are representative of selected portions of the test signal to be generated, and means for retrieving predetermined ones of the stored pattern segments and for repeating or holding selected ones of the retrieved pattern segments in a predetermined sequence in order to construct, in real time, the entire test signal waveform, and also including means for converting the sequence of retrieved pattern segments into the test signal.

Abstract: A frequency synthesizer which has a constant resolution over an octave frequency range is disclosed. The frequency synthesizer has a presettable high speed counter, a low speed counter, an adjusting counter, and a count selector. The low speed counter provides a first output signal whose frequency is rapidly alternated between two closely-spaced frequencies so that the average frequency of the output signal is the desired frequency. The adjusting counter determines the period of time that each of the closely-spaced frequencies is present at the output. The count selector determines the frequency of each of the two closely-spaced frequencies. The frequency synthesizer also has a phase splitter and provides a second output signal which is also of the desired frequency but which is phase-shifted by ninety degrees from the first output signal.

Abstract: The frequency divider includes a first or prescaling counter which selects between first and second frequency division factors, in response to a first control signal, and then divides an input signal frequency responsive to the first control signal. A second and programmable counter frequency divides the output of the first or prescaling counter by a third frequency-division factor. A third and programmable counter frequency divides the output of the first counter by a fourth frequency-division factor which is smaller than the third frequency-division factor. A switching control circuit then converts the output of the third counter and supplies the converted signal to the first counter, as the first control signal. The digital frequency divider is suitable for use a part of a phase-locked loop frequency synthesizer.

Abstract: A pulse generator (2) provides output pulses which are phase-synchronized to pulses from an external trigger source (3) through the use of gated delay lines (13) used as clocks. Output mode versatility is achieved by storing desired pulse output waveforms in a random access memory device (26). Expanded output resolution is achieved via an arrangement of three independent counters (10, 20, 24). A fourth independent counter (40) is used for burst counting. A pair of converters (36, 38) are used to provide an output amplitude monitor/test capability.

Abstract: A gray code counter is produced from a binary code counter by connecting each output of the binary counter to a "toggle" flip-flop. Each toggle flip-flop has a toggle input connected to its corresponding binary output. The output of each toggle flip-flop changes state (i.e. "toggles") only when its corresponding binary code bit makes a transition from a first level to a second level (i.e., it does not change state when its corresponding binary code bit makes a transition from the second level to the first level).

Abstract: A circuit is described for recovering binary data from an input signal which may be phase coded and received intermittently and nonsynchronously incorporating an edge detector for detecting transitions of the data from a 0 to a 1, a counter which may be reset upon detection of a data transition, a second counter which may be reset upon the first counter reaching a predetermined value, the second counter being permitted to free run up to a predetermined value, a circuit for generating data in synchronous with the output of the second counter, and a squelch circuit for inhibiting the output of the generated data in response to output of the counters.

Abstract: Characteristics of a pulse sequence, such as frequency, are controlled in a simple circuit without requirement for specific storage components. The cumulative effect of a sequence of control signals is maintained by providing a phase shift between a pair of waveforms. The phase shift between the waveforms is used to provide a number of control pulses to the circuit for varying the desired characteristic. In a particular embodiment, control signals are externally provided for varying the phase shift between two waveforms. In response to the phase variation, a number of control signals are provided for adding or deleting pulses to a pulse stream. The use of feedback control loops results in repeated addition and/or deletion of pulses to or from the pulse stream, thereby varying the output frequency in accordance with a one time input of the external control signals.

Abstract: A programmable high resolution timing system includes a selectable modulus prescaler counter. In one embodiment a high frequency clock is coupled to a prescaler counter which provides an output signal every predetermined number of clock pulses. The prescaler is coupled to a period counter which provides a period signal after a predetermined number of prescaler output signal pulses. The prescaler and period counter are coupled to a memory which stores data corresponding to the selected modulus of the prescaler and the number of counts by which the period counter output signal is to be delayed. The period resolution is thus made substantially equal to the resolution of the high frequency clock by varying the prescaler modulus at programmable intervals.

Abstract: A method of making measurements on a machine having a movable probe for measuring a part in which a present location of the probe is maintained and a past location (e.g., a part measurement) of the probe is also maintained (stored) and advantageously displayed. The measuring apparatus includes two sets of storage members, with the present position information of the probe stored in one set. The present probe position information is transferred to the other storage members in response to a control signal. The control signal, such as an electrical signal indicating contact with an object, causes measurements to be transferred from the one set of storage members to the second set of storage members and, advantageously, the transfer of further information to the second storage members may be locked out of a predetermined time or until an event occurs (such as a resetting signal).

Abstract: At the inception of a time interval whose duration is to be measured, pulses whose rate may be varied are applied to a first counter. A second counter controls the rate of the pulses applied to the first counter. An overflow sensing circuit is connected to the output of the first counter for, in response to each overflow signal at the output of the first counter, incrementing the second counter which then causes pulses having a new rate to be applied to the first counter and for, concurrently, presetting the counter to a new count. The new rate is equal to 1/N the old rate and the new count is equal to 1/N the count in the first control prior to the overflow. The elapsed time information in the circuit is therefore always valid.

Abstract: A programmable counter system of the swallow operation type using binary counters is disclosed. The counter comprises a prescaler for frequency dividing an input signal by a frequency division factor "2.sup.n -1" or "2.sup.n ", upper and lower order bit counters for counting down an output signal from the prescaler, a flip-flop for selecting either the frequency division factor "2.sup.n -1" or "2.sup.n " according to the logical level of the output signal of the counter A or B, and inverters for level inverting programming data and applying them to the lower order bit counter A, thereby setting a division number of the counter A to a complement of the binary code of the programming data.

Abstract: The counting circuit described issues a numerical information which is a non-linear function of the number of pulses applied to its input.The circuit comprises dividers which divide by integers K.sub.i the pulses applied to their inputs. A first selector connects the output of one of the dividers to the input of a counter in response to a first signal. The content of the counter is compared with numbers k.sub.i by comparators. The output of one of the comparators is connected to a control circuit by a second selector controlled by a second signal issued by the control circuit in response to a comparison signal.

Abstract: The clock signal to a fine delay shift register is divided by the number of fine delay bits for application to a coarse delay shift register such that two serially connected shift registers can provide a range of delays equivalent to a shift register having a number of bits equal to the product of the bits of the two shift registers.

Abstract: In an instrument for converting the rotary motion of the feed shaft of a machine to a pulse train having a direction component and for counting and displaying the pulse train as counted by a reversible counter, a digital measuring device arranged such that its reversible counter does not count pulses generated by the idling rotation of the feed shaft due to play in the feed system of the machine, thereby digitally counting and displaying the correct transfer distance or feed ratio of the transfer unit of the machine.

Abstract: A target processor utilizing a feedback loop to maintain a constant false alarm rate for variable level video input signals with noise or noise plus clutter on the input signal. The processor includes three serially connected stages of binary coincidence detectors which comprise a threshold detector for processing video signals which exceed a threshold level, an M of N detector for providing an alarm for each range gate having a count of M or greater pulses, and a P of Q detector for generating a target alarm after at least P or greater frequencies have been transmitted.

Abstract: A method of sampling accurately the instantaneous content of a high speed counter without interrupting the counting process is provided. The method is applicable even when the higher order digits of the counter are constructed by slower switching circuits configured in either a synchronous or ripple-through arrangement. The switching and carry propagation times of these higher order counters need not be shorter than the time between successive events being counted. Sampling of the contents may be made repeatedly in the interim without affecting the totality of the final count.

Abstract: The counter circuit is adapted to counting high frequency pulses and to being read while counting said pulses. It comprises a plurality of pulse counting stages of increasing numerical significance, and read means for reading the states of said stages. Said plurality of pulse counting stages comprises lower significance stages (10.sub.1 to 10.sub.4) connected as a synchronous counter (10) and higher significance stages (12.sub.1 to 12.sub.n) connected as a ripple counter (12). The synchronous counter is so connected that it counts the high frequency pulses (H) directly, and that any change of state required in any of its stages on counting a pulse occurs substantially simultaneously with the arrival of said pulse. The ripple counter is so connected that it counts count cycles of the synchronous counter, and that it takes a long time relative to the interval separating two successive high frequency pulses for a change of state to propagate, where necessary, from the least significant stage (12.sub.

Abstract: A system for converting the frequency of a pulse train to a binary number includes an output counter which converts the pulse train to the binary number. Sampling time periods are applied as pulses to a comparator through another counter. The number of desired sampling periods is set into the comparator. The comparator enables the counter during the sampling time periods and inhibits the output counter on the termination of the total sampling time periods. The output of the output counter, therefore, is a binary representation of the frequency of the incoming pulse train during the total sampling time period.

Abstract: A switching circuit with a time-delay device comprises a pulse generator, and a counter which receives pulses therefrom. The overflow output of the counter transmits a counter signal after receiving a predetermined number of pulses. The counter is provided with a holding circuit for maintaining the counter signal up to the time of resetting and renewed start of the counting operation. The resetting input of the counter receives a signal either by way of an inverter or directly. The overflow output of the counter is connected with the output of the time delay device, either directly to obtain a delayed start or by way of an inverter to obtain a delayed termination.

Abstract: A circuit for controlling the application of a timing pulse to a count down chain where the contents of the count down chain are read-out in stages and asynchronously with respect to the application of the timing pulse. The control circuit ensures that a timing pulse is not applied during the read-out of the contents of the count down chain.

Abstract: A control system for an acreage counter, controllable by an electrical logic condition, includes: a flip-flop having enable logic condition output upon being set, and an inhibit logic output upon being reset; an enable counter and an inhibit counter connected respectively to the set and reset inputs of the flip-flop; an enable clock and an inhibit clock connected respectively to the enable and inhibit counters; and sensors or switches connected to the respective counters and cooperating respectively with an operating lever or operating switches of an agricultural implement to actuate the associated counters upon change in the status of the operating controls. The clocks and counters function to delay setting or resetting of the flip-flop for a selected time so that minor adjustments may be made to the working position of the implement without falsely initiating or interrupting the acreage counter.

Abstract: A frequency synthesized transceiver capable of tuning to a plurality of communication channels is disclosed. The transceiver includes a receiver section and a transmitter section which are coupled to the synthesizer which generates the appropriate injection signals to achieve tuning. The frequency synthesizer includes a multiposition switch which accesses various addressable memory locations in a programmable read-only memory where the appropriate divisors are stored to cause tuning of the synthesizer to the appropriate communication channel. A zone selector switch enables grouping and easy retrievability of channels. The divisors are supplied to a single synchronous binary swallow counter which works in conjunction with a dual modulus prescaler to monitor the frequency output of the voltage controlled oscillator. A programmable divider coupled to a reference oscillator source is compared with the output of the synchronous counter in a digital and analog phase detector.

Abstract: A system for reading out the contents of multiple counters onto a common bus comprising a plurality of synchronous binary counters arranged in a ring with each counter having N corresponding stages each having an output terminal on which appears the contents of the stage, an input terminal, and a clock pulse input terminal, with each stage responsive to a clock pulse supplied to its clock input terminal to transfer the signal logic level on its input terminal to its output terminal and with the output terminals of the stages of a given counter comprising the common bus. Also provided is a clock pulse source for supplying clock pulses to all of the clock input terminals and a switching signal source for generating a switching pulse. A switch associated with each stage is responsive to the switching pulse to connect the output terminal of each stage to the input terminal of the corresponding stage of the next adjacent counter in the ring of counters.

Abstract: The swallow counter includes a two modulus prescaler which selectively divides a frequency of an input pulse according to a signal level of a control signal for producing a frequency divided signal, a first programmable counter which starts counting in response to the frequency divided signal to produce a first code signal, a second programmable counter which starts counting in response to the first code signal for producing a second code signal, a first code detector for detecting a specific code signal of the first and second code signals to produce a first pulse signal, a third programmable counter which, in response to the frequency divided signal, starts to count for producing a third code signal, a second code detector for detecting a specific bit of the third code signal for producing a second pulse signal utilized as a reset signal of the first to third programmable counters, a flip-flop circuit for selectively outputting a reset or set signal in response to the first or second pulse signal, and a per