Abstract: Disclosed is a divide-by-m counter for generating an ouptut clock signal having a fifty percent duty cycle from a higher frequency source clock signal having m cycles for each single cycle of the output clock signal and wherein m may be an odd or even integer number, the divide-by-m counter including a modulo binary counter for counting up to a predetermined number, circuitry for presetting the modulo binary counter by another predetermined number, counter clock selector for providing a counter clock signal to the modulo binary counter which, when m is odd, will be either an non-inverted source clock or an inverted source clock based upon the occurrence of either the HIGH or LOW intervals of the output clock, and interval defining circuitry for defining the beginning of such HIGH and LOW intervals of the output clock based upon the occurrence of a ripple carry pulse from the modulo binary counter.

Abstract: In a frequency-dividing circuit for producing an output having a frequency half that of its input, a pair of terminals of a latch circuit are connected to input terminals of a pair of amplify/delay means, and are also connected to receive through a pair of transistors, the outputs of the amplify/delay means. A single-phase input signal is input to the control electrodes of the transistors to turn on and off the transistors. When the transistors are turned from off to on, the output states of the amplify/delay means are transferred through the transistors to invert the latch circuit, and the states of complementary terminals of the latch circuits are in turn transferred through the amplify/delay means to invert the output states of the outputs of the amplify/delay means. When the transistors are turned from on to off, no change occurs in the states of the circuit. In this way, the states of the circuit are inverted each time the transistors are turned from off to on.

Abstract: A device for doubling or dividing by 2 the flow rate of series bits comprising a succession of first one-bit registers (R4-R0) actuated at a frequency F; a second register (R) actuated at a frequency 2F; an input terminal (IN) connected to the input of the first (R4) of the first registers and, through a first gate (T5), to an internal line (L) connected to the input of the second register; first multiplexers (M4-M1) connected to the input of each second (R3) to last (R0) of the first registers for selecting either the output of the preceding register, or the internal line, or still the output of the second register; a second multiplexer (M), which selects either the output of the last (R0) of the first registers, or the output of the second register, or filling bits; second transfer gates (T4-T0) between the output of each first register and the internal line; and means for controlling the various gates and multiplexers.

Abstract: A frequency division network is disclosed in which a sinusoidal signal is converted to a digital format for frequency division and then converted back to the sinusoidal format, the sinusoidal output waveform having low phase noise. In a preferred embodiment the frequency conversion takes place in an m-fold plurality of edge triggered flip-flops, connected to divide by two, and clocked by the sinusoidal waveform. Each flip-flop is subject to jitter causing phase noise, which is minimized when the output of two sets of four flip-flops are averaged, and then filtered to obtain the sinusoidal fundamental. When a crystal filter having a very narrow pass band is employed, the phase noise is further reduced. The frequency division network uses low cost components and the phase noise of the output waveform approaches that of a stable crystal oscillator.

Abstract: An integrated semiconductor device including a frequency divide-by-two circuit comprising an inverter stage and a switching transistor (T2) which is controlled by a microwave input signal (E). The divider circuit includes an oscillator stage in that the inverter stage is at least equipped with a reactive element which in combination with the inverter stage forms a negative resistant network. The switching transistor is connected in parallel with this reactive element and the transmit time .tau..sub.0 of the switch is less than the transit time .tau..sub.2 of a signal propagating through the reactive element.

Abstract: A frequency conversion system for converting a pulse period into a frequency value by calculating a reciprocal value of a binary digit value of a pulse period from a remote period counter. The system uses the binary digit as a divisor and successively adds the divisor until a running sum results in (1) greater than a chosen dividend value or (2) the number of additions needed to reach a chosen dividend value is reached. A second embodiment is included which contains a local period counter.

Abstract: A clock frequency multiplication circuit. A circuit is described for receiving a clock signal of a first frequency X and multiplying the frequency of the signal by a multiple N to produce a signal of frequency N times X. The circuit is particularly useful in, for example, computer systems in which it is desired to upgrade certain components such as a processor to operate at an increased clock speed without modifying the clock speed of the system clock and where it is further desired to provide synchronization between the system clock and the processor clock.

Abstract: A digital logic circuit (100) is provided for multiplying, such as doubling, the frequency of an input clock pulse sequence of period T. The circuit in one embodiment includes complementarily clocked first and second chains of cascaded delay elements (12, 13 in A1, A2, A3, . . . and B1, B2, B3, . . . ). Further, the n'th one of set of clocked latches (14, 15, 16 in A2, A4, A6, . . . ) derives its input from the 2n'th one of the delay elements in the first chain, where n is a running integer index (n=1,2,3, . . . ). The circuit (100) also includes a set of two-input logic gates (11), one of whose inputs (IN) is the output (OU) of a separate one of the logic elements (12, 13) in the second chain and the other of whose inputs is an output (MO) of a separate one of the latches (14, 15, 16). Each of the outputs of these logic gates (11) is fed to a multiple input output logic gate (25) whose output has a desired double-frequency feature (edges at T/4) relative to the frequency of the clocked pulse sequence (CLK).

Abstract: A system for determining the position of movable machine parts including an incremental pulse generator for generating angular-speed pulses includes a computer. At least one counting circuit via which the incremental pulse generator is connected to the computer counts the generated angular-speed pulses.

Abstract: A method for modifying the frequency of a clock signal includes the steps of producing a clock signal having voltage pulses which occur at a first frequency and producing a control signal having voltage pulses which occur at a lower frequency. The frequency of the voltage pulses in the control signal is incremented in successive time intervals and the clock signal and control signal are combined such that one voltage pulse in the clock signal is deleted for each voltage pulse in the control signal. This results in a modified clock signal having a frequency which may be ramped up or down depending upon the initial frequency of the control signal and the direction in which the frequency of the control signal is incremented.

Abstract: A clock circuit for generating two clock signals, one (CLK) having stretched clock phases on a cycle by cycle basis, and the second (2X CLK) being a clock signal having a frequency twice the frequency of the first clock signal which is phase and edge coherent with the first clock signal, including the stretched clock phases. The circuit inputs a signal generated by an oscillator which is twice the frequency of the CLK signal which is then used to generate the CLK signal for use by a microprocessor, either phase of which can be stretched on demand, while the second 2X CLK signal remains phase coherent with the microprocessor CLK signal.

Abstract: A digital peak noise reduction circuit for reducing peak noise of an input digital signal having variable levels corresponding to a predetermined sound volume range. The circuit includes a division circuit for dividing the level of the input signal; a ROM for supplying a plurality of data expansion rates, each expansion rate being defined by a relationship between a different specific range of input digital signal level and the predetermined range; a multiplier for multiplying the digital audio data with the reciprocal related data output from the ROM; a multi-stage shift circuit for supplying a plurality of data compression rates, (each compression rate correspond to the expansion rates of the ROM) and for producing an output signal having a level corresponding to the selected compression rate; a de-emphasis circuit for compensating for specified frequency characteristics of the output signal; and a feedback circuit for supplying the output signal to the division circuit for controlling the ROM.

Abstract: A programmable system for providing a programmable ratio of output pulses to input pulses. The programmable system receives pulses from an electric power meter and outputs a programmable number of pulses representing a number of kilowatt hours consumed. Various electric power meter disk patterns can be processed by the programmable system. The programmable ratio can be applied via input pins and/or via an external memory.

Abstract: An asynchronous nonlogical counting device includes at least a first counter and a second counter connected in cascade. The first counter has a frequency dividing ratio of 2.sup.n where n is a natural number. A control unit produces a control signal based on the count value of the first counter. The second counter has a variable frequency dividing ratio which is based on the control signal. The counting device can be made programmable by substituting a comparator circuit for the control unit. The comparator compares the output of the first counter to an instruction signal from an external source.

Abstract: A frequency doubler operating where the predetermined duty cycle is essentially 50% in response to a series of input pulses with a given frequency and a duty cycle essentially of 50%. The circuit includes a means to generate a ramp signal which the ramp portion forms as a function of the repetition of the input pulses in response to the input pulses, an exclusive-OR logic to evaluate the exclusive-OR of the output from the ramp signal generating means and the input pulses in response to the output from the ramp signal generating means and said input pulses. A means, which is coupled to the ouptut of said exclusive-OR logic, integrates the output of the exclusive-OR logic, adds it to the ouptut from the ramp signal generating means, and feeds it back to the input of the exclusive-OR logic. A means, which is coupled to the integrating and feedback means, and causes the duty cycle of the output from the exclusive-OR logic to become essentially 50% by applying reference voltage.

Abstract: A method and apparatus for effecting photometry from plural points of an automatic exposure camera includes the provision of photometric means which determines the brightness of a relatively limited region of an image field. Photometry is successively made of the brightness of an object being photographed at a number of desired points thereon, utilizing the photometric means, and corresponding photometric values are derived. An average of these values is taken, and transmitted to exposure control means, thus effecting an exposure control in accordance with the average.

Abstract: An analog/digital voltage controlled oscillator includes a voltage to pulse converter which responds to a control voltage to generate appropriate control pulses to change the mode of operation of a divider to thereby vary the output frequency of the oscillator.

Abstract: A frequency multiplier is disclosed for producing an output signal having a frequency greater than the frequency of an input signal by a factor (1+N/M). The frequency multiplier comprises an input terminal and an output terminal; and a plurality of frequency multiplying stages, coupled between the input and output terminals, each producing an output signal having a frequency greater than the frequency of its input signal by a factor having the general form (1+1/P).

Abstract: A clock frequency divider for generating a basic clock signal which provides operation timing for a semiconductor integrated circuit operating in accordance with a program. The clock frequency divider comprises a frequency-dividing factor register for storing a frequency-dividing factor which can be rewritten by the program, and a frequency-dividing circuit for frequency-dividing a source clock signal having a fixed frequency in accordance with the frequency-dividing factor stored in the frequency-dividing factor register, whereby a basic clock which provides a processing rate optimum for a program to be executed being obtained.

Abstract: A dividing mechanism for use in frequency synthesizers: comprising:a two modulus divider system having a first and second counter for providing respective programmable count totals A, M, and first counter being coupled to a dual modulus device providing moduli of n and n+1 whereby the two modulus divider system provides a division ratio of (Mn+A) for incoming signals:first and second input means for receiving first and second programming number signals N, Q, synchronization means for receiving a strobe signal from a further counter which provides a count total P, and logic interface means responsive to said first and second input means and said synchronization means to provide programming number signals A, M to said two modulus divider system, the logic interface means being such that in the absence of said strobe signal the two modulus divider system provides a count total C.sub.

Abstract: Generally there is provided circuitry and a method for frequency multiplication of a first signal source including a first counter for counting pulses from a second signal of higher frequency by counting from a loaded value and generating a circuit output each time the first counter resets. A second counter is used to count cycles of the first counter and generate a feedback signal when a predetermined number of cycles have been completed (the system multiplication factor). Calibration is achieved by comparing the end of the period of the first signal to the occurrence of a feedback signal. In response the comparision circuit causes the loaded value to be changed to thereby control the output.

Abstract: A digital integrating mixer is described including a bandpass filter for filtering an input signal, a comparator for comparing the filtered signal to a reference signal to provide an output which may be of one of two values. A cascaded string of D flip-flops samples the comparator output at predetermined times to provide a first and second type of sample. The time interval between any two samples of the same type is an integral multiple of the cycles of the input signal. The time interval between any two samples of different types is different from an integral multiple of a cycle of the input signal. The mixer also includes a counter which counts up when the sample is of the first value and counts down when the sample is of the second value, when the sample is of the first type, and counts in the opposite direction when the sample is of the second type. If the string of D flip-flops samples approximately an equal number of the first and second types of samples, DC offset in the mixer is reduced.

Abstract: A logic integrated circuit of the scan path system comprises a combination circuit and a shift register associated to the combination circuit and including a plurality of cascaded flipflops. The shift register has a scan input, a clock input, a scan control input, and a scan output. A scan input terminal is connected to the scan input of the shift register, and a clock terminal is connected to the clock input of the shift register. A scan output terminal is connected to the scan output of the shift register. Further, there is provided a counter having an input connected to the clock terminal and an output connected to the scan control input of the shift register. This counter has a frequency division ratio equivalent to the stage number of the flipflops in the shift register, so that the shift register is switched between a shift register mode and a normal mode by the frequency division signal from the counter.

Abstract: A method and apparatus for effectively doubling the operational speed of certain digital circuit designs. In particular, a digital clock operating at a first frequency is utilized to effectively drive TTL shift registers at twice the frequency of the digital clock. This effective doubling of the clock speed is achieved without the necessity of resorting to expensive and high power consumption circuit designs.

Abstract: A frequency divider for dividing input pulses by a predetermined number is formed of an input means for receiving input pulses, a plural number of counters, each having a series connection of stages through which a count signal is respectively shifted in response to the input pulses. The numbers of series stages being selected so that they do not have any common divisor and have a minimum common multiple larger than the predetermined number pulse one. The frequency divider also includes a detecting means for detecting common occurrence of said count signals at selected stages of respective counters, and an output means for producing an output pulse in response to the detection by the detecting means.

Abstract: A phase locked loop including a programmable frequency divider with a variable modulus divider (VMD) having two modes of operation, n and n+1, a programmable counter for counting the number of times the VMD divides the input signal and a comparator for comparing the count in the counter to a predetermined number and switching the VMD from the first mode to the second mode when the instant count and predetermined number are equal. The programmable counter provides an output pulse each time the total count equals a selected number. The VMD is a GaAs semiconductor device.

Abstract: A method of and an apparatus for generating a control frequency in which two submultiples of a frequency standard are obtained which differ by unity in the respective frequency division and are mixed so that the contribution of a prior control frequency is reduced form period group to period group while the contribution of the new control frequency is increased from period group to period group. The system provides fine control of frequencies for, for example, driving synchronous motors without requiring excessively high frequency standard oscillators.

Abstract: A pulse train divider circuit includes a first flip-flop (1) whose Q output is connected to the D input of a second flip-flop (2) whose Q output is connected to the D input of the first flip-flop (1). A pulse train to be divided is applied via an input (3) directly to the clock input C of the first flip-flop (1) and via a circuit (4) which delays the pulse train applied to the clock input C of the flip-flop (2) to provide a given phase relationship between the pulse trains at the two clock inputs. The circuit divides-by-two, and the resulting divided pulse trains available at the various outputs have phase relationships depending on the phase relationship of the applied pulse trains at the clock inputs.

Abstract: A method of counting a plurality of pulses representative of randomly occurring events includes the steps of counting the number of pulses, having an amplitude exceeding a first threshold amplitude, which occur during a predetermined sampling period to obtain a first count and counting the number of pulses, having an amplitude exceeding a second threshold amplitude, which occur during the sampling period to obtain a second count. The second count is compared to a predetermined number and the counts for that sampling period are rejected if the second count is too large. If the second count is not too large, the true count is calculated by subtracting the second count from the first count. This counting procedure is repeated for a preselected number of successive sampling periods. After the final sampling period, all of the true counts are added to obtain an accumulated count and the accumulated count is multiplied by a scaling factor to obtain an output count.

Abstract: A counter slip control circuit is described for digital transmission systems wherein the counter uses a feedback circuit to define the permissible counter states. The slip control input modifies the feedback function so that certain counter states are either repeated or skipped. A repeated counter state is equivalent to retardation of the counter output signal phase. A skipped counter state is equivalent to advancing the counter output signal phase. The slip control gate is eliminated from the clock input line to the counter and instead is included in the feedback path which eliminates the skew problem and permits the equivalent of adding clock pulses without the requirement for logic speeds of twice the normal clock speed.

Abstract: A frequency multiplying circuit for a disc controller includes a first time counting unit responsive to input pulse signals for producing a first detection signal when a HIGH level of the input pulse signals is longer than a predetermined length, a second time counting unit responsive to the input pulse signals for producing a second detection signal when a LOW level of the input pulse signals is longer than a predetermined length, and a gate timing determination unit responsive to the produced first and second detection signals for providing a gate signal in response to the first detection signal and for providing another gate signal in response to the second detection signal. First and second pulses are generated responsive to the gate signals and to rising or falling edges of the input signals for providing a frequency multiplied output of the input pulse signals.

Abstract: A method and circuit employ digital techniques in processing an input signal of a first frequency to develop an output signal of a second frequency that is a multiple of the first frequency. During each cycle of the input signal, a presettable down counter (146) is decremented from its maximum value at a rate of 1/T.sub.1. The digital word appearing at the output of the down counter at the end of the cycle is programmed into an up counter (278) that is clocked at a rate of 1/T.sub.2. The frequency of the signal developed at the overflow output (336) of the up counter is divided by two by a flip-flop (342) whose output (348) provides a signal of a frequency which is T.sub.1 /2T.sub.2 times that of the input signal. The frequency of the output signal changes after one cycle of a change in frequency of the input signal. The frequency multiplication factor can be a noninteger value.

Abstract: Method and apparatus for rapid, low-jitter acquisition of a clock signal at a serial communication port. In the absence of communication over the port, and during clock acquisition, a free-running clock is generated for local communication. Following clock acquisition by a circuit which performs coarse phase adjustments, a simple logic network generates refined phase adjustment signals which drive a variable, nominal divide-by-32, counter so that the clock generated thereby is smoothly brought into synchronization with the acquired clock in one bit increments. In a typical application, at most 48 bit periods at the port are required to synchronize the clock, with a clock phase jitter of less than 1.1%.

Abstract: A bipolar clock-controlled bistable multivibrator circuit arrangement having a static memory cell formed of a D-master-slave flip-flop with a first inverted output signal fed back to a data input and with feedback loops, respectively, for intermediately storing output signals of the master and the slave. A dynamic memory cell is formed of the D-master-slave flip-flop with a second inverted output signal fed back to the data input. The second inverted output signal has gate propagation times performing intermediate memory functions in place of the feedback loops and includes a synchronizing device connected between the static and the dynamic memory cells. Means are provided for setting the circuit of the static memory cell in operation at relatively high clock frequencies. Thereby the useful frequency range of the multivibrator is at least doubled.

Abstract: A weighted event counting circuit comprises a cascade connection circuit composed of a plurality of frequency dividing circuit means and a plurality of coincidence detecting circuit means inserted between the frequency dividing circuit means, and input circuit means to supply digital data representing the occurrence of plural events to the coincidence detecting circuit means. The number of occurrence times of the plural events is counted and totalized with weighting.

Abstract: A frequency divide by n circuit, where n is an odd number, which includes means for splitting an incoming clock signal of frequency "f" into two non-overlapping complementary clock signals of frequency "f" and a shift register circuit. The shift register circuit is coupled to the signal splitting means and generates an output clock signal of frequency f/n in response to the two complementary clock signals. The output clock signal has a duty cycle equal to ((n-1)/2+D.sub.in)/n where D.sub.in is the duty cycle of the incoming clock signal. The output duty cycle is substantially independent of processing and operating conditions.

Abstract: Phase quantizer apparatus in an all digital phase locked loop to provide a two-part digital number representing the phase of the input signal (a noncontinuous pulse train) relative to the output signal of the all digital phase locked loop. The phase quantizer comprises a write counter (modulo m counter) and a phase counter (modulo n counter) which receive the noncontinuous pulse train as an input signal. The leading pulse edge in the noncontinuous pulse train increments the write counter and resets the phase counter. The write counter comprises a binary counter and a conversion circuit. The binary counter portion of the write counter was being used and is still being used in the digital communications system to provide address information to the elastic buffer to read data into predetermined storage locations in the elastic buffer.

Abstract: An all digital equivalent to a voltage controlled oscillator with low intrinsic jitter and the absence of sample aliasing within a nonzero bandwidth, the offset (non-symmetrical) digitally controlled oscillator comprising a divider (divide by n or n-1) which is timed from a high speed reference clock, a 2.sup.m counter and a digital comparator. The divider divides the high speed reference clock signal so that for every thirty second cycle of the high speed reference clock a pulse is output from the present invention. The output pulse is input to the 2.sup.m counter and increments same. The 2.sup.m counter counts the number of output cycles (or pulses) that have occurred since the last phase adjustment and comares this m-bit number to the input to the present invention. When the output of the 2.sup.m counter becomes greater than or equal to the input, a divide by n-1 signal is sent to the divider which shortens the output cycle and adjusts the average output frequency and phase. The 2.sup.

Abstract: A digital phase locked loop to function as a stable reference clock given a gapped, or pulse stuffed, input clock signal which may have a frequency offset relative to the nominal specified frequency and a phase jitter relative to the average frequency of the input signal, the digital phase locked loop comprising an input synchronizer for synchronizing the input clock signal to a stable high frequency reference clock. The output of the input synchronizer increments a write counter and resets a phase counter to zero at the begininning of each cycle of the input clock signal. The outputs of the write counter and the phase counter are sampled by a sampling circuit which interprets the sampled data in two's complement form.

Abstract: An improved, high-speed frequency divider circuit (32) is presented. The frequency divider circuit (32) is comprised of three D-type flip-flops (34, 36 38). The three flip-flops (34, 36, 38) are clocked synchronously for higher speed of operation. The design of the frequency divider circuit (32) embodies a sagacious state assignment to minimize the number of bits that change state on any given state transition, thus reducing the possibility of faulty circuit operation.

Abstract: A frequency divider for converting an n-bit periodic counting stream (each period containing a single zero or one bit, respectively, followed by n-1 one or zero bits) into a 2n-bit counting stream includes a two-input NOR gate or NAND gate, respectively, connected for delivering its output to an n-bit delay device, the NOR or NAND gate further connected for receiving the output of the delay device as feedback at one of its two-input terminals and for receiving the n-bit counting stream at the other of its two-input terminals. The output of the delay device is then a 2n-bit counting stream.

Abstract: A frequency multiplier circuit including a circuit element to receive an input signal having a first frequency which is provided to a phase shifting circuit element to provide an intermediate signal resembling the input signal except shifted in phase. This intermediate signal is provided to a logic element which combines the intermediate frequency with the input signal to produce an output signal having a second frequency which is a multiple of the first frequency.

Abstract: A wide band analog frequency divider circuit operable at a high frequency in the GHz band, and a frequency synthesizer utilizing the analog frequency divider circuit. The analog frequency divider circuit comprises an LC series circuit having a capacitor and an inductor connected between the anode and the cathode of a diode, and means for applying a forward bias to the diode. The input signal is supplied from the anode side of the diode, and the output is delivered from the cathode side, or the anode side of the cathode is grounded. The frequency synthesizer is arranged to frequency divide the output of a VCO by the analog frequency divider circuit, and to supply the frequency-divided output to a prescaler. The output of the prescaler is further frequency divided by a programmable divider, and the phase difference between the output of the programmable divider and a reference signal is detected thereby to control the oscillation frequency of the VCO.

Abstract: A serial pulse frequency converter is disclosed of the type which counts high frequency clock pulses between input pulses, multiplies each successive count by first and second proportionally constants and downcounts the products by high frequency clock pulses to produce output pulses at a new, proportional frequency. A first serial register is used to both count the high frequency pulses between input pulses and hold the count during the multiplication process. It is loaded at the end of multiplication with the a number representing the "lost counts" as it is switched to its counting mode. A second serial register accumulates the sum of partial products of the count and the proportionality constants. The gain circuit serially provides a first proportionality constant and then a second, but may selectively substitute a binary number representing a constant unity for the second.

Abstract: A square wave with a 50% duty cycle which has frequency twice that of an input square wave also having a 50% duty cycle is obtained by generating from the incoming square wave two waveforms having 75% duty cycles with the two waveforms 180.degree. out of phase with each other. The two waveforms are combined in an ANDing operation to obtain an output waveform which is a square wave with twice the frequency of the incoming square wave. In similar fashion, using additional similar circuits and gating, tripling is possible.

Abstract: A solid state electronic pulse scaler uses the ratio of two integers to control a ratio of its input and output frequencies. In one embodiment, the pulse scaler is used as a calibration device to adjust for manufacturing tolerances in an electric metering device. In another embodiment, the pulse scaler is used to provide a pulse-initiator output to external circuits. A further embodiment includes both of the above functions in a single device. A switch-selectable control is provided to determine the consequences of input pulses generated during reverse rotation of a meter disk. The reverse pulses may be used to generate output pulses on the same, or a separate, channel as that employed for forward pulses, ignored, or temporarily stored and subtracted from ensuing forward pulses.

Abstract: A circuit for producing a pair of output pulses for each cycle of differentially applied input pulses includes a pair of input transistors to which the differential input pulses are applied and a pair of output transistors the collectors of which are connected to an output of the pulse doubling circuit and the bases of which are respectively coupled to the emitters of a corresponding input transistor. A pair of delay circuits are provided coupled respectively from one of the input transistors to the base of the opposite output transistor.

Abstract: A variable-ratio frequency divider has a D flip-flop which makes possible high-speed operation, and the number of frequency divisions is made variable by changing the transmission delay time of a delay element included in a feedback loop from the output Q to a predetermined terminal of the D flip-flop.

Abstract: An integrated D flip-flop circuit including a plurality of inverter gates produces an output signal having a frequency that is equal to the frequency of an applied alternating input signal divided by a predetermined divide ratio wherein the improvement comprises an additional inverter gate that has an output connected to a predetermined one of the interconnected inverter gates and is responsive to a divide inhibit signal being applied to an input thereof for changing the divide ratio of the D flip-flop circuit.

Abstract: In utilizing frequency dividers at high frequencies the maximum operating frequency is determined by the delay time through the frequency divider. To minimize this delay time, a digital frequency divider is provided having a binary counter constructed of flip-flops and a shift register coupled to the output of said counter, wherein the output state of the shift register is forcibly reduced to a low level in response to a control signal for varying the number of frequency division of said counter. A circuit is also provided for feeding the input terminal of the flip-flop at the first stage of said counter with an OR output made up of the outputs of said shift register and said counter. Thus, the digital frequency divider can operate at a speed which is limited only by the toggle frequency of said flip-flop circuits.