Abstract: A programmable divider includes a synchronous counter configured to process an input clock signal and produce first output signals in response the input clock signal. A number of logic devices are coupled to the synchronous counter and configurable to receive the first output signals and correspondingly produce second output signals. Also included is a multiplexer that is configured to receive the second output signals and has an output coupled to an input of the synchronous counter. In the programmable divider, characteristics of the synchronous counter are selectable based upon a particular number of the logic devices configured.

Abstract: In one embodiment, as an example, N/M (=3.33333 . . . ) dividing is performed assuming M=3, N=10. That is, the frequency of the input signal CK is converted to the frequency of 1/3.33333 . . . times. Here, it is assumed that the frequency dividing number is 3.33333 . . . In this case, 3(=n) dividing is combined with 4(=n+1) dividing to perform the dividing, and accordingly a signal of a desired frequency can be obtained. In response to the output DOUT of the frequency divider, an n dividing counter counts the number of performed n-dividing operations and an n+1 dividing counter counts the number of performed n+1-dividing operations. An adder outputs the frequency dividing number (n) or (n+1). A frequency divider uses the frequency dividing numbers to divide an arbitrary frequency signal CK.

Abstract: A non-integer frequency divider is disclosed. The non-integer frequency divider circuit includes several base stages connected to each other. The non-integer frequency divider circuit also includes a clocking circuit for passing an enable bit from one of the base stages to another such that only one of the base stages is enabled at any give time. The enable bit has a pulse width of one clock cycle. The outputs from the base stages are grouped together by an OR gate to generate a single output that is a fraction of an input clock signal.

Abstract: A clock multiplier circuit which generates a multiple clock having a stable frequency from a reference clock without using analog devices. The clock multiplier circuit includes ring oscillator which oscillates at a higher frequency than that of the multiple clock; a reference clock counter for counting the sampling output of the reference clock by the output clock of the ring oscillator to obtain a count value of the half cycle of the reference clock; and a multiple clock counter which, in case the value obtained by dividing the count value of the half cycle of the obtained reference clock by the multiplication factor externally given is defined as a multiple count value, inverts the multiple clock output each time it counts the multiple count value by the output clock of the ring oscillator.

Abstract: A counter has selectable divide factors using multiple multiplexers. The counter includes an inverter and cascading delay stages having selectable stage delays. The inverter connects a stage output of a last one of the delay stages to a stage input of a first one of the delay stages. Each delay stages includes a stage input to receive a quotient signal, at least two paths having different associated path delays each coupled to receive the quotient signal from the stage from the stage input, and a multiplexer. The multiplexer is coupled to selectively communicate the quotient signal from one of the at least two paths to a stage output to select one of the stage delays.

Abstract: A device generating a pulse signal includes at least one first register which stores waveform data therein, a pulse signal generation unit which generates a pulse signal in accordance with the waveform data of the first register, a control unit which is connected to a bus, and is controlled by control signals supplied from the bus, and a signal line which is separate from and independent of the bus, and is connected to the control unit, wherein the control unit updates the waveform data of the first register in response to a signal that is externally supplied through the signal line.

Abstract: A system may include a control unit and a dual modulus prescaler. The control unit may generate a modulus control signal. The dual modulus prescaler may be configured to divide the frequency of an input signal by Q when the modulus control signal has a first value and to divide the frequency of the input signal by (Q+V) when the modulus control signal has a second value. Q is an irreducible fraction. The sum (Q+V) may be an integer or a fraction. The dual-modulus prescaler includes several clocked storage units (e.g., flip-flops) that are each clocked by a respective one of several equally spaced phases of the input signal. Each clocked storage unit operates in a toggle mode.

Abstract: A fractional-N frequency synthesizer includes a voltage-controlled oscillator, a dual-modulus divider which divides an output frequency of the voltage-controlled oscillator according to a fractional control input, and a phase comparator which compares a phase of an output of the dual-modulus divider with a phase of a reference frequency, where an output of the phase comparator controls an input of the voltage-controlled oscillator. The synthesizer further includes a sigma-delta modulator which has a single-bit output, and a bit converter which converts the single-bit output of the sigma-delta modulator to the fractional control input applied to the dual-modulus divider.

Abstract: A circuit generates an output signal whose frequency is lower than the frequency of an input signal. In an example embodiment, there is a chain of frequency dividing cells. Each of the frequency dividing cells has a pre-defined division ratio and a clock input for receiving an input clock, a divided clock output for providing an output clock to a subsequent frequency dividing cell, a mode control input for receiving a mode control input signal from the subsequent frequency dividing cell, and a mode control output for providing a mode control output signal to a preceding frequency dividing cell. Further included are a latch for altering the division ratio of each of the frequency dividing cells and D-Flip-Flop circuitry having two latches. A first signal clocks the first latch and a second signal clocks the second latch, whereby the frequency of the first signal is lower than the frequency of the second signal.

Abstract: A fractional-N frequency synthesizer has a modulus controller with multiple inputs that control an initial output frequency of the frequency synthesizer, an increment of variation of tuning of the frequency synthesizer, and a difference between two adjacent output frequency settings. The fractional frequency synthesizer includes a modulus controller, which controls the modulus factor for a multiple modulus frequency divider. The modulus controller has a modulus selection circuit that provides a modulus control signal to the modulus divider to select the modulus factor of the modulus divider as a function of a sum of one input factor and a product of a second input and the gain factor. Control signal is an overflow from a continuous summation of the second digital data word and a product of the first digital data word and the gain factor digital data word repetitively with itself.

Abstract: In one embodiment, as an example, N/M (=3.33333 . . . ) dividing is performed assuming M=3, N=10. That is, the frequency of the input signal CK is converted to the frequency of 1/3.33333 . . . times. Here, it is assumed that the frequency dividing number is 3.33333 . . . . In this case, 3(=n) dividing is combined with 4(=n+1) dividing to perform the dividing, and accordingly a signal of a desired frequency can be obtained. In response to the output DOUT of the frequency divider, an n dividing counter counts the number of performed n-dividing operations and an n+1 dividing counter counts the number of performed n+1-dividing operations. An adder outputs the frequency dividing number (n) or (n+1). A frequency divider uses the frequency dividing numbers to divide an arbitrary frequency signal CK.

Abstract: A multi-selection prescaler for dividing an input signal according to a ratio to obtain a desired frequency. The circuit has of a plurality of logic gates and D-flip-flops: a first frequency divider for receiving an input signal and generating a divided frequency; a second frequency divider connected to the first frequency divider for performing a further frequency division based on a selection switch having a plurality of selection signals and a plurality of AND gates; a module control for performing a logic operation on the selection signals and an external control signal (MC) by OR gates and being connected to the first frequency divider to control the divided frequency of the first frequency divider; and an output selection circuit connected to the second frequency divider for selecting output signal according to the selection signals.

Abstract: A frequency divider circuit is disclosed that generates output signals having a frequency substantially half of the frequency of the input signal. The circuit comprises two D-Flip-Flop circuits wherein one employs the said input signal and the other one employs the complement of the said input signal, and each of the two D-Flip-Flop circuits consists of a pair of loading transistors, two regenerative pairs coupled with each others, and two common-gate switches.

Abstract: Apparatus and method for generating a divided clock signal. A ring counter is provided with a sequence of output states. During steady-state operation, a different one of the output states is set at a first logical level and each of the remaining output states is set at a second logical level at each successive clock transition in a master clock signal. A gate network uses the respective logical levels of the output states to generate the divided clock signal. An error detection circuit outputs an error detection signal when a number of the output states at the first logical level is other than one, and proceeds to synchronously reset the ring counter when the error condition is detected. A programmable processor further asynchronously resets the ring counter in response to the error detection signal, as desired.

Abstract: An integrated circuit including a phase lock loop or delay lock loop (PLL/DLL) circuit comprising: a clock input terminal for accepting a clock signal; a phase/frequency detector (PFD) circuit including a reference clock input connected to the clock input terminal and including a PFD feedback input and including a PFD output; a charge pump (CP) circuit; at least one external feedforward output terminal; a loop filter (LF); a loop controlled signal source (LCSS); and a feedback circuit connected between a LCSS output and the PFD feedback input, the feedback circuit including, an external feedback input terminal; first frequency selection circuitry to produce a first programmable feedback signal; second frequency selection circuitry to produce a second feedback signal; and multiplex circuitry connected with the LCSS output, the external feedback input terminal and the first and second frequency selection circuitry, to cause either the first programmable feedback signal or the second programmable feedback signal

Abstract: A non-integer frequency divider is disclosed. The non-integer frequency divider circuit includes several base stages connected to each other. The non-integer frequency divider circuit also includes a clocking circuit for passing an enable bit from one of the base stages to another such that only one of the base stages is enabled at any give time. The enable bit has a pulse width of one clock cycle. The outputs from the base stages are grouped together by an OR gate to generate a single output that is a fraction of an input clock signal.

Abstract: Apparatus (50) for generating an output signal (fdiv) whose frequency is lower than the frequency of an input signal (CK1, fvco). The apparatus (50) comprises a chain of frequency dividing cells (51-56), wherein each of the frequency dividing cells (51-56) has a definable division ratio (DR) and comprises:—a clock input (CKi) for receiving an input clock (CKin);—a divided clock output (CKi+1) for providing an output clock (CKout) to a subsequent frequency dividing cell;—a mode control input (MDi) for receiving a mode control input signal (MDin) from the subsequent frequency dividing cell; and—a mode control output for providing a mode control output signal (MDout) to a preceding frequency dividing cell. The apparatus (50) further comprises a logic network (58) having m inputs. Each of the m inputs is connected to a mode control input (MDi, MDi+1, MDi+2) of one of the m consecutive frequency dividing cells (51-54).

Abstract: A resampling technique is used to reduce the noise and improve the signal quality in the output of a prescaler circuit (10). The resampling of the output of a last frequency divider stage is accomplished using at least one flip/flop (FF) (e.g., a D-type FF 18) that is clocked by a signal obtained from the input of the prescaler. This reduces or eliminates the noise caused by edge jitter in the output of the prescaler, as well as the effect of spurious signals generated by the prescaler. These teachings can be used in integer N PLLs and in fractional N PLLs, as well as in single and programmable dual or multi-modulus prescalers. Using this technique the current consumption of the prescaler frequency dividers (12, 14, 16) need not be increased in an effort to reduce the prescaler noise, thereby conserving current in battery powered and other applications.

Abstract: A prescaler (100) includes a frequency divider (102) having an input node (136) and a divider output (128). The frequency divider is coupled to a clock signal and has a predetermined divisor. Series-coupled delay elements (104, 106, 108) are coupled to the divider output and to the clock signal. Each delay element includes a delayed output (130, 132, 134) and adds a delay equal to the clock period at the delayed output. The prescaler also includes transmission gates (112, 114, 116), each transmission gate coupled between the input node and the delayed output of a corresponding one of the delay elements. When one of the transmission gates is enabled and couples the delayed output of an nth one of the delay elements to the input node, the divider output frequency equals the clock frequency divided by the predetermined divisor plus n.

Abstract: A programmable-divider provides a lower-speed transition signal to effect a synchronized load of a new divisor value during a safe-load period of the programmable-divider, such that the division occurs using either the prior divisor value or the new divisor value, only. A combination of in-phase and reverse-phase counter stages are used to position the divisor-independent period of each counter stage so that an edge of at least one of the lower-speed counter-enabling signals occurs during a period when all of the counter stages are in a divisor-independent period. The preferred selection of in-phase and reverse-phase counter stages also maximizes the critical path duration, to allow for the accurate division of very high speed input frequencies.

Abstract: A clock generating circuit of a semiconductor integrated circuit device includes a plurality of stages of frequency-dividing circuits connected in series, of which a first stage receives a reference clock signal, each frequency-dividing circuit requiring no reset signal; and a plurality of buffers respectively transmitting a reference clock signal and output clock signals of the plurality of frequency-dividing circuits to an internal circuit of the semiconductor integrated circuit device. Therefore, a plurality of clock signals having different frequencies with aligned edges can be generated without the need for separately providing an external pin for inputting the reset signal or a circuit for generating the reset signal.

Abstract: The dual-modulus prescaler circuit for a frequency includes several dividers-by-two of the asynchronous type, connected in series, a phase selector unit (11) inserted between two of the dividers-by-two (10, 12a) and a control unit for supplying first control signals(S0, S1, S2, C1, C2) to the selector unit as a function of a selected mode. Said control unit receives four signals phase shifted by 90° with respect to each other from a first master-slave divider and supplies a selected one of the four phase shifted signals. The selector unit includes a first amplifying branch (21) receiving two first phase shifted signals (F2I, F2Ib), a second amplifying branch (22) receiving two second phase shifted signals (F2Q, F2Qb), and a selection element (23) connected to each branch. The first control signals (S0, S1, S2) are supplied to the first and second branches, and to the selection element for selecting one of the four phase shifted signals (F2) at one output in a determined division period.

Abstract: Apparatus including a frequency dividing cell (42) with a prescaler logic, an end-of-cycle logic, a clock input for receiving an input clock (CKin) with frequency fn, a clock output for providing an output clock (CKout) with frequency fm to a subsequent cell (43), a mode control input for receiving a mode control input signal (MDin) from the subsequent cell (43), and a mode control output for providing a mode control output signal (MDout) to a preceding cell (41). The end-of-cycle logic of the frequency dividing cell (42) has a switchable tail current source. This switchable tail current source allows the biasing current of the end-of-cycle logic to be switched off in to save power.

Abstract: A duty cycle correction circuit is provided for converting a pair of differential analog signals from an oscillator into an output pulse signal with 50% of duty cycle. The pulse signal has the same frequency as that of each of the differential analog signals. The duty cycle correction circuit includes a first differential-to-single-ended buffer circuit, a second differential-to-single-ended buffer circuit, a first frequency divider, a second frequency divider and a symmetrical exclusive OR element. The first and the second differential-to-single-ended buffer circuits are used for processing the pair of differential analog signals into a first and a second digital pulse signals, respectively. The first and the second frequency dividers are employed for frequency-dividing the first and the digital pulse signal into a third and a fourth digital pulse signal, respectively. The symmetrical exclusive OR element is used for performing an exclusive OR operation so as to produce the output pulse signal.

Abstract: A digital, preferably programmable, circuit is disclosed for providing one or more clock signals with variable frequency and/or phase. The clock signals exhibit a low amount of skew relative to other clock signals and data signals provided by the circuit. In one embodiment, the circuit includes a plurality of channels each having a parallel-in/serial-out shift register, a flip-flop, and a delay circuit. The shift register can receive data bits in data channels or clock frequency select bits in frequency-divided clock channels. The serial output from the register acts as an input for the flip flop, both of which are triggered by an input reference clock. The delay circuit delays the input reference clock. In each channel, a multiplexer is configured to select the clock or data channel output from the register, flip-flop, and delay circuit outputs. Since the delays in all output paths are matched, skew is minimized.

Abstract: The present invention provides a synthesizer having an efficient lock detect signal generator, an extended range VCO that can operate within any one of a plurality of adjacent characteristic curves defined by a plurality of adjacent regions, and a divide circuit implemented using only a single counter along with a decoder. This allows for a method of operating the synthesizer, methods of establishing or reestablishing a lock condition using the extended range VCO, and a method of designing a plurality of divide circuits which each use the same single counter and each use a different decoder.

Abstract: A digital frequency synthesizer (DFS) circuit adds little additional delay on the clock path. True and complement versions of an input clock signal are provided to a first and second passgates, respectively. Under the direction of a control circuit, the passgates pass selected rising edges of the true clock signal, and selected falling edges of the complement clock signal, to an output clock terminal of the DFS circuit. When neither the true nor the complement clock signal is passed, a keeper circuit retains the value already present at the output clock terminal. In some embodiments, both passgates can be disabled and a ground or power high signal can be applied to the output terminal. Other embodiments include PLDs in which the DFS circuits are employed to allow individual clock control for each programmable logic block.

Abstract: To generate a target frequency from a basic frequency, a phased signal of the basic frequency and of a phase controllable by a phase clock signal is generated in accordance with the invention, the target frequency being generated by dividing the frequency of the phased signal by an output dividing factor and the phase clock signal being generated from the phased signal irrespective of the target frequency. A wider range of target frequencies can be obtained in this way. Also, the switching pattern in which the phase of the phased signal is changed can be made independent of the state of the phased signal, thus giving further possible ways of acting on the target frequency.

Abstract: A programmable frequency divider capable of a 50% duty cycle at odd and even integer division ratios. In one embodiment, the frequency divider is configured to produce an output signal having a period equal to a division ratio N times a period of a clock signal, and the division number N is a programmable variable which bears the following relationship to the number F of required storage elements: F = N + P 2 , where P is 1 if the division ratio is odd, and 0 if the division ratio is even.

Abstract: The invention relates to a method and system for implementing a digitally controlled sample and timing clock in a system performing analog and digital signal processing. According to the method, as the timing clock of the digital signal processing is used a clock with a controllable frequency such that said digital signal processing can have a factions suited for controlling the frequency of said timing clock, and the conversion of the signal is performed in synchronism with the timing clock of the digital signal processing operation when a delta-sigma converter or a switched-capacitor filter device is employed.

Abstract: A single-event upset immune frequency divider circuit is disclosed. The single-event upset immune frequency divider circuit includes a dual-path shift register, a dual-path multiplexor, and a summing circuit. The dual-path shift register has a clock input, one signal input pair and multiple signal output pairs. The dual-path multiplexor has multiple signal input pairs and one output pair. The signal input pairs of the dual-path multiplexor are respectively connected to the signal output pairs of the dual-input shift register. The dual-path multiplexor selects one of the signal output pairs of the dual-path shift register for feeding back into the signal input pair of the dual-path shift register. The summing circuit then sums the signal input pair of the dual-path shift register to generate an output clock signal that is a fraction of the frequency of an input clock signal at the clock input of the dual-path shift register.

Abstract: An apparatus and associated method is disclosed for increasing the maximum input frequency of a frequency divider system by altering the division ratio in the frequency divider system. In an exemplary form, the apparatus includes an electrical mixer circuit to combine an internal and an external frequency input signals into a combination frequency signal and a frequency divider circuit to receive the combination frequency signal and to frequency divide the combination frequency signal by a predetermined number, a signal splitter and a directional coupler in operative to receive the divided frequency signal and to generate an output frequency signal and a feedback frequency signal wherein the feedback frequency signal is identical in frequency to the output frequency signal and becomes the internally inputted frequency signal for the mixer. In this way the maximum input frequency of the frequency divider system can be advantageously increased.

Abstract: A clock multiplication technique includes driving two oscillatory circuits by an input signal. One of the circuits has an inverted input. The oscillatory circuits are characterized by a transfer function having an unstable region bounded by two stable region. Oscillations produced during operation of each of the circuits in the unstable regions are combined to produce a signal whose frequency is a multiple of the input frequency.

Abstract: A programmable divider includes a synchronous counter configured to process an input clock signal and produce first output signals in response the input clock signal. A number of logic devices are coupled to the synchronous counter and configurable to receive the first output signals and correspondingly produce second output signals. Also included is a multiplexer that is configured to receive the second output signals and has an output coupled to an input of the synchronous counter. In the programmable divider, characteristics of the synchronous counter are selectable based upon a particular number of the logic devices configured.

Abstract: A frequency divider circuit (11) has an input port for an input signal (F0) to be divided, an output port for a divided signal (FDIV), and means (12-19) for providing a variable division-ratio control signal (N+C) and a residual quantization error signal (R), applying the variable division ratio control signal (N+C) to a control port of the frequency divider, and using the residual quantization error signal (R) to cancel phase error in the divided signal. Both the variable division ratio control signal (N+C) and the residual quantization error signal (R) are dithered.

Abstract: An integrated circuit including a phase lock loop or delay lock loop (PLL/DLL) circuit comprising: a clock input terminal for accepting a clock signal; a phase/frequency detector (PFD) circuit including a reference clock input connected to the clock input terminal and including a PFD feedback input and including a PFD output; a charge pump (CP) circuit; at least one external feedforward output terminal; a loop filter (LF); a loop controlled signal source (LCSS); and a feedback circuit connected between a LCSS output and the PFD feedback input, the feedback circuit including, an external feedback input terminal; first frequency selection circuitry to produce a first programmable feedback signal; second frequency selection circuitry to produce a second feedback signal; and multiplex circuitry connected with the LCSS output, the external feedback input terminal and the first and second frequency selection circuitry, to cause either the first programmable feedback signal or the second programmable feedback signal

Abstract: A digital frequency divider has a single circulating shifter register loaded with a bit sequence of variable length and having two outputs adjacent such that are output is equal to the other delayed by one clock period. The outputs are passed to a multiplexer via further logic, the multiplexer selecting one of two inputs depending on whether a clock is high or low. Program logic is provided so that the circuit is configurable for odd, even or half integer division by detecting changes in the bit sequence between 0 and 1 and selectively “deleting” the first half clock cycle when a change is detected. This allows even, odd or half integer clock division with an “even” mark space ratio.

Abstract: A cascadable divide-by-two binary counter circuit (120) that has particular application for use as a synchronous divider circuit (50, 54) in a phase lock loop (26). The counter circuit (120) employs a D flip-flop (122) that receives a D input and provides a Q output. A first AND gate (124) is responsive to a P input and a Q input, where the Q input is the output from a preceding counter circuit and the P input is the state of all of the preceding counter circuits. The output of the AND gate (124) is applied to an exclusive-OR gate (126) along with the Q output of the flip-flop (122). The output of the exclusive-OR gate (126) is applied to one input of a second AND gate (128). The other input of the second AND gate (128) is a reset signal and the output of the second AND gate (128) is the D input of the flip-flop (122). A decoder (142) is programmed to provide the reset signal when the desired count is reached.

Abstract: A novel 2/3 full-speed divider operating at high speed with low power consumption comprising a ECL D flip-flop in master-slave configuration and a phases-selection block is provided in the present invention. The master latch and slave latch comprise a pair of input terminals, a pair of control terminals, and a pair of output terminals. The master latch further comprises two pairs of complementary cross-couple transistors for amplifying the output of the master latch for entering the phase-selection block. The phase-selection block has a pair of input terminals, a clock signal input terminal, and an output terminal generating an output signal adjusted by a division ratio according to the clock signal. The division ratio is either 1/2 or 1/3 and the divider functions as a 2/3 divider.

Abstract: A fractional-N frequency synthesizer is disclosed wherein the multi-modulus frequency divider in the feedback path of the phase locked loop is controlled by a delta-sigma modulator to achieve the desired division ratio. The fractional input control signal to the delta sigma modulator is dither to break any periodicity in the modulator output signal to avoid the generation of fractional spurious frequencies.

Abstract: A phase interpolator circuit that produces 2m phase resolution elements using a control signal that has less than m bits. The circuit combines the function of a divide-by-N circuit with a phase interpolation circuit enabled by the use of a higher-speed clock as an input. By performing phase interpolation at a high speed and then slowing down the speed for the subsequent circuits, the phase resolution increases and fewer control bits are required.

Abstract: 1.

Abstract: The present invention discloses a glitch-free frequency dividing circuit, comprising: a frequency dividing module, dividing the frequency of a reference pulse according to the divisor, outputting a frequency divided output pulse and receiving a control signal such that the state of the frequency divided output pulse is maintained the same when the control signal is enabled; and a latch module, detecting the state of the frequency divided output pulse after a divisor switching signal is received, enabling the control signal when the frequency divided output pulse is as pre-determined, switching the divisor when the frequency divided output pulse is as pre-determined and disabling the control signal after the divisor is switched; whereby the generation of the glitch is prevented during the switching of the divisor.

Abstract: The present invention relates to a structure of a delta-sigma factional divider. The divider structure adds an external input value and an output value of a delta-sigma modulator to modulate a value of a swallow counter. Therefore, the present invention can provide a delta-sigma factional divider the structure is simple and that can obtain an effect of a delta sigma mode while having a wide-band frequency mixing capability.

Abstract: A frequency dividing circuit divides a master clock frequency by a non-integer factor to provide an output clock signal whose frequency is equal to the frequency of the master clock signal divided by that non-integer factor. In one embodiment, the circuit is operative to divide the master clock frequency by 2.5.

Abstract: A divide-by-N clock divider circuit adds little additional delay on the clock path. N can be any integer, and the value of N does not affect the clock path delay. The divide-by-N clock divider circuits of the invention include a control circuit and a logical NOR circuit, where the control circuit is clocked by an input clock signal and the NOR circuit combines the output signal of the control circuit with the input clock signal. The control circuit acts as a filter, selecting pulses from the input clock signal to be passed to the output terminal. By selecting one out of every N input clock pulses, a divide-by-N clock divider is implemented. Because no decode logic is included in the clock path, the through-delay of the clock divider circuit is small. In some embodiments, the value of N is programmable. In some embodiments, optional duty cycle correction is available.

Abstract: To divide a clock signal, a clock pulse counter counting clock pulses of the clock signal is in each case alternately reset after passing through different count differences. In this process, a first signal and a second signal is formed, the logic state of which is in each case changed with the presence of a first or, respectively, second predetermined count of the clock pulse counter by a rising or, respectively, falling clock signal edge. A divided output clock signal is then generated by a logical operation on the first and the second signal.

Abstract: A digital, preferably programmable, circuit is disclosed for providing one or more clock signals with variable frequency and/or phase. The clock signals exhibit a low amount of skew relative to other clock signals and data signals provided by the circuit. In one embodiment, the circuit includes a plurality of channels each having a parallel-in/serial-out shift register, a flip-flop, and a delay circuit. The shift register can receive data bits in data channels or clock frequency select bits in frequency-divided clock channels. The serial output from the register acts as an input for the flip flop, both of which are triggered by an input reference clock. The delay circuit delays the input reference clock. In each channel, a multiplexer is configured to select the clock or data channel output from the register, flip-flop, and delay circuit outputs. Since the delays in all output paths are matched, skew is minimized.

Abstract: The dual-modulus prescaler circuit for a frequency includes several dividers-by-two of the asynchronous type, connected in series, a phase selector unit (11) inserted between two of the dividers-by-two (10, 12a) and a control unit for supplying first control signals(S0, S1, S2, C1, C2) to the selector unit as a function of a selected mode. Said control unit receives four signals phase shifted by 90° with respect to each other from a first master-slave divider and supplies a selected one of the four phase shifted signals. The selector unit includes a first amplifying branch (21) receiving two first phase shifted signals (F2I, F2Ib), a second amplifying branch (22) receiving two second phase shifted signals (F2Q, F2Qb), and a selection element (23) connected to each branch. The first control signals (S0, S1, S2) are supplied to the first and second branches, and to the selection element for selecting one of the four phase shifted signals (F2) at one output in a determined division period.

Abstract: An apparatus and associated method is disclosed for increasing the maximum input frequency of a frequency divider system by altering the division ratio in the frequency divider system. In an exemplary form, the apparatus includes an electrical mixer circuit to combine an internal and an external frequency input signals into a combination frequency signal and a frequency divider circuit to receive the combination frequency signal and to frequency divide the combination frequency signal by a predetermined number, a signal splitter and a directional coupler in operative to receive the divided frequency signal and to generate an output frequency signal and a feedback frequency signal wherein the feedback frequency signal is identical in frequency to the output frequency signal and becomes the internally inputted frequency signal for the mixer. In this way the maximum input frequency of the frequency divider system can be advantageously increased.