Abstract: A variable frequency dividing circuit adjusts the frequency dividing ratio by a non integer. The variable frequency dividing circuit includes a sequence storing part for storing an N-bit sequence data to output the N bits of the sequence data in parallel. The variable frequency dividing circuit also includes a sequence generator for receiving the N-bit sequence data from the sequence storing pan to generate a sequence control signal and a sequence control signal converter for converting the sequence control signal according to a frequency variation request to generate the converted sequence control signal. The variable frequency dividing circuit further includes a frequency divider for dividing a clock signal frequency according to the converted sequence control signal outputted from the sequence control signal converter and a clock signal generator for producing a clock waveform in accordance with the divided clock signal frequency.

Abstract: A prescaler which can be used in a PLL includes a counter section and an extender section. The counter section has a pair of staged, synchronous flip-flops which generate a frequency divided signal by frequency dividing an input oscillation signal by either two or three. The extender section has a plurality of staged, asynchronous flip-flops which generates a second frequency divided signal. A switching circuit connected between the extender section and the counter section controls whether the counter section operates as either a binary counter or a ternary counter. Power conservation is achieved by limiting the counter section to only a pair of flip-flops.

Abstract: A frequency multiplier integrated circuit (IC) has a frequency multiplier 1, an initialization signal generator 2, data sampling generator 3, and a clock generator 4. The frequency multiplier 1 has a timer 17 for calculating a first time between changes of state of an input signal, a time calculator 18 for a second time that a should occur between changes of state in the output signal, and an output signal generator 19 for generating the output signal. The initialization signal generator generates two initialization signals 12 and 13, one being the complement of the other, with a duration greater than 20 msec after an input initialization signal is received.

Abstract: A programmable divider circuit having an adjustable shift register is coupled to a clock and to an output. The shift register receives a clock signal having a clock signal frequency and outputs an output signal with an output frequency corresponding to a user selected divide ratio of the clock signal frequency. Control inputs are coupled to the adjustable shift register to receive control data for adjusting a length of the shift register, the length of the shift register corresponding to the user selected divide ratio.

Abstract: A PLL circuit having a variable frequency divider circuit includes a timing circuit which ensures that data provided to a comparison counter circuit is stable before initiating a counting operation, which prevents the counter circuit from generating erroneous data.

Abstract: Perfectly resynchronized windowed clock signals are constructed starting from a main clock signal of the same frequency of that of the active phases of the constructed windowed clock signal, advantageously without requiring a main clock of a higher frequency.

Abstract: A programmable divider or prescaler divides an input signal by a divisor of two raised to the m.sup.th -power plus one, (2.sup.m +1), where m is an integer, and n is a value between zero and two raised to the m.sup.th -power minus one, (2.sup.m -1). When m is equal to 3, the duty cycle is between 44% and 56%. The divider can be utilized in communication applications for providing radio frequency source signals. The duty cycle is maintained around 50% for use with balanced mixers.

Abstract: A clock multiplier controls the frequency of an output clock signal according to the frequency of an input clock signal by means of two feedback loops. The first feedback loop, active during a fixed number of initial cycles of the input clock signal, counts cycles of the output clock signal during each cycle of the input clock signal, and controls the output clock frequency according to the resulting count values. The second feedback loop, used after the fixed number of initial cycles, divides the frequency of the output clock signal, and controls the output clock frequency according to the phase difference between the resulting divided signal and the input clock signal.

Abstract: The present invention provides a phase locked loop (PLL) clock generator for a digital system. The PLL clock generator is capable of an instantaneous transition between a high frequency and a low frequency, corresponding to an active mode and a slow mode, and vice versa The PLL clock generator includes a phase locking circuit, a frequency changer coupled to the output of the phase locking circuit, and a frequency controller coupled to the frequency changer. The frequency changer is capable of instantaneously changing the frequency of a first clock signal received from the phase locking circuit. The frequency controller is responsible for controlling the frequency at the output of the frequency changer. The frequency controller is responsive to a control signal which is used to transition the PLL clock generator from an active mode to a slow mode and vice versa In one embodiment, the phase locking circuit generates the first clock signal in response to a reference clock signal and a feedback clock signal.

Abstract: An m bit counter which counts to a desired clock frequency F.sub.D given a central clock frequency F.sub.C is emulated by a chain of two subcounters. The ratio r of the central clock frequency F.sub.C over the desired clock frequency F.sub.D is factored to r=F.sub.C /F.sub.D =2.sup.n * p, where n is one of zero or an integer (i.e., 0, 1, 2, 3 . . . ) and where p is an integer. A 1 to p subcounter counts from 1 to p driven by the central clock frequency F.sub.C. The output of the 1 to p counter is an intermediate clock frequency which includes a pulse every periodic count from 1 to p. The intermediate clock frequency drives a m+n bit subcounter with the n bits being appended as the least significant bits of the m+n bit subcounter. In this manner, the m most significant bits of the m+n bit subcounter count to the desired clock frequency F.sub.D.

Abstract: A multi-divide frequency divider, includes a chain of serially-connected frequency divider units, each responding to a first state of received control signals by using the reference clock signal to generate an output signal having a frequency that is the reference clock frequency divided by a first divisor, and each responding to a second state of the control signals by using the reference clock signal to generate an output signal having a frequency that is the reference clock frequency divided by a second divisor. The output signal may be supplied to a successor frequency divider unit in the chain. Division by the first and second divisors causes the frequency divider to respectively transition through first and second predetermined state sequences.

Abstract: Quality requirements on a counter may set a limit to the highest frequency that can be applied to the counter. This will also limit the resolution. A counter is provided including a generator for generating, in response to a first clock frequency, M second clock signals phase shifted with respect to each other and of a second frequency lower than the first frequency, and M secondary counters, each one responsive to a respective one of the M second clock signals for generating a secondary counter signal. The second frequency is adapted to work well in the technology available for realizing the secondary counters, with consideration taken to quality requirements. Furthermore, the counter included a summing circuit responsive to the secondary counter signals for generating the resulting counter signals by adding the secondary counter signals such that the counter signal has the same number of bits and the same significance as the secondary counter signals.

Abstract: To implement a counter which can count clocks at high frequency exceeding the maximum operating frequency of the counter circuit, with a circuit with smaller circuit scale and lower power consumption, the present invention divides an externally set value HDB indicative of a count completion value into upper and lower bits, the upper bits being counted by using a counter circuit 12 with small circuit scale and power consumption, match being detected by a comparator 13. The clock signal is frequency divided to accommodate supply of high frequency clocks, and supplies it to the counter circuit 12. Then, the match detection signal of the upper bits is shifted in the number corresponding to the value of lower bits by a shift register 14 operating at a high frequency, and a count completion signal OUT is output.

Abstract: A divide-by-4/5 counter includes a half transparent register, a domino logic, a buffer, a divide-by-4 counter and a control circuit. The half transparent register includes first, second, and third NMOS and PMOS transistors and first and second inverters. The domino logic includes fourth PMOS and NMOS transistors and first and second switches. The buffer is connected to a drain of the fourth PMOS transistor for out putting a reference clock signal. The divide-by-4 counter includes two divide-by-2 counters to obtain a divide-by-2 clock signal and an output clock signal. The control circuit is connected to a control terminal of the second switch for outputting a control signal of the domino logic according to the divide-by-2 clock signal, the output clock signal and a divide-by-4/5 control signal.

Abstract: A system and method are presented for equalizing data buffer storage and fetch rates of peripheral devices. A computer system of the present invention includes a central processing unit (CPU), first and second peripheral devices, and a data buffer. The first peripheral device stores data within the data buffer, and the second peripheral device fetches data from the data buffer. A fraction of the data buffer contains unread data (i.e. data stored within the data buffer by the first peripheral device and not yet fetched by the second peripheral device). The first peripheral device includes a reload register, the contents of which determines the rate at which the first peripheral device stores data within the data buffer. The CPU produces a reload value, which is stored within the reload register, such that the rate at which the first peripheral device stores the data within the data buffer is made substantially equal to the rate at which the second peripheral device fetches the data from the data buffer.

Abstract: A clock divider circuit and a system using the same. The clock divider circuit has a clock input coupled to receive an input clock signal having an input clock frequency. Clock division logic generates an output clock signal having a fifty percent duty cycle and an output clock frequency which is an odd fraction of the input clock frequency. The clock division logic generates both the rising and the falling clock edges of the output clock signal from the input clock signal. The system disclosed includes a processor operating at a first frequency and a memory circuit coupled to exchange data with the processor. The processor includes a clock division circuit coupled to receive a first clock signal and to generate a second clock signal at a second frequency which is an odd fraction of the first frequency. The processor also includes an input/output buffer coupled to exchange data with the memory circuit.

Abstract: A frequency divider (50) comprises complementary components (e.g., CMOS transistors) which are placed in two complementary portions (10, 20) with similar structures. The portions are coupled by four lines (131-134). Each line (e.g., 131) is coupled to a pair of transistors including a pull device (e.g., 271) and a hold device (e.g., 291). The devices receives identical signals from another line (e.g., 134) and the input signal X in the same, non-inverted form. The devices have complementary logical functions because of their complementary structures (serial.backslash.parallel) and complementary components (P-FET, N-FET). When a line (e.g., 131) is pulled to a reference line (e.g., 91), contention between the devices is substantially avoided. There is no need to provide the input signal X in a non-inverted and in an inverted form.

Abstract: Improved PLL frequency synthesizer circuits, including a novel swallow counter, may be operated at high speeds without experiencing internal delays or malfunctions. The swallow counter supplies a modulus signal to a prescaler which is capable of selectively changing a frequency-dividing ratio of a frequency signal. The swallow counter includes a shift register, a counter, a count-up detector, a modulus signal generator, and a control circuit. The swallow counter is connected to the prescaler and the program counter, and is capable of counting a frequency-divided signal based on a set value data and producing the modulus signal in response to a load signal after counting is completed. The swallow counter supplies the modulus signal to the prescaler and determines whether the set value data is data prepared to fix the frequency-dividing ratio.

Abstract: A dual-modulus prescaler (100) has improved performance for high-speed operation. A timing signal is developed from a flip flop circuit (106) two and one-half clock cycles before the last stage of the prescaler is clocked. The timing signal is used to produce a selector signal to gate a multiplexer (112). Because of the early generation of the timing signal, the multiplexer selection process is removed from the critical path. The remaining delay through the multiplexer is minimal to minimize the critical path of the prescaler.

Abstract: A clock frequency multiplication device comprising a first multiplier for generating an oscillating frequency every first half of a period of an input clock signal where the input clock signal is high in logic, counting the oscillating frequency, dividing the resultant count data at a division ratio of 1/2.sup.

Abstract: A method and apparatus for generating a finely adjustable clock is accomplished by a ring oscillator, a plurality of counting circuits, and a controller. The ring oscillator generates a plurality of oscillations, wherein each of the oscillations have an approximately equal period and are phase shifted by an approximately equal phase shift. Each of the plurality of oscillations is provided to one of the counting circuits which divides the frequency of the respective oscillation by a given count value to produce corresponding periodic representation. The controller selects one of the corresponding periodic representations based on control signal to be the output oscillation, or clock signal. When the clock signal needs to be finely adjusted, the controller, based on the control signal, selects another one of the corresponding periodic representations.

Abstract: The frequency multiplier 10 is embodied by a phase-locked loop including a phase comparator 11 for commanding a plurality of delay elements 130 to 137 that furnish successive phase-shifted signals CL0-CL7 to a logical adder 16 made up of EXCLUSIVE OR gates.

Abstract: A deviation of a clock rate of the timepiece clock signal is determined relative to a reference clock rate of a reference clock signal (CR) which is either issued while the mobile unit is switched on or is contained in a received signal. The reference clock rate is higher than the clock rate of the timepiece clock signal. A count number (N) is calculated based on the deviation of the clock rate of the timepiece clock signal. The clock signal is generated such that the clock pulses the clock signal are successively issued each time the clock pulses of the timepiece clock signal counted up to the count number.

Abstract: An on-chip clock waveform generator for generating from an externally supplied clock (EFI) an on-chip (internal) clock with a 50% duty cycle having a clock rate of 1/2, 1, or 2 times that of EFI, is based on a tapped delay line with a tap-to-tap differential delay of approximately 1% of the external clock (EFI) period. The waveform generator detects the tap at which a full period of delay occurs between delay line input and the tap. By knowing the tap for a first full period delay the generator determines the taps at which the 1/4, 1/2, and 3/4 period waveform states can be observed. The pulses corresponding to fractional periods, are used to generate standard pulse width streams that correspond to 1/4 period intervals. A programmed multiplexer/selector selects the proper sequence from these pulse streams to drive an RS flip-flop in order to produce the output 50% duty-cycle clock running at 1/2, 1, or 2 times the external (EFI) clock.

Abstract: A dynamic latching arrangement with a conditional driver, a system, and a method reduce power consumption, increase operating speed, and reduce the number of discrete components. The conditional driver selectively impresses a signal on an internal node of the circuit such that when a control signal is asserted, a signal related to the clock signal is generated, but when the control signal is not asserted, a different signal related to the clock signal is generated.

Abstract: A programmable digital frequency multiplier includes either a delay locked loop with an input clock or a ring oscillator which generates multiple phase delayed clock signals having a common frequency equal to that of the input clock and a corresponding number of equidistant phases. In the delay locked loop, a phase comparator compares the phase of the input clock as received by the first inverter circuit with the phase of the output of the last inverter circuit and generates an error signal which is used as a circuit bias control signal for each of the inverter circuits, thereby controlling the phase delay through each inverter circuit. The multiple inverter circuit output signals are individually gated in separate NOR gates with a corresponding number of frequency programming bits.

Abstract: This invention relates to a programmable frequency divider that includes a plurality of flip-flops that are clocked at a frequency to be divided. The plurality of flip-flops is operatively arranged to allow the connection in a ring of a predetermined number of them, selected according to a desired frequency division ratio. In one embodiment, the smallest selectable ring includes at least two successive flip-flops that are initialized to a first state, immediately followed by at least two successive flip-flops that are initialized to the opposite state.

Abstract: A frequency multiplication circuit (10) includes a periodic interval selector (12) and a delay element (28) to produce an output signal (26) in phase with, and at a frequency multiple of a reference signal (18). During a first time interval, the periodic interval selector (12) bases the output signal (26) on the reference signal (18). During a second time interval, the periodic interval selector (12) bases the output signal (26) on a delayed signal (22) produced by the delay element (14) based upon the output signal (26). Feedback from the output of the periodic interval selector (12) through the delay element (14) and the operation of the periodic interval selector (12) causes the output signal (26) to be in phase with, and at a frequency multiple of the reference signal (18). Delay adjuster (52) adjusts delay produced by the delay element (14) to adjust the output signal (26) to cause the output signal (26) to have a desired duty cycle consistency.

Abstract: An input buffer circuit for a frequency divider includes a bias circuit including a first group of diodes connected in series and to a power supply voltage terminal, at least first and second resistors connected in series to each other at a first junction, the first resistor being connected in series with the first plurality of diodes, and a second plurality of diodes connected in series, the second plurality of diodes being connected between the second resistor and a ground; an input signal terminal for receiving an input signal from a frequency divider; a reference input terminal for receiving a reference signal; an output signal terminal; a reference output terminal connected to the reference input terminal; an amplitude limiting circuit connected to and between the output signal terminal and the reference output terminal; third and fourth resistors connected in series to each other at a second junction, the third resistor being connected to the output signal terminal and the fourth resistor being connecte

Abstract: A frequency multiplier has a delay circuit consisting of delay units each having a delay time and being connected in series to sequentially delay an input clock signal, a pulse width detector for measuring and storing the width of a pulse of the input clock signal according to the outputs of the delay units, a first selector for selecting one of the outputs of the delay units according to the output of the pulse width detector, a second selector for selecting one of the inverted outputs of the delay units according to the output of the pulse width detector, and first and second output flip-flops. The first and second output flip-flops are reset according to the outputs of the first and second selectors and are set in response to rising and falling edges of the input clock signal, to generate a frequency-multiplied clock signal.

Abstract: The clock generator generates an output clock signal of known frequency from an internally generated high frequency signal of unknown frequency and from a low frequency input signal of known frequency. To this end, the clock multiplier first determines the frequency of the internal clock signal from a comparison with the input clock signal. In one arrangement, the frequency of the internal signal is determined by counting a number of clock transitions occurring during the internal signal within one period of the input clock signal. Once the frequency of the internal signal has been determined, the clock multiplier generates an output clock signal based upon the internal clock signal but adjusted in accordance with the newly determined frequency of the internal clock signal. In one arrangement, the clock multiplier employs a programmable divider.

Abstract: A fractional-N frequency divider system generates an output signal having frequency of an input signal divided by a desired frequency division ratio (N+A/M) in which N is an integer and A/M is a fraction, A.ltoreq.M, and includes a programmable frequency divider receiving input frequency and providing divided frequency in which division ratio (N, N+1) is an integer and is externally supplied, a selector supplying one of the externally supplied integers (N, N+1) to the divider according to a selection signal, and a fractional part set having a first counter initialized to count M, a second counter initialized to count A, and a logic circuit for supplying the selection signal according to the counters. The counters are decremented by an output of the divider and reach zero when they receive M and A number of pulses, respectively. The second counter stops counting operation when it reaches zero.

Abstract: The object of the present invention is to provide a clock synthesizer IC which can produce clock signals with much lower radiated EMI.

Abstract: A clock signal generator for converting a high speed clock signal to a low speed clock signal, the generator including a first counter receiving the high speed clock signal and counting the cycles thereof, the first counter being configured to count to a first preselected value and then generate an output signal indicating when the first preselected value is reached; a second counter receiving the high speed clock signal and counting the cycles thereof, the second counter being configured to count to a second preselected value and then generate an output signal indicating when the second preselected value is reached, wherein the first and second preselected values are different; and an m-state controller receiving the output signals from the first and second counters and generating the low-speed clock signal therefrom, the m-state generator periodically outputting a reset signal to reset the first and second counters to restart counts in each of those counters.

Abstract: A clock signal generator can prevent unnecessary power consumption and can lower the power consumption of a system or a chip as a whole. A clock generator has a plurality of multipliers having variable multiplying factors and multiplying a single input reference clock signal by a designated multiplying factor. A plurality of frequency dividers have variable divide factors and divide a clock signal by a designated dividing factor. A clock selector selects a clock signal which has a required frequency according to a status signal STS from each of the functional locks from among the clock signals having a plurality of frequencies generated by the clock generator. The clock selectors stops the operation of the multipliers or the frequency dividers which are generating unused frequencies by switching clock signals.

Abstract: This frequency dividing device has an input terminal for a signal to be divided and an output terminal for an output signal. It further comprises: a first mixing circuit which is particularly of the sub-harmonic type, has a first input which forms the input terminal, and a second input for receiving a signal from a local oscillator; a first dividing circuit for dividing the output signal of the first mixing circuit; a second dividing circuit for dividing the output signal of the local oscillator; and a second mixing circuit which has a first input for receiving the output signal of the first dividing circuit, and a second input for receiving the output signal of the second dividing circuit, and an output which forms the output terminal.

Abstract: A two-cycle asynchronous first-in/first-out (FIFO) device has a plurality of queue registers for holding data, and control cells coupled to the queue registers for controlling data transfer into and out of the registers. Each control cell includes interconnected first and second latches. The first latch receives a request-in signal from a previous control cell and in response produces an intermediate signal. The second latch receives the intermediate signal and in response supplies a request-out signal to a subsequent control cell. The control cell also has a logic circuit coupled to the queue register and first and second latches. In response to input signals, the logic circuit produces load and hold control signals to the queue register and first and second latches. The device includes two-to-four and four-to-two cycle converters that allow the two-cycle FIFO device to be used in either a two-cycle or a four-cycle environment.

Abstract: A frequency divider/counter circuit utilizing at clock and a clear signal to divide the clock by an odd value. A first adder receives the clock and the clear signal, and has a carry-in input, and generates an adder output and carry-out output. A second adder also receives the clock and the first adder cell carry-out output, and generates an adder output. A reset cell receives the clock and the clear signal, and has an input and generates a reset output. Logic receives selected adder outputs and generates a divider output when the odd value is reached, wherein the first adder receives the divider output as its carry-in input, the second adder receives the carry-out output of the first adder as its carry-in input and the reset output as its clear input, and the reset cell receives the divider output as its input.

Abstract: A frequency converter is provided of which a frequency-dividing ratio is arbitrarily altered and retained after a power is turned off. The frequency converter has a programmable counter which outputs a signal having a desired frequency, a non-volatile memory for storing data for setting the frequency-dividing ratio and a control unit for controlling a writing operation of data stored into the non-volatile memory. The programmable counter, the non-volatile memory and the control unit are accommodated in a single package. The frequency converter may comprise a resonator and an oscillating circuit within the package so that the frequency converter can be treated as a single frequency generator such as a quartz-crystal oscillator.

Abstract: Frequency divider circuit, frequency synthesizer comprising such a divider and radio telephone comprising such a synthesizer. A frequency divider circuit according to the invention includes a succession of N divide-by-two or divide-by-three dividing cells for an input frequency signal, while specific ones of these cells can be disabled to obtain division factors smaller than 2.sup.N.

Abstract: A digital trimming circuit is used to produce a stable time reference signal. This type of reference time signal can be used in equipment, such as watches, which have motors and acoustic outputs that interfere with producing the time reference signal. A basic oscillation frequency, which is produced by an oscillator circuit, is frequency divided to form the generic time reference signal. The digital trimming circuit generates a control signal to shorten the period of the time reference signal by predetermined amounts based on correction data. The control signal is in the form of pulses which can be dispersively applied to create substantially equal intervals between pulses during one time period of the time reference time signal. While maintaining the necessary digital trimming amount in one digital trimming time period, an expansion/reduction amount of the time reference signal is suppressed at one digital trimming time instant.

Abstract: A circuit (10) for generating an output signal having a frequency that is a multiple of an input clock signal (CLKIN). The circuit includes a delay circuit (12) having an input port and a plurality of output ports (A,B,C). The input port is coupled during use to the input clock signal. Individual ones of the plurality of output ports output a signal that is delayed with respect to the input clock signal and also with respect to others of the plurality of output ports. The circuit further includes a logic network (20) having a first input for coupling to the input clock signal and a plurality of second inputs for coupling to the plurality of output ports. The logic network operates to logically combine signals emanating from the plurality of output ports with the input clock signal, and has an output port (OUTPUT) for outputting a signal having a frequency that is multiple of a frequency of the input clock signal.

Abstract: A frequency dividing circuit includes a first inverter circuit supplied with a first frequency-divided signal, a second inverter circuit supplied with a second frequency-divided signal which has a complementary relationship to the first frequency-divided signal, and a first pair of push-pull circuits. There are also provided a first switch circuit performing a first switching operation in response to a first input signal and selectively supplying output signals of the first and second inverter circuits to the first pair of push-pull circuits so that one of the first pair of push-pull circuits performs a pull-up operation when the other one thereof performs a pull-down operation.

Abstract: The invention realizes a serial to parallel conversion circuit which operates at a high speed with low power dissipation. High speed serial data are input and re-timed with a high speed clock input by a first high speed flip-flop. Differential divide-by-eight clock signals are produced by dividing the high speed differential clock input by two using a second high speed flip-flop and are supplied to ninth through eleventh flip-flops, by which divide-by-eight shift clock signals and another series of divide-by-eight shift clocks leading the divide-by-two clocks by a half-period are produced. The output of the first high speed flip-flop is input to a shift register comprising first through fourth flip-flops, and is shifted with the positive phase divide-by-two clock signals. The output of the shift register is then re-timed with the other divide-by-eight shift clock signals described above by twelfth through fifteenth flip-flops.

Abstract: An on-chip clock waveform generator for generating from an externally supplied clock (EFI) an on-chip (internal) clock with a 50% duty cycle having a clock rate of 1/2, 1, or 2 times that of EFI, is based on a tapped delay line with a tap-to-tap differential delay of approximately 1% of the external clock (EFI) period. The waveform generator detects the tap at which a full period of delay occurs between delay line input and the tap. By knowing the tap for a first full period delay the generator determines the taps at which the 1/4, 1/2, and 3/4 period waveform states can be observed. The pulses corresponding to fractional periods, are used to generate standard pulse width streams that correspond to 1/4 period intervals. A programmed multiplexer/selector selects the proper sequence from these pulse streams to drive an RS flip-flop in order to produce the output 50% duty-cycle clock running at 1/2, 1, or 2 times the external (EFI) clock.

Abstract: A digital trimming circuit is used to produce a stable time reference signal. This type of reference time signal can be used in equipment, such as watches, which have motors and acoustic outputs that interfere with producing the time reference signal. A basic oscillation frequency, which is produced by an oscillator circuit, is frequency divided to form the generic time reference signal. The digital trimming circuit generates a control signal to shorten the period of the time reference signal by predetermined amounts based on correction data. The control signal is in the form of pulses which can be dispersively applied to create substantially equal intervals between pulses during one time period of the time reference time signal. While maintaining the necessary digital trimming amount in one digital trimming time period, an expansion/reduction amount of the time reference signal is suppressed at one digital trimming time instant.

Abstract: A frequency multiplier circuit comprising a first delay circuit for delaying sequentially a reference clock signal, a frequency doubler for delaying the reference clock signal and combining logically the delayed reference clock signal and the reference clock signal, a second delay circuit for delaying sequentially an output signal from the frequency doubler, a signal detector for logically combining the output signal from the frequency doubler and a plurality of output signals from the second delay circuit to detect a desired duty factor of signal, a decoder for decoding a plurality of output signals from the first delay circuit and a plurality of output signals from the signal detector to output a signal delayed by n times half a period of the reference clock signal, and a frequency generator for logically combining an output signal from the decoder and the reference clock signal to generate a multiple frequency of that of the reference clock signal.

Abstract: An N+1 frequency divider counter (20) has a binary counter (22), ones detect circuitry (26), control logic (24), and an output flip-flop (28). The binary counter (22) counts from an initial value to a final value for each half of an output clock signal. If N+1 is an even number, one full cycle is added to each half cycle of the output clock signal. If N+1 is an odd number, one-half of a cycle is added to each half phase of the output clock signal. At the final count value, the control logic (24) causes the output clock signal to transition on either the rising edge or the falling edge of an input clock signal. The N+1 counter (20) has a fifty percent duty cycle for all count values of N, and does not require additional circuitry to accommodate when N equals zero.

Abstract: A dynamically switchable clock system having a symmetrical output signal includes a frequency doubler which couples the input frequency to provide greater resolution and synchronization of an output signal to an input signal in the frequency divider and the facility to handle odd divides as even divides at double frequency, a counter controlled by a divisor select signal, first and second compare circuits which compare against the preprogrammed count for division, the compare circuits receiving an input from the divisor select circuits, and having outputs to a counter reset line and to an output clock S/R latch which provides the frequency divided symmetrical output signal.

Abstract: A device for doubling or dividing by 2 the flow rate of series bits comprising a succession of first one-bit registers (R4-R0) actuated at a frequency F; a second register (R) actuated at a frequency 2F; an input terminal (IN) connected to the input of the first (R4) of the first registers and, through a first gate (T5), to an internal line (L) connected to the input of the second register; first multiplexers (M4-M1) connected to the input of each second (R3) to last (R0) of the first registers for selecting either the output of the preceding register, or the internal line, or still the output of the second register; a second multiplexer (M), which selects either the output of the last (R0) of the first registers, or the output of the second register, or filling bits; second transfer gates (T4-T0) between the output of each first register and the internal line; and means for controlling the various gates and multiplexers.