Abstract: A frequency-divider circuit performs a division operation using a divisor that can include a fraction. In one such embodiment, a first divider module includes a divider circuit that operates to divide the frequency of an input clock signal and a phase-quadrature circuit. The first divider module generates a first-divider-output signal having periodic signals with regular phase displacement therebetween and a common period that is an integer multiple of the clock signal. Using this first-divider-output signal, a second divider module performs another divide operation and is clocked as a function of a delay effected by at least one of the periodic signals. The present invention is useful in a wide variety of applications including applications having a high frequency clock source that cannot tolerate excessive loading or jitter attributable to a divider circuit.

Abstract: A method and system described for producing frequency multiplication/division by any non-integer output signal frequency relative to a reference signal frequency of a Phase Lock-Loop (PLL), while simultaneously maintaining low jitter. In one embodiment, the invention increases the number of the available clock phases to M and then shifts the output clock phase by one, every K/M cycle. In one aspect of the present invention, this is accomplished by adding a multiplexer (MUX) to the output of the PLL to implement the phase shifting every K/M cycles. In another aspect, the MUX is placed in the feedback loop of the PLL. In one embodiment, a quantizer is used to drive the MUX.

Abstract: A programmable divider includes a synchronous counter configured to process an input clock signal and produce first output signals in response the input clock signal. A number of logic devices are coupled to the synchronous counter and configurable to receive the first output signals and correspondingly produce second output signals. Also included is a multiplexer that is configured to receive the second output signals and has an output coupled to an input of the synchronous counter. In the programmable divider, characteristics of the synchronous counter are selectable based upon a particular number of the logic devices configured.

Abstract: A frequency divider circuit for providing a divided clock signal having a frequency that is an odd integer factor less than the frequency of an incoming system clock signal. The frequency divider includes a clock generator circuit coupled to a delay circuit which operates in an active and a reset phase to provide a divided clock signal from the system clock signal. In the active phase, the clock generator circuit drives the divided clock signal to a first logic state until a reset signal is received. The delay circuit then generates the reset signal at a predetermined number of system clock edges after the divided clock signal is driven to the first logic state. In the reset phase, both the clock generator circuit and the delay circuit are reset in response to the reset signal such that the clock generator circuit immediately drives the divided clock signal to a second logic state, and the delay circuit disables the reset signal within the predetermined number of system clock edges.

Abstract: Various apparatus and method embodiments are disclosed.

Abstract: A synchronous prescaler is provided that has an input line for receiving an input signal, which is synchronized to a low order dual modulus prescaler. The dual modulus prescaler generally divides responsive to a mode command line, but may have a dead-zone period where it may fail to respond to a generated mode command. The dual modulus prescaler also has an output line that is synchronized to an extender section. The extender section is used to further divide the input signal, and is synchronized to an adjustable counter section. A sync controller circuit receives an output from the counter section, as well as a timing signal from the extender, and generates the mode signal on the mode command line. In this arrangement, the sync controller generates the mode signal at a time when the low order dual modulus is in a condition to change divide modes, thereby avoiding providing the signal during the dead-zone period.

Abstract: A frequency divider having an input frequency divider, an edge counter, and an output generator. The input frequency divider generates an intermediate signal having a frequency of fi from an input signal having a frequency fin, wherein fin=2fi. The edge counter generates a value equal to the number of edges in the intermediate signal that have occurred since a reset signal was generated. The output generator generates an output signal when the edge counter value reaches a value Q and generates the reset signal. In one embodiment, the edge counter includes a positive edge counter that counts the number of positive going transitions in the intermediate signal since the reset signal, a negative edge counter that counts the number of negative going transitions in the intermediate signal, and an adder that generates the sum of the positive and negative count values.

Abstract: A programmable frequency divider circuit with symmetrical output is disclosed. The frequency divider includes a non-symmetrical LFSR based component operated in series with a symmetrical divider component. Both the LFSR and the symmetrical divider may be programmed to provide flexibility. The frequency divider can dynamically adjust the divisor of the LFSR component to overcome limitations in the divide resolution due to the series combination of dividers, providing even and odd divisor values. The divider architecture can also provide higher level functions, including synchronization of multiple divider outputs, dynamic switching of divisor values and generation of multi-phased and spaced outputs. The linear feedback shift register (LFSR) component includes a feedback logic network decomposed into multiple stages to realize a maximum latch-to-latch operational latency of one gate delay regardless of the size of the LFSR.

Abstract: An MN counter with analog interpolation (an “MNA counter”) includes an MN counter, a multiplier, a delay generator, and a current generator. The MN counter receives an input clock signal and M and N values, accumulates M for each input clock cycle using a modulo-N accumulator, and provides an accumulator value and a counter signal with the desired frequency. The multiplier multiplies the accumulator value with an inverse of M and provides an L-bit control signal. The current generator implements a current locked loop that provides a reference current for the delay generator. The delay generator is implemented with a differential design, receives the counter signal and the L-bit control signal, compares a differential signal generated based on the counter and control signals, and provides the output clock signal. The leading edges of the output clock signal have variable delay determined by the L-bit control signal and the reference current.

Abstract: A method includes generating N reference clocks with period T and phases uniformly distributed in 360 degrees; using each of the N reference clocks to trigger M intermediate signals with period M*T and phases uniformly distributed in 360 degrees; and performing a logic operation between at least two intermediate signals respectively corresponding to two different reference clocks to generate an output clock with period (M/N)*T to achieve non-integer frequency division.

Abstract: A frequency divider circuit uses a base counter to frequency divide a clock signal with period T by an integer value N and employs a cyclic rotational select circuit to select among multiple equally phase shifted signals of a multiple phase clock to generate a fractional term P/k where P is variable from 0 to k?1. The counter counts an output clock that corresponds to the output of a multiplexer selecting from among the multiple clock phases. Depending on the desired fractional term, after N counts of the output clock phases of the multiple phase clock are selected glitch free by rotationally selecting a first phase, and skipping either 0, 1, 2 . . . up to k?1 sequential phases to generate fractional terms 0, 1/k, 2/k, 3/k . . . k?1/k, respectively, thus providing frequency division corresponding to N+P/k where P may be varied from 0 to k?1.

Abstract: A system and method for improving the signal-to-noise ratio of a frequency generator suppresses phase noise and noise generated from mismatches in the internal generator circuits. This is accomplished using a modulation scheme which shifts spurious noise signals outside the loop bandwidth of the generator. When shifted in this manner, the noise signals maybe removed entirely or to any desired degree using, for example, a filter located along the signal path of the generator. In one embodiment, a Sigma-Delta modulator controls the value of a pulse-swallow frequency divider situated along a feedback path of a phase-locked loop to achieve a desired level of noise suppression. In another embodiment, a reference signal input into a phase-locked loop is modulated to effect noise suppression. In another embodiment, the foregoing forms of modulation are combined to accomplish the desired frequency shift.

Abstract: A fractional divide circuit for generating a periodic fractional clock is disclosed. A base clock is provided for generating a pre-divide clock at a base clock frequency with a period counter provided for counting cycles of the base clock. A select register stores constants that define parameters for a fractional divide ratio, there being at least four. A positive edge flip flop is provided wherein two of the constants are associated therewith. A negative edge flip flop is provided wherein the other of the two constants are associated therewith.

Abstract: A frequency divider circuit (11) has an input port for an input signal (Fo) to be divided, an output port for a divided signal (FDIV), and means (12-19) for providing a variable division-ratio control signal (N+C) and a residual quantization error signal (R), applying the variable division ratio control signal (N+C) to a control port of the frequency divider, and using the residual quantization error signal (R) to cancel phase error in the divided signal. Both the variable division ratio control signal (N+C) and the residual quantization error signal (R) are dithered.

Abstract: A method and system described for producing frequency multiplication/division by any non-integer output signal frequency relative to a reference signal frequency of a Phase Lock-Loop (PLL), while simultaneously maintaining low jitter. In one embodiment, the invention increases the number of the available clock phases to M and then shifts the output clock phase by one, every K/M cycle. In one aspect of the present invention, this is accomplished by adding a multiplexer (MUX) to the output of the PLL to implement the phase shifting every K/M cycles. In another aspect, the MUX is placed in the feedback loop of the PLL. In one embodiment, a quantizer is used to drive the MUX.

Abstract: A system that includes a first circuit configured generate a first set of encoded signals in response to a first clock signal and a second circuit configured to generate a second set of encoded signals in response to the first clock signal is provided. The system also includes a third circuit configured to generate a first pulse signal and a second pulse signal in response to the first set of encoded signals and the second set of encoded signals, and a fourth circuit configured to generate a second clock signal in response to the first pulse signal and the second pulse signal.

Abstract: A frequency generating circuit utilizes a quad modulus prescaler in which two control signals are used to select the prescaler modulus. The modulus control signals are generated by a multistage counter in which two independent counting stages are used to generate the first and second modulus control signals. The first modulus control signal is at a first logic level when the associated counter is at a non-zero value and is at a second logic level when the associated counter reaches zero. The second modulus control signal is generated by a second counter and has a first logic value when the second counter is in a non-zero state and a second logic value when the second counter reaches zero.

Abstract: A programmable divider includes a synchronous counter configured to process an input clock signal and produce first output signals in response the input clock signal. A number of logic devices are coupled to the synchronous counter and configurable to receive the first output signals and correspondingly produce second output signals. Also included is a multiplexer that is configured to receive the second output signals and has an output coupled to an input of the synchronous counter. In the programmable divider, characteristics of the synchronous counter are selectable based upon a particular number of the logic devices configured.

Abstract: In one embodiment, as an example, N/M (=3.33333 . . . ) dividing is performed assuming M=3, N=10. That is, the frequency of the input signal CK is converted to the frequency of 1/3.33333 . . . times. Here, it is assumed that the frequency dividing number is 3.33333 . . . In this case, 3(=n) dividing is combined with 4(=n+1) dividing to perform the dividing, and accordingly a signal of a desired frequency can be obtained. In response to the output DOUT of the frequency divider, an n dividing counter counts the number of performed n-dividing operations and an n+1 dividing counter counts the number of performed n+1-dividing operations. An adder outputs the frequency dividing number (n) or (n+1). A frequency divider uses the frequency dividing numbers to divide an arbitrary frequency signal CK.

Abstract: A non-integer frequency divider is disclosed. The non-integer frequency divider circuit includes several base stages connected to each other. The non-integer frequency divider circuit also includes a clocking circuit for passing an enable bit from one of the base stages to another such that only one of the base stages is enabled at any give time. The enable bit has a pulse width of one clock cycle. The outputs from the base stages are grouped together by an OR gate to generate a single output that is a fraction of an input clock signal.

Abstract: A fractional clock divider system and method is provided. The clock divider is configured to provide an output clock signal in response to an input clock signal. The frequency of the output clock signal may be an integral or fractional division of the input clock signal. The output frequency is equal to: (ref_freq*2)/mul, where ref_freq is the frequency of the input clock signal, and mul is a selected integer that is greater than one. The positive and negative edges of the input clock are counted to provide a positive count and a negative count respectively. A table is configured to store preselected reference values. A logic circuit is configured to control the output clock signal such that an appropriate clock transition occurs in the output clock signal when the positive and negative count reach the corresponding preselected reference values.

Abstract: A system that includes a first circuit configured generate a first set of encoded signals in response to a first clock signal and a second circuit configured to generate a second set of encoded signals in response to the first clock signal is provided. The system also includes a third circuit configured to generate a first pulse signal and a second pulse signal in response to the first set of encoded signals and the second set of encoded signals, and a fourth circuit configured to generate a second clock signal in response to the first pulse signal and the second pulse signal.

Abstract: A system may include a control unit and a dual modulus prescaler. The control unit may generate a modulus control signal. The dual modulus prescaler may be configured to divide the frequency of an input signal by Q when the modulus control signal has a first value and to divide the frequency of the input signal by (Q+V) when the modulus control signal has a second value. Q is an irreducible fraction. The sum (Q+V) may be an integer or a fraction. The dual-modulus prescaler includes several clocked storage units (e.g., flip-flops) that are each clocked by a respective one of several equally spaced phases of the input signal. Each clocked storage unit operates in a toggle mode.

Abstract: This invention provides a circuit and a method for programmable counters. It consists of a circuit and a method for unique programmable counters that provide half-integral as well as integral steps, such as 1.5, 2, 2.5, 3, 3.5, 4. This circuit and method are the first implementations of providing programmable counting with half-integral steps. The circuit and method of this invention can be extended via the cascading of toggle flip flops at the front end of the circuit of this invention. This provides the ability to enhance the speed of normal integral step counting applications. In addition, the cascading of the multiple copies of the circuit of this invention provides the ability to provide other fractional programmable counters. A key advantage of this invention is that the method of this invention is general enough to use any other type of counter sub-component beside the binary counter sub-component of this invention.

Abstract: A fractional-N frequency synthesizer has a modulus controller with multiple inputs that control an initial output frequency of the frequency synthesizer, an increment of variation of tuning of the frequency synthesizer, and a difference between two adjacent output frequency settings. The fractional frequency synthesizer includes a modulus controller, which controls the modulus factor for a multiple modulus frequency divider. The modulus controller has a modulus selection circuit that provides a modulus control signal to the modulus divider to select the modulus factor of the modulus divider as a function of a sum of one input factor and a product of a second input and the gain factor. Control signal is an overflow from a continuous summation of the second digital data word and a product of the first digital data word and the gain factor digital data word repetitively with itself.

Abstract: A multi-selection prescaler for dividing an input signal according to a ratio to obtain a desired frequency. The circuit has of a plurality of logic gates and D-flip-flops: a first frequency divider for receiving an input signal and generating a divided frequency; a second frequency divider connected to the first frequency divider for performing a further frequency division based on a selection switch having a plurality of selection signals and a plurality of AND gates; a module control for performing a logic operation on the selection signals and an external control signal (MC) by OR gates and being connected to the first frequency divider to control the divided frequency of the first frequency divider; and an output selection circuit connected to the second frequency divider for selecting output signal according to the selection signals.

Abstract: A frequency divider device including: a divider input: a phase count and select section including: at least two phase count and select inputs each communicatively connected to the divider input, for receiving each at least one phase shifted signal having a phase difference with respect to the other phase shifted signal; a signal generator section for generating an output signal; a switch device having switch inputs each connected to said at least one of said phase count and select inputs, said switch device further having at least one switch output, said switch device connecting a selected input of said switch inputs with said switch output, an inverter device for switching said output signal from a current state to a substantially inverse state if a selected signal from a current state to a substantially inverse state if a selected signal from said selected input has a transition from a first state to s a second state; a counter device for determining a number of periods of said selected signal; a switch act

Abstract: A frequency prescaler includes an asynchronous counter having a least significant stage clocked by an input signal, and a first true single phase clock flip-flop having an input stage with an embedded logic gate to decode a state of the asynchronous counter, configured to modify a modulus of the asynchronous counter.

Abstract: A non-integer fractional divider is disclosed. According to the present invention, the non-integer fractional divider comprises means for dividing a reference clock signal having a period ‘P’ by a non-integer ratio ‘K’. In a preferred embodiment, the divider comprises means for receiving a plurality ‘N’ of clock signals issued from the reference clock signal and wherein each clock signal is equally phase shifted by a ‘P/N’ delay one over the other. Selection means are coupled to the receiving means for selecting a first and a second clock signals between the plurality ‘N’ of clock signals. The selected clock signals are such that the phase shift delay between the two selected clock signals is representative of the non-integer value of the ratio ‘K’. The selected clock signals are combined into combining means to generate a clock signal being phase shifted by the non-integer part of the non-integer ratio.

Abstract: An improved fractional divider that comprises an integer value storage means containing the integer part of the division value ‘K’ connected to the input of a programmable counter means that is configured for a count value of ‘K’ or ‘K+1’ depending upon the state of a count control signal and generates the output signal as well a terminal count signal which is connected to an enable input of a fractional accumulator means that produces the count control signal on an addition overflow and has a first input connected to its result output and a second input connected to the output of a fractional value storage means, containing the fractional part of the divider value.

Abstract: A fractional-N frequency synthesizer has a modulus controller with multiple inputs that control an initial output frequency of the frequency synthesizer, an increment of variation of tuning of the frequency synthesizer, and a difference between two adjacent output frequency settings. The fractional frequency synthesizer includes a modulus controller, which controls the modulus factor for a multiple modulus frequency divider. The modulus controller has a modulus selection circuit that provides a modulus control signal to the modulus divider to select the modulus factor of the modulus divider as a function of a sum of one input factor and a product of a second input and the gain factor. Control signal is an overflow from a continuous summation of the second digital data word and a product of the first digital data word and the gain factor digital data word repetitively with itself.

Abstract: A programmable-divider provides a lower-speed transition signal to effect a synchronized load of a new divisor value during a safe-load period of the programmable-divider, such that the division occurs using either the prior divisor value or the new divisor value, only. A combination of in-phase and reverse-phase counter stages are used to position the divisor-independent period of each counter stage so that an edge of at least one of the lower-speed counter-enabling signals occurs during a period when all of the counter stages are in a divisor-independent period. The preferred selection of in-phase and reverse-phase counter stages also maximizes the critical path duration, to allow for the accurate division of very high speed input frequencies.

Abstract: The dual-modulus prescaler circuit for a frequency includes several dividers-by-two of the asynchronous type, connected in series, a phase selector unit (11) inserted between two of the dividers-by-two (10, 12a) and a control unit for supplying first control signals(S0, S1, S2, C1, C2) to the selector unit as a function of a selected mode. Said control unit receives four signals phase shifted by 90° with respect to each other from a first master-slave divider and supplies a selected one of the four phase shifted signals. The selector unit includes a first amplifying branch (21) receiving two first phase shifted signals (F2I, F2Ib), a second amplifying branch (22) receiving two second phase shifted signals (F2Q, F2Qb), and a selection element (23) connected to each branch. The first control signals (S0, S1, S2) are supplied to the first and second branches, and to the selection element for selecting one of the four phase shifted signals (F2) at one output in a determined division period.

Abstract: The invention features a fractional frequency divider including a phase selection device where mutually phase-shifted signals are alternately switched through to a phase output, at the input of the phase selection device; and a control device for selecting individual phases where the control device changes the mutually phase-shifted signals.

Abstract: A digital, preferably programmable, circuit is disclosed for providing one or more clock signals with variable frequency and/or phase. The clock signals exhibit a low amount of skew relative to other clock signals and data signals provided by the circuit. In one embodiment, the circuit includes a plurality of channels each having a parallel-in/serial-out shift register, a flip-flop, and a delay circuit. The shift register can receive data bits in data channels or clock frequency select bits in frequency-divided clock channels. The serial output from the register acts as an input for the flip flop, both of which are triggered by an input reference clock. The delay circuit delays the input reference clock. In each channel, a multiplexer is configured to select the clock or data channel output from the register, flip-flop, and delay circuit outputs. Since the delays in all output paths are matched, skew is minimized.

Abstract: A method and system described for producing frequency multiplication/division by any non-integer output signal frequency relative to a reference signal frequency of a PhaseLock-Loop (PLL), while simultaneously maintaining low jitter. In one embodiment, the invention increases the number of the available clock phases to M and then shifts the output clock phase by one, every K/M cycle. In one aspect of the present invention, this is accomplished by adding a multiplexer (MUX) to the output of the PLL to implement the phase shifting every K/M cycles. In another aspect, the MUX is placed in the feedback loop of the PLL. In one embodiment, a quantizer is used to drive the MUX.

Abstract: To generate a target frequency from a basic frequency, a phased signal of the basic frequency and of a phase controllable by a phase clock signal is generated in accordance with the invention, the target frequency being generated by dividing the frequency of the phased signal by an output dividing factor and the phase clock signal being generated from the phased signal irrespective of the target frequency. A wider range of target frequencies can be obtained in this way. Also, the switching pattern in which the phase of the phased signal is changed can be made independent of the state of the phased signal, thus giving further possible ways of acting on the target frequency.

Abstract: A frequency dividing circuit divides a master clock frequency by a non-integer factor to provide an output clock signal whose frequency is equal to the frequency of the master clock signal divided by that non-integer factor. In one embodiment, the circuit is operative to divide the master clock frequency by 2.5.

Abstract: A programmable frequency divider capable of a 50% duty cycle at odd and even integer division ratios. In one embodiment, the frequency divider is configured to produce an output signal having a period equal to a division ratio N times a period of a clock signal, and the division number N is a programmable variable which bears the following relationship to the number F of required storage elements: F = N + P 2 , where P is 1 if the division ratio is odd, and 0 if the division ratio is even.

Abstract: A digital frequency divider includes phase control of the output signal in increments of whole or half cycles of the input frequency. Whole cycle phase control is achieved by varying (logically or physically) the tap off point of a shift register loaded with a bit pattern for appropriate division. Half cycle phase changes are achieved by a multiplexer selecting one of two signals every half cycle.

Abstract: A frequency divider includes a clock inversion circuit, an inverter, a delay processing circuit and serially connected data storage units. The clock inversion circuit receives an output of the final data storage unit and a clock signal of original oscillation, logically inverts the clock signal at a change of the output of the final data storage unit, and outputs the inverted clock signal to odd-numbered data storage units and even-numbered data storage units in a complementary manner as an input control signal. The inverter and delay processing circuit logically invert the output of the final data storage unit, provide the output of the final data storage unit with a predetermined delay, and input the delayed output to the data input of the first data storage unit.

Abstract: The present invention relates to a structure of a delta-sigma fractional type divider. The divider structure adds an external input value and an output value of a delta-sigma modulator to modulate a value of a swallow counter. Therefore, the present invention can provide a delta-sigma fractional type divider the structure is simple and that can obtain an effect of a structure of a delta sigma mode while having a wide-band frequency mixing capability.

Abstract: A programmable divider includes a synchronous counter configured to process an input clock signal and produce first output signals in response the input clock signal. A number of logic devices are coupled to the synchronous counter and configurable to receive the first output signals and correspondingly produce second output signals. Also included is a multiplexer that is configured to receive the second output signals and has an output coupled to an input of the synchronous counter. In the programmable divider, characteristics of the synchronous counter are selectable based upon a particular number of the logic devices configured.

Abstract: A system and method is presented for dividing a reference clock frequency by any real number. The invention allows for a real number divisor that could have any desired degree of precision. Additionally, the invention seeks to minimize hardware complexity in realizing such a reference-clock frequency divider. In one particular embodiment of the invention, a system and method is presented, wherein the real number divisor is a real number having a repeating decimal (i.e., the real number may be represented by a fraction).

Abstract: A multi-modulus prescaler with a terminal count request input, which when set causes the prescaler to produce an output pulse with edges synchronous with the input clock. The prescaler is driven by a control circuit which produces a terminal count request output which enables the prescaler to generate a terminal count output pulse whose active edge, irrespective of the divide ratio, is always a fixed number of input clock cycles before or after the end of the prescaler control cycle.

Abstract: A novel 2/3 full-speed divider operating at high speed with low power consumption comprising a ECL D flip-flop in master-slave configuration and a phases-selection block is provided in the present invention. The master latch and slave latch comprise a pair of input terminals, a pair of control terminals, and a pair of output terminals. The master latch further comprises two pairs of complementary cross-couple transistors for amplifying the output of the master latch for entering the phase-selection block. The phase-selection block has a pair of input terminals, a clock signal input terminal, and an output terminal generating an output signal adjusted by a division ratio according to the clock signal. The division ratio is either 1/2 or 1/3 and the divider functions as a 2/3 divider.

Abstract: A method and apparatus for dividing a signal's frequency by a non-integer value is provided. Further, a method and apparatus for dividing a signal's frequency by a non-integer value by counting phases of the signal is provided.

Abstract: A prescaler is used for generating an output frequency from an input frequency by fractional division. It comprises a component signal composer (402) arranged to generate a number of parallel component signals that differ in phase from each other. Additionally it comprises a controllable phase selector (403) arranged to respond to a control signal by either selecting a constant number of unchanged ones of the parallel component signals or to repeatedly change its selection among the parallel component signals. The component signal composer (402) is arranged to generate more than four parallel component signals for the phase selector (403) to choose from.

Abstract: To divide a clock signal, a clock pulse counter counting clock pulses of the clock signal is in each case alternately reset after passing through different count differences. In this process, a first signal and a second signal is formed, the logic state of which is in each case changed with the presence of a first or, respectively, second predetermined count of the clock pulse counter by a rising or, respectively, falling clock signal edge. A divided output clock signal is then generated by a logical operation on the first and the second signal.

Abstract: Accumulator 201 accumulates data K (K: integer) for every clock and outputs a carry-out signal at the time of an overflow. Random signal generator 202 outputs a random signal for every clock. Adder 203 adds the carry-out signal and random signal to data M (M: integer), changes the frequency dividing ratio randomly and converts spurious to white noise. This makes it possible to optimally maintain the spurious characteristic, shorten the lockup time and reduce power consumption.