Abstract: Apparatus is disclosed wherein the average period of a synthesized signal is a non-integral multiple of the period of a given signal. The apparatus is arranged so that a counter alternates its count between N and N+1, wherein N is a predetermined integer, in a predetermined pattern so that the average count approximates a rational non-integral value between N and N+1.

Abstract: A programmable counter system of the swallow operation type using binary counters is disclosed. The counter comprises a prescaler for frequency dividing an input signal by a frequency division factor "2.sup.n -1" or "2.sup.n ", upper and lower order bit counters for counting down an output signal from the prescaler, a flip-flop for selecting either the frequency division factor "2.sup.n -1" or "2.sup.n " according to the logical level of the output signal of the counter A or B, and inverters for level inverting programming data and applying them to the lower order bit counter A, thereby setting a division number of the counter A to a complement of the binary code of the programming data.

Abstract: Division by fractions is accomplished with a counter (Z) presettable to integers and a digitally adjustable delay line (V) following this counter. The fractional parts (b) of the divisor, which are held in decimal point representation (a+0.b) in a divisor register (R), are applied to a first adder (A1) followed by a buffer memory (S), and the integral parts (a) of this divisor are applied to a second adder (A2). The output of the buffer memory (S) is coupled to the set input (Es) of the delay line (V) and to the second input (E2) of the first adder (A1). Thus, at the input of the delay line (V), the number corresponding to the fractional parts (b) is continuously increased by the fractional parts (b) until the overflow output (Ao) of the first adder (A1) provides a signal which is applied to the least significant digit (LB) of the first input (E1) of the second adder (A2). One unit is thus added to the integral parts (a), and the counter (Z) counts one additional digit for one cycle.

Abstract: A frequency-dividing circuit comprises an asynchronous counter having a plurality of one-half frequency-dividers connected in series in a plurality of stages in which a master clock signal is applied to an input terminal of the initial stage, for asynchronously producing output signals of each of the one-half frequency-dividers, where the asynchronous counter is set with a preset data n (n is an integer) which is preset according to a desired frequency-dividing ratio when a load pulse is applied, a coincidence detection circuit for detecting the coincidence of a plurality of outputs supplied from the asynchronous counter, and a frequency-divided output signal and load pulse generation circuit supplied with the master clock signal and an output signal of the coincidence detection circuit, for generating a frequency-divided output signal and a load pulse. The frequency-divided output signal and load pulse generation circuit supplies a load pulse to the asynchronous counter.

Abstract: A frequency synthesizer or a circuit for deleting cycles from a wave source includes a dual modulus counter responsive to a reference frequency source of the synthesizer or waves of the source. The dual modulus counter selectively decreases the number of cycles of the source by the factors K.sub.2 and (K.sub.2 +1). A frequency divider divides the frequency of the source by a third factor L to derive an output wave. The dual modulus counter is activated so it divides by K.sub.2 +1, whereby the dual modulus counter derives an output signal having a frequency F.sub.0 =F.sub.in /K.sub.2 (1-1/L), where F.sub.in equals the frequency of the source, L is an integer and K.sub.2 is an integer greater than L.

Abstract: Subharmonics of a data waveform are generated for the purpose of reducing ta bandwidth prior to transmission. Input data waveform is phase split and the antiphased output signals are fed to a rectifier. The rectification of antiphased signals creates two pulsating voltage with opposite polarity. The pulsating voltages are alternately switched by a chopper to provide a sinusoidal signal. The sinusoidal signal is filtered to average the energy of the pulsating voltage to provide a smooth waveform of one-half the frequency of the input data waveform.