With Programmable Counter (i.e., With Variable Base) Patents (Class 377/52)
  • Patent number: 10163467
    Abstract: Examples of the present disclosure provide apparatuses and methods for multiple endianness compatibility. An example method comprises receiving a plurality of bytes in a non-bit-sequential format. The method includes reordering the bits in each byte of the plurality of bytes such that the plurality of bytes are arranged in a bit-sequential format.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: December 25, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Kyle B. Wheeler, Timothy P. Finkbeiner, Jeremiah J. Willcock
  • Patent number: 9590637
    Abstract: A frequency divider includes a multiplexer having a first input terminal coupled to receive a first value M and a second input terminal for receiving a second value that is M+LSB, the multiplexer is configured to alternately output the first value M and the second value. The frequency divider includes a multi-modulus divider coupled to the multiplexer for receiving the output of the multiplexer, the multi-modulus divider operable to alternately generate an output pulse at M input clock cycles and at M+LSB clock cycles. A divide-by-two counter having an input coupled to the output of the multi-modulus divider, is operable to divide the output of the multi-modulus divider to generate a divided clock signal having a frequency of N, where N is equal to 2M+LSB. Duty cycle correction logic is coupled to the output of the divide-by-two counter and is configured to correct the duty cycle of the divided clock signal to a fifty percent duty cycle when N is odd.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: March 7, 2017
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Pak-Kim Lau, Min Chu
  • Patent number: 9374257
    Abstract: A method and apparatus for measuring and tracking Impulse Noise parameters in a communication system are described. The method includes estimating one or more parameters of the impulse noise, the parameters including a period, an offset and duration of the impulse noise.
    Type: Grant
    Filed: March 15, 2006
    Date of Patent: June 21, 2016
    Assignee: Broadcom Corporation
    Inventor: Hossein Sedarat
  • Patent number: 9106216
    Abstract: An electronic device includes a configurable pulse generator configured to generate a programmable master pulse train. One or more functional circuits of the electronic device includes a programming interface to receive one or more a programmable slave pulse parameters for the one or more functional circuits. The programmable slave pulse parameters are dependent upon the programmable master pulse train. A slave pulse generator generates a slave pulse for one of the functional circuits based on the one or more programmable slave pulse parameters corresponding to the functional circuits relative to the programmable master pulse train.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: August 11, 2015
    Assignee: Microsoft Technology Licensing LLC
    Inventors: Avdhesh Chhodavdia, Michael S. Fenton, Sheethal Somesh Nayak
  • Patent number: 8964931
    Abstract: A counter is provided, where, as the number of events that occur increases, the frequency in which the events are counted is scaled.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 24, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Joseph Daniel Gleason
  • Publication number: 20140270049
    Abstract: A counter is provided, where, as the number of events that occur increases, the frequency in which the events are counted is scaled.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventor: Joseph Daniel Gleason
  • Patent number: 8514999
    Abstract: Occurrences of a particular event in an electronic device are counted by incrementing an event counter each time a variable number of the particular events have occurred, and automatically increasing that variable number as the total count increases. The variable number (prescale value) can increase geometrically according to a programmable counter base each time the count mantissa overflows. The event counter thereby provides hardware-implemented automatic prescaling while significantly reducing the number of interface bits required to support very large count ranges, and retaining high accuracy at very large event counts.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: August 20, 2013
    Assignee: International Business Machines Corporation
    Inventors: Giles R. Frazier, Venkat R. Indukuru, Alexander E. Mericas, John F. Spannaus
  • Patent number: 8395539
    Abstract: In a double data rate (DDR) counter and counting method used in, for example, an analog-to-digital conversion in, for example, a CMOS image sensor and method, a first stage of the counter generates a least significant bit (LSB) of the value in the counter. The counter includes at least one second stage for generating another bit of the value in the counter. An input clock signal is applied to a data input of the first stage and a clock input of the second stage.
    Type: Grant
    Filed: December 7, 2009
    Date of Patent: March 12, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong Lim, Kyoung-Min Koh, Kyung-Min Kim
  • Patent number: 8218712
    Abstract: A method and apparatus for dividing clock frequencies are disclosed. For example, a circuit according to one embodiment of includes a high-speed divider and a plurality of programmable dividers cascading with the high-speed divider, wherein the plurality of programmable dividers are of a lower speed than the high-speed divider.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: July 10, 2012
    Assignee: Xilinx, Inc.
    Inventors: Xuewen Jiang, Adebabay M. Bekele
  • Patent number: 8189732
    Abstract: A counter is efficiently implemented in non-volatile memory by using two binary counters and selectively using one or the other as a current counter. Writes to the binary counters are minimized by using two linear counters and using the state of the binary counters to determine which binary counter contains the current count. Write operations can be performed to the “not current” binary counter with the final write operation being to the linear counters. The linear counter write operations can be in program-only mode so that a power failure will not result in a loss of counts.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: May 29, 2012
    Assignee: Atmel Corporation
    Inventors: Randall Wayne Melton, Brad Phillip Garner, Kerry David Maletsky
  • Patent number: 7990304
    Abstract: In a double data rate (DDR) counter and counting method used in, for example, an analog-to-digital conversion in, for example, a CMOS image sensor and method, a first stage of the counter generates a least significant bit (LSB) of the value in the counter. The first stage includes a first clock input and is edge-triggered on one of the rising and falling edges of a signal applied at the first clock input. The counter includes at least one second stage for generating another bit of the value in the counter. The second stage includes a second clock input and is edge-triggered on the other of the rising and falling edges of a signal applied at the second clock input.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: August 2, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong Lim, Kyoung-Min Koh, Kyung-Min Kim
  • Patent number: 7961837
    Abstract: A control unit that outputs a plurality of control signals in response to the input of a plurality of counter enable signals allocated into the numerical value of a multiple of 2 is provided. An operating unit increments or decrements by a multiple of 2 in response to input of the plurality of control signals and count up-down signals.
    Type: Grant
    Filed: October 26, 2009
    Date of Patent: June 14, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jae-Boum Park, Young-Bo Shim
  • Publication number: 20100080336
    Abstract: In an embodiment, a circuit device includes a first counter responsive to a clock signal and to a first control word having a first precision. The counter produces a first control signal related to the first control word at a first output. The circuit device farther includes a second counter responsive to the clock signal and to a second control word having the first precision. The second counter produces a second control signal related to the second control word at a second output. The circuit device also includes a filtering circuit responsive to the first output and the second output to receive the first and second control words. The filtering circuit is adapted to produce an output control signal related to the first and second control words, where the output control signal has a second precision that is greater than the first precision.
    Type: Application
    Filed: September 26, 2008
    Publication date: April 1, 2010
    Applicant: Silicon Laboratories, Inc.
    Inventor: John Gammel
  • Publication number: 20100046694
    Abstract: A control unit that outputs a plurality of control signals in response to the input of a plurality of counter enable signals allocated into the numerical value of a multiple of 2 is provided. An operating unit increments or decrements by a multiple of 2 in response to input of the plurality of control signals and count up-down signals.
    Type: Application
    Filed: October 26, 2009
    Publication date: February 25, 2010
    Applicant: Hynix Semiconductor Inc.
    Inventors: Young-Bo Shim, Jae-Boum Park
  • Patent number: 7609801
    Abstract: A control unit that outputs a plurality of control signals in response to the input of a plurality of counter enable signals allocated into the numerical value of a multiple of 2 is provided. An operating unit increments or decrements by a multiple of 2 in response to input of the plurality of control signals and count up-down signals.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: October 27, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jae-Boum Park, Young-Bo Shim
  • Patent number: 7596201
    Abstract: There is offered a Gray code counter with which a delay time of a critical path is reduced and a fast operation is made possible. A first Gray code bit Q0 is obtained by outputting an output signal Q0o of an RDFF 2 through an RDFF 31 to synchronize with a clock CLK. A second Gray code bit Q1 is obtained by outputting an output signal Q1o of an RDFF 2 through an RDFF 32 to synchronize with the clock CLK. A third Gray code bit Q2 is obtained by delaying an output signal Q2o of an RDFF 4 with a selection circuit 21 and outputting it through an RDFF 33 to synchronize with the clock CLK. A fourth Gray code bit Q3 is obtained by delaying an output signal Q3o of an RDFF 5 with an AND circuit 11 and a selection circuit 22 and outputting it through an RDFF 34 to synchronize with the clock CLK. Higher bits of the Gray code are similarly generated.
    Type: Grant
    Filed: February 22, 2008
    Date of Patent: September 29, 2009
    Assignee: Epson Imaging Devices Corporation
    Inventor: Norio Fujimura
  • Patent number: 7292177
    Abstract: An asynchronous counter that is capable of switching count mode includes flip-flops, and three-input single-output tri-value switches respectively provided between the adjacent pairs of the flip-flops. The tri-value switches switch among three values, namely, non-inverting outputs and inverting outputs of the flip-flops and a power supply level. Each of the tri-value switches switch among the three input signals according to two-bit control signals, and input a selected signal to a clock terminal of a subsequent flip-flop. When count mode is switched according to the control signals, a count value immediately before the mode switching is set as an initial value, and counting after the mode switching is started from the initial value.
    Type: Grant
    Filed: April 25, 2005
    Date of Patent: November 6, 2007
    Assignee: Sony Corporation
    Inventors: Yoshinori Muramatsu, Noriyuki Fukushima, Yoshikazu Nitta, Yukihiro Yasui
  • Patent number: 7203265
    Abstract: A M by N bit synchronous counter for use in advanced applications is provided. The M by N bit synchronous counter comprises an M by N register configured to receive and store data corresponding to at least one word integrated with a N bit counter configured to sequentially count out a selected word of data from the M by N register. The present design replaces a single counter latch circuit with a plurality or stack of selectable latches and employs combined load/store logic and counter controls.
    Type: Grant
    Filed: June 16, 2005
    Date of Patent: April 10, 2007
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Frederick A. Perner
  • Patent number: 7142543
    Abstract: A digital counter allows the provision of start and stop values in order to allow it to be configurable to any length. The counter rolls over to zero at a maximum value and proceeds to count until it reaches an indicated stop count. At that point, it proceeds to the start count and continues counting. The counter counts half bytes of a cell of data for transmission to and from a multiport DRAM in accordance with communication protocols, such as asynchronous transfer mode (ATM.
    Type: Grant
    Filed: May 1, 2001
    Date of Patent: November 28, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Christopher K. Morzano
  • Patent number: 7092479
    Abstract: Ripple counter circuits in integrated circuit devices can have fast terminal count capability. A terminal count circuit can be configured to mask selected unstable counter bits generated by a ripple counter circuit using an indication that a terminal state of the ripple counter circuit has been reached. Related methods are also disclosed.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: August 15, 2006
    Assignee: Integrated Device Technology, Inc.
    Inventors: David Reid, Timothy Gillespie
  • Patent number: 6952121
    Abstract: Circuits, devices and methods are provided for dividing a fast pulse signal by an integer M. A dual modulus prescaler receives input pulses, counts them, and generates one prescaled pulse for every Qth input pulse. Q is a division modulus, and has a different value depending on a modulus control signal. When the prescaler generates a prescaled pulse from an input pulse, it ignores the modulus control signal at least until the onset of a next input pulse. A program counter generates a reset signal when the prescaler receives the Mth input pulse. A swallow counter then changes the modulus control signal to a different value, and the prescaler starts dividing by a different modulus. Even if the prescaler had already received the onset of the next input pulse, it accounts for it properly, for dividing with the different modulus.
    Type: Grant
    Filed: November 20, 2003
    Date of Patent: October 4, 2005
    Assignee: National Semiconductor Corporation
    Inventor: Ha C. Vu
  • Patent number: 6882699
    Abstract: An increasing monotonic counter over n bits formed as an integrated circuit, including an assembly of 2n+1?(n+2) irreversible counting cells distributed in at least n groups of 2p?1 counting cells, where p designates the group rank, and at least n?1 parity calculators, each calculator providing a bit of rank p, increasing from the most significant bit of the result count, taking into account the states of the cells of the group of same rank.
    Type: Grant
    Filed: October 27, 2003
    Date of Patent: April 19, 2005
    Assignee: STMicroelectronics S.A.
    Inventors: Luc Wuidart, Claude Anguille
  • Patent number: 6795000
    Abstract: A counter circuit is provided which is particularly suitable for controlling cyclical events. The counter consists of a chain of logic elements 160, 167, 164 which sequentially pass a ‘1’ along the chain in response to a clock signal. Each element is also responsive to a respective select signal and, if selected, behaves like a latch, whereas if unselected it behaves as if it were not there.
    Type: Grant
    Filed: October 18, 2001
    Date of Patent: September 21, 2004
    Assignee: Analog Devices, Inc.
    Inventors: Derek John Hummerston, Nicola Mary O'Byrne, Michael A. Byrne
  • Patent number: 6784929
    Abstract: A programmable two-dimensional timing generator according to the invention employs a clock generator (102) and a user-defined two-stage waveform generator (106, 108). A single static random access memory (SRAM) (112) stores a user-defined waveform control word for both waveform generator control units. The SRAM data is entered via the host controller external data bus. A single waveform control word may be used to control both waveform generators.
    Type: Grant
    Filed: August 20, 1999
    Date of Patent: August 31, 2004
    Assignee: Infineon Technologies North America Corp.
    Inventor: Tai-Ming Chen
  • Patent number: 6731176
    Abstract: The present invention provides a synthesizer having an efficient lock detect signal generator, an extended range VCO that can operate within any one of a plurality of adjacent characteristic curves defined by a plurality of adjacent regions, and a divide circuit implemented using only a single counter along with a decoder. This allows for a method of operating the synthesizer, methods of establishing or reestablishing a lock condition using the extended range VCO, and a method of designing a plurality of divide circuits which each use the same single counter and each use a different decoder.
    Type: Grant
    Filed: March 13, 2002
    Date of Patent: May 4, 2004
    Assignee: Atheros Communications, Inc.
    Inventors: David K. Su, Chik Patrick Yue, David J. Weber, Masound Zargari
  • Patent number: 6690525
    Abstract: A high-speed programmable synchronous counter is disclosed. The high speed counter includes a most-significant-bit counter synchronized with a least-significant bit counter. The least-significant-bit counter is programmed to an initial state and configured to decrement a state with each pulse of a clock wave. The least-significant-bit counter provides an output signal when the least-significant-bit counter has a zero-count state. The most-significant-bit counter decrements when the least-significant-bit counter has a zero-count state and provides an output signal when the least-significant-bit counter has a zero-count state. A counter output pulse is generated and the high-speed counter is reset to the initial state when both the least-significant bit counter and the most-significant bit counter have a zero-count state.
    Type: Grant
    Filed: May 25, 2001
    Date of Patent: February 10, 2004
    Assignee: Infineon Technologies AG
    Inventors: Michael A. Ruegg, Sasan Cyrusian
  • Patent number: 6566918
    Abstract: A divide-by-N clock divider circuit adds little additional delay on the clock path. N can be any integer, and the value of N does not affect the clock path delay. The divide-by-N clock divider circuits of the invention include a control circuit and a logical NOR circuit, where the control circuit is clocked by an input clock signal and the NOR circuit combines the output signal of the control circuit with the input clock signal. The control circuit acts as a filter, selecting pulses from the input clock signal to be passed to the output terminal. By selecting one out of every N input clock pulses, a divide-by-N clock divider is implemented. Because no decode logic is included in the clock path, the through-delay of the clock divider circuit is small. In some embodiments, the value of N is programmable. In some embodiments, optional duty cycle correction is available.
    Type: Grant
    Filed: August 2, 2002
    Date of Patent: May 20, 2003
    Assignee: Xilinx, Inc.
    Inventor: Andy T. Nguyen
  • Publication number: 20030007591
    Abstract: The novel frequency divider has an adjustable divider ratio. Such circuits are subject to demands for ever higher clock frequencies. The circuit generates the output signal in a blockwise manner and converts it into a sequential signal in a parallel-serial converter on the output side and outputs it in a bitwise manner. As a result, the essential part of the frequency divider circuit can be operated with a slower frequency than the input frequency, which in turn enables higher input frequencies.
    Type: Application
    Filed: July 22, 2002
    Publication date: January 9, 2003
    Inventor: Josef Holzle
  • Patent number: 6501816
    Abstract: The present invention is a method and system for a fully programmable modulus pre-scaler. In one embodiment, the pre-scaler is a cascade of fully programmable divide-by-⅔ sections. A fully programmable divide-by-⅔ section includes a state machine and a control circuit. The state machine generates a modulus control output synchronously with a clock signal in response to a modulus control input and a programming signal. The state machine has a plurality of states corresponding to a ⅔ divider. The control circuit is coupled to the state machine to generate the programming signal to the state machine in response to a programming word for a frequency divider.
    Type: Grant
    Filed: June 7, 2001
    Date of Patent: December 31, 2002
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Konstantin Kouznetsov, Daniel Linebarger
  • Publication number: 20020167359
    Abstract: A phase-locked loop (PLL) includes a down counter having a detection circuit configured to determine when the counter reaches its terminal count. The down counter also includes a control line configured to alter the terminal count detected by the detection circuit by an off-set.
    Type: Application
    Filed: May 14, 2001
    Publication date: November 14, 2002
    Inventors: Eric L. Unruh, Scott G. Gibbons
  • Patent number: 6329855
    Abstract: A frequency synthesizer has a voltage controlled oscillator to generate a oscillation signal of a frequency corresponding to a control voltage, a divider to divide the oscillation signal and to generate a dividing signal, a reference signal oscillator to generate a reference signal, a phase comparator to obtain a phase error between the reference signal and the dividing signal, and a filter to smooth the comparison result of the phase comparator and generate the control voltage, in which the divider comprises a swallow counter which times a switching time of a number of dividings, a prescaler to divide the oscillation signal by the number of dividings corresponding to the switching time timed with the swallow counter, a variable divider to divide a dividing result of the prescaler by a number of dividings set by a user, and a dividing number change controller to change a relation between the number of dividings and a switching time of the numbers of dividings in the prescaler.
    Type: Grant
    Filed: June 13, 2000
    Date of Patent: December 11, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Horie
  • Patent number: 6320927
    Abstract: It is an object of the present invention to make it possible to optionally configure various types of electronic counters. Therefore, the present invention is provided with a one-chip microcomputer 12 having a built-in ROM 13 and RAM 14 to write data corresponding to a variable on a program input through a communication port 10 and an interface 11 in the RAM 14.
    Type: Grant
    Filed: April 19, 2000
    Date of Patent: November 20, 2001
    Assignee: Koyo Electronics Industries Co., LTD
    Inventors: Yoshihiro Endo, Yuichi Hoshino
  • Patent number: 6314524
    Abstract: An interval timer for timing multiple repetitive timing intervals. A single large clock register increments ticks of a high-speed clock. Successive previously-stored timing values are loaded into a single compare register which is preferably of equivalent length to the clock register. A comparator monitors the clock register's current value and compares it with the timing value currently loaded in the compare register. As the clock register's value reaches the current timing value in the compare register, an alert signal is generated and sent out to activate a particular timed operation identified by an event ID (“EID”) associated with the timing value in the compare register. The current timing value in the compare register is then discarded, and the next timing value in sequence is retrieved into the compare register. A repeat flag is carried with each timing value and associated EID.
    Type: Grant
    Filed: March 18, 1999
    Date of Patent: November 6, 2001
    Assignee: Intervoice Limited Partnership
    Inventor: Ellis K. Cave
  • Patent number: 6263450
    Abstract: The programmable timer for use in a microprocessor has a counter and a reset register each connected to a databus of the microprocessor, and a first comparator for comparing the counter against the reset register in providing the result of the comparison at a first comparison output. The counter includes a clock signal input for counting clock pulses. The counter may be reset to a reset value via a reset input provided on the counter. The reset register may receive and store a digital value from the microprocessor. The first comparison output is connected to the reset input in order to reset the counter when the counter reaches a count greater than or equal to the value stored in the reset register thereby providing a periodic signal at the first comparison output. The programmable timer may operate in various modes including, an interval timing mode, a PWM encode mode and a pulse timing mode.
    Type: Grant
    Filed: November 16, 1998
    Date of Patent: July 17, 2001
    Assignee: Celestica North America Inc.
    Inventor: Myke Predko
  • Patent number: 6157695
    Abstract: A loadable counter circuit which is able to perform multiple contiguous counts. The loadable counter circuit uses a counter for monitoring a number of specified events. A data storage device is coupled to the counter for loading the counter with counter values for each of the contiguous counts. A control logic circuit is coupled to the counter and to the data storage circuit for loading the counter and the data storage device with the counter values.
    Type: Grant
    Filed: October 26, 1998
    Date of Patent: December 5, 2000
    Assignee: Microchip Technology, Inc.
    Inventor: Paul Barna
  • Patent number: 6133796
    Abstract: A programmable dividing circuit comprises a first plurality N of similar transistor stages connected in a divide-by-N sequence, wherein N is an odd integer, the transistor stages being configured so that when an output of the last stage is supplied to a first stage in the sequence, the dividing circuit operates as a divide-by-N circuit in which an output signal is generated which has one cycle for every N cycles of a clock signal applied to the transistor stages.
    Type: Grant
    Filed: December 23, 1998
    Date of Patent: October 17, 2000
    Assignee: STMicroelectronics Limited
    Inventor: Trevor Monk
  • Patent number: 6114915
    Abstract: Method and circuitry for a frequency synthesizer having wide operating frequency range. The frequency synthesizer uses multiple programmable loadable counters in a phase-locked loop arrangement to generate any combination of clock frequencies based on user programmed values. In a specific embodiment of the invention, the phase-locked loop includes a voltage-controlled oscillator with a built-in programmable phase shift. The present invention further provides a preferred embodiment for a high speed loadable down counter for use in the frequency synthesizer.
    Type: Grant
    Filed: March 23, 1999
    Date of Patent: September 5, 2000
    Assignee: Altera Corporation
    Inventors: Joseph Huang, Xiaobao Wang, Chiakang Sung, Bonnie I. Wang, Khai Nguyen, Wayne Yeung, In Whan Kim
  • Patent number: 6094100
    Abstract: Disclosed herein is a fractional N-type PLL frequency synthesizer apparatus. A fractional N-type control circuit employed therein for varying N values for each reference cycle is constructed of a combination of a frequency divider (comprising D flip-flops) and a logic circuit (comprising an exclusive OR circuit, AND circuits and an OR circuit), taking the timing provided to output a carry signal into consideration in advance. Owing to such a construction, the fractional N-type PLL frequency synthesizer apparatus can be activated with low noise and can provide a short lockup time.
    Type: Grant
    Filed: November 25, 1998
    Date of Patent: July 25, 2000
    Assignee: Sony Corporation
    Inventors: Yasunobu Kamikubo, Masanobu Onizuka
  • Patent number: 6072338
    Abstract: A pulse width determining device includes a down counter for counting down from a first initial count value reloaded thereinto. If the down counter underflows, it can start counting down from a second initial count value reloaded thereinto as needed. Every time the device receives an input pulse, a count clock control circuit can set a period of time during which it can generate and furnish count clock pulses to the down counter, according to the pulse width of the input pulse. The device can determine whether or not the pulse width of the input pulse is in a predetermined range of pulse widths according to a relation between timing with which the down counter underflows and the time period during which the count clock pulses are generated.
    Type: Grant
    Filed: June 11, 1998
    Date of Patent: June 6, 2000
    Assignees: Mitsubishi Electric Engineering Company Limited, Mitsubishi Denki Kabushiki Kaisha
    Inventor: Taiki Nishiuchi
  • Patent number: 6072849
    Abstract: A programmable n stage shift counter divider circuit includes a plurality of n flip-flops arranged in cascade from a first stage to an nth stage. The data inputs of each of the flip flops are coupled with the output of the next preceding stage through corresponding OR gates. A source of preload signals is coupled with the second inputs of the OR gates; and a combined trap detector and terminal count detector has inputs coupled with the outputs of the last n-1 stages of the shift counter circuit and an output coupled with the source of pre-load signals to operate it.
    Type: Grant
    Filed: August 4, 1998
    Date of Patent: June 6, 2000
    Assignee: VLSI Technology, Inc.
    Inventor: D. C. Sessions
  • Patent number: 6057719
    Abstract: A programmable, self-resetting divider includes a modified Linear Feedback Shift Register (LFSR) counter that starts in an initial state and increments through a count range. The self-resetting divider also includes a reset circuit that detects a pre-selected final state of the modified LFSR counter, provides an output signal in response to the detecting of the final state, and provides a reset signal to the modified LFSR counter in response to the detecting of the final state.
    Type: Grant
    Filed: June 5, 1998
    Date of Patent: May 2, 2000
    Assignee: International Business Machines Corporation
    Inventors: John S. Austin, Ram Kelkar
  • Patent number: 6026140
    Abstract: A ripple counter becomes programmable by use of intervening circuitry selectively inhibiting state transitions according to an initial programming step. The illustrated embodiment of a programmable ripple counter includes a forward chain of count registers operating generally in the fashion of a ripple counter, but selectively inhibited by an intervening control signal originating from a reverse chain of control registers. By selectively controlling the number of state transitions inhibited and by selectively controlling the number of registers participating in the counting operation, a low power general purpose programmable ripple counter results.
    Type: Grant
    Filed: April 21, 1998
    Date of Patent: February 15, 2000
    Assignee: Seiko Communications Systems Inc.
    Inventor: Jeffrey R. Owen
  • Patent number: 5978437
    Abstract: A counting system with a dynamic maximum count includes a counter, match logic, and a maximum count controller. The counter has a present count register, a clock (or event indicator) event input, and a reset input. The maximum count controller can be programmed with an adjustable maximum count stored in a maximum count register. The match logic includes a count-wide AND gate fed by NAND gates. Each NAND gate has an inverted input coupled to a respective bit position of the present count register and an uninverted input coupled to a respective bit position of the maximum count register. The function of the match logic is to indicate a match whenever the present count has a 1 at every bit position that the maximum count has a 1, irrespective of the present count values at bit positions at which the maximum count has 0s. Thus, imperfect matches are provided for. The values of the imperfect matches always exceed the values of perfect matches, so they are not usually encountered.
    Type: Grant
    Filed: December 30, 1997
    Date of Patent: November 2, 1999
    Assignee: VLSI Technology, Inc.
    Inventor: Timothy A. Pontius
  • Patent number: 5907591
    Abstract: A digital counter allows the provision of start and stop values in order to allow it to be configurable to any length. The counter rolls over to zero at a maximum value and proceeds to count until it reaches an indicated stop count. At that point, it proceeds to the start count and continues counting. The counter counts half bytes of a cell of data for transmission to and from a multiport DRAM in accordance with communication protocols, such as asynchronous transfer mode (ATM.
    Type: Grant
    Filed: July 25, 1997
    Date of Patent: May 25, 1999
    Assignee: Micron Technology, Inc.
    Inventor: Christopher K. Morzano
  • Patent number: 5892405
    Abstract: Disclosed herein is a fractional N-type PLL frequency synthesizer apparatus. A fractional N-type control circuit employed therein for varying N values for each reference cycle is constructed of a combination of a frequency divider (comprising D flip-flops) and a logic circuit (comprising an exclusive OR circuit, AND circuits and an OR circuit), taking the timing provided to output a carry signal into consideration in advance. Owing to such a construction, the fractional N-type PLL frequency synthesizer apparatus can be activated with low noise and can provide a short lockup time.
    Type: Grant
    Filed: April 21, 1997
    Date of Patent: April 6, 1999
    Assignee: Sony Corporation
    Inventors: Yasunobu Kamikubo, Masanobu Onizuka
  • Patent number: 5859890
    Abstract: A dual-modulus prescaler (100) has improved performance for high-speed operation. A timing signal is developed from a flip flop circuit (106) two and one-half clock cycles before the last stage of the prescaler is clocked. The timing signal is used to produce a selector signal to gate a multiplexer (112). Because of the early generation of the timing signal, the multiplexer selection process is removed from the critical path. The remaining delay through the multiplexer is minimal to minimize the critical path of the prescaler.
    Type: Grant
    Filed: February 26, 1997
    Date of Patent: January 12, 1999
    Assignee: Motorola, Inc.
    Inventors: Carl L. Shurboff, Matsuo M. Marti
  • Patent number: 5842006
    Abstract: A counter circuit with multiple registers for eliminating reprogramming delays and for providing seamless switching between timing signals. In a first embodiment, two registers are preloaded with values and control logic chooses between the registers for loading a counter. The counter asserts a terminal count signal to output logic, which correspondingly asserts a convert pulse to an analog measuring circuit. The control logic receives start and stop signals and the terminal count signal, where the control logic controls operation accordingly. In this manner, a delay value is initially loaded into the counter to provide an initial delay period upon receiving the start signal, and then a scan rate value is continually loaded into the counter from another register thereafter for defining the scan rate until the start signal is received.
    Type: Grant
    Filed: September 6, 1995
    Date of Patent: November 24, 1998
    Assignee: National Instruments Corporation
    Inventors: Audrey F. Harvey, Jaffar Shah, Joseph Peck, Kosta Ilic
  • Patent number: 5748949
    Abstract: A counter (200) generates signals which have an average period of a non-integer multiple of an input clock period. Through the use of this non-integer multiple period, non-integer division operations are executed and used in circuits such as pulse width modulators (800) and phase lock loops (900). Additionally, when the counter (200') is used with a Gray coded counter, the average duty cycle of all bits is exactly equal to 50%.
    Type: Grant
    Filed: July 2, 1996
    Date of Patent: May 5, 1998
    Assignee: Motorola Inc.
    Inventor: Thomas K. Johnston
  • Patent number: 5740220
    Abstract: Microprocessor with registered clock counting for at a predetermined count producing a command signal of adjustable shape, and a hierarchical interrupt system for use therewith.A microprocessor comprises registered counting means that counts clock pulses. Upon attainment of a predetermined count it generates a command signal. Furthermore, it has a presettable input section that recurrently receives a variable preset count for downcounting, a secondary count section that is fed by said command signal output for counting successive command signals and under control of attainment of a predetermined count generates a secondary command signal on a secondary output. Next, a programmable registered pulse shaper mechanism under control of said secondary command signal executes serial shifting and outputs a shaped version of the secondary command signal. The above counting means is also associated to a parametrizeable interrupt priority mechanism.
    Type: Grant
    Filed: November 7, 1996
    Date of Patent: April 14, 1998
    Assignee: U.S. Philips Corporation
    Inventor: Frederik Zandveld
  • Patent number: 5737381
    Abstract: The invention provides a counting device and a direct memory access system using the counting device. In the counting device, a carry/borrow signal to be supplied from a predetermined one-bit counter among a plurality of one-bit counters to another one-bit counter in the subsequent stage is inputted to an input/cutoff element such as an AND circuit. The input/cutoff element is also supplied with a control signal for controlling the input/cutoff of the carry/borrow signal. Thus, the range of the values to be counted can be changed.
    Type: Grant
    Filed: June 21, 1996
    Date of Patent: April 7, 1998
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Semiconductor Software Co., Ltd.
    Inventors: Takehiko Shimomura, Nobusuke Abe, Yoshikazu Satoh