Abstract: A unique timing system is provided which allows for a user to program timing events with variable periods and edges from a fixed frequency clock, and having resolution greater than that of the fixed reference frequency. Delay elements, which are inherently expensive, inaccurate, and require repeated calibration, are minimized.

Abstract: A programmable counter/timer is responsive to signals on a data line for producing signals on one or more output lines and includes a counter connected to the data line, a comparator connected to said counter for producing a control signal when said counter reaches a stored preselected value, and a qualification unit connected to the comparator, the qualification unit having a register for storing a logic state. The qualification unit is responsive to the control signal and the stored logic state for generating a signal on selected output lines when the counter reaches the predetermined stored value.

Abstract: A programmable divide-by-N counter employs a plurality of speed enhancement techniques to provide an overall operational speed corresponding to the speed at which a single-clocked flip-flop is capable of being toggled. The counter configuration provides flexibility in selecting the value of N, the programmable divisor, as well as the possibility of increasing the length the counting chain without producing a reduction in overall operational speed. The speed enhancement techniques are primarily located in the reset logic portion of the counter. A key aspect utilized through-out the overall circuit is that critical signal propagation paths in terms of speed of operation present no more than four gate delay intervals in total response time.

Abstract: Method and apparatus for rapid, low-jitter acquisition of a clock signal at a serial communication port. In the absence of communication over the port, and during clock acquisition, a free-running clock is generated for local communication. Following clock acquisition by a circuit which performs coarse phase adjustments, a simple logic network generates refined phase adjustment signals which drive a variable, nominal divide-by-32, counter so that the clock generated thereby is smoothly brought into synchronization with the acquired clock in one bit increments. In a typical application, at most 48 bit periods at the port are required to synchronize the clock, with a clock phase jitter of less than 1.1%.

Abstract: In an effort to reduce the number of "terminal legs" in highly integrated electronic circuits, two different kinds of coded signals are applied successively to the control terminals thereof, namely: binary coded signals applied in parallel and successive pulses. An evaluation is made only of pulses applied to selected terminals, and a different number of pulses is applied to the individual control terminals. The total number of pulses evaluated is counted in a counter. The counter outputs are decoded in a decoder. The binary coded signals also are decoded in a decoder, and the outputs of both decoders are combined in a selection logic so that both kinds of signals together define a control state. In this manner 3.sup.n different control states are obtained by a number n of control terminals.

Abstract: There is disclosed herein an up/down counter with a programmable terminal count. The up/down counter has a two level input structure such that new terminal counts may be written into the up/down counter asynchronously without disturbing operations of the up/down counter. Although the invention is described in the bidirectional sense, certain of the features are also applicable to unidirectional counters.

Abstract: An electronic integrator for integrating a linear voltage signal utilizes a voltage-to-frequency converter for converting the voltage to input frequency. A binary counter counts pulses of the input frequency. The binary counter generates a first operating frequency which is applied to a scaling circuit and another calibration frequency which has a much higher rate than the operating frequency. Both, however are proportional to the input frequency. The scaling circuit scales the operating frequency to a selected extent to form a counting signal. Using the double pole switch, either the calibration frequency or the counting frequency are applied to a pulse counter which is either used to integrate the input voltage signal by counting up pulses of the scaled counting signal, or the integrator can be calibrated using the calibration frequency which quickly increments the pulse counter.

Abstract: An integrated D flip-flop circuit including a plurality of inverter gates produces an output signal having a frequency that is equal to the frequency of an applied alternating input signal divided by a predetermined divide ratio wherein the improvement comprises an additional inverter gate that has an output connected to a predetermined one of the interconnected inverter gates and is responsive to a divide inhibit signal being applied to an input thereof for changing the divide ratio of the D flip-flop circuit.

Abstract: A system to provide warning whenever unreliable data is being received by an airborne receiver for a microwave landing system. The received data is tested against certain criteria to determine validity. The received data is also tested to determine whether it was received via a direct path or via a multipath reflection. A validity counter records the percentage of valid data received. A multipath counter records the length of time data is received via direct path relative to the length of time data is received via multipath. Both counters control warning flags to cause a warning to be generated whenever the counter contents are below threshold values. The validity counter is set to an upper limit when its count crosses the threshold in a positive direction and is set to a negative limit when its count crosses the threshold in a negative direction.

Abstract: A digital-to-analog converter system for converting a digital input signal having parallel words, each word including multi-bit groups of weighted significance, and which is provided at an input word rate of W Hz, is disclosed. The digital-to-analog converter system (10, 100, 200) includes pulse generating circuitry (11, 13, 111, 113, 211, 213) responsive to a first multi-bit group and a second multi-bit group of the digital input words for providing (a) a first pulse modulated signal as a function of the value of the first multi-bit group and (b) a second pulse modulated signal as a function of the value of the second multi-bit group; weighting elements (15, 19, 115, 119, 215, 219) for weighting the first and second pulse modulated signals as a function of the relative weighted significance of the first and second multi-bit groups; and output circuitry (20, 120, 220) for summing and filtering the weighted signals to provide an analog output signal that is representative of the digital input signal.

Abstract: A frequency synthesizer which has a constant resolution over an octave frequency range is disclosed. The frequency synthesizer has a presettable high speed counter, a low speed counter, an adjusting counter, and a count selector. The low speed counter provides a first output signal whose frequency is rapidly alternated between two closely-spaced frequencies so that the average frequency of the output signal is the desired frequency. The adjusting counter determines the period of time that each of the closely-spaced frequencies is present at the output. The count selector determines the frequency of each of the two closely-spaced frequencies. The frequency synthesizer also has a phase splitter and provides a second output signal which is also of the desired frequency but which is phase-shifted by ninety degrees from the first output signal.

Abstract: A binary ripple counter having exclusive OR coupling elements between the counter bistables for use in a digital delay by events circuit of a display device such as an oscilloscope. The counter is programmable.

Abstract: When the frequency dividing ratio of a programmable divider in a phase locked loop is controlled by an up/down counter, the designing of a system can be simplified by reducing the number of control lines connected to a microprocessor as much as possible. An up/down counter control circuit of the present invention comprises a timing control means to which a latch signal, a data and a clock signal are supplied, a data memory means and an up/down counter and is characterized in that under the control of the timing control means, in the data latch mode, a first level (0 or 1) of the latch signal is detected and in synchronism with the clock signal that data is latched in the data memory means, while in the up/down mode, a second level (1 or 0) of the latch signal is detected and the content of the up/down counter is changed in response to the level of the data synchronized with the clock signal.

Abstract: An adjustable ratio divider comprises a controllable gate connected in series with a divider for passing a clock signal in pulse form whose frequency is to be divided. A means is provided for controlling the gate to subtract a selectable number (including zero) of clock pulses from the clock signal to control the division ratio of the divider.

Abstract: A high speed programmable prescaler has an input divider that divides an input stream of clock pulses by either 2 or upon command by 3. Connected to the input divider is a plurality of dividers that are electrically cascaded together from a first member to last member with each member of the plurality of dividers being capable of dividing the clock pulses applied to it by either 2 or upon command by 3. A prescaler selects either 2 or 3 for dividing the input stream of clock pulses so that number of clock pulses necessary to obtain an output pulse can be represented by the equation of 2.sup.N +M where N is the number of members of the plurality of dividers and M is the control number having a range of 0 to 2.sup.N -1.The critical path delays are minimized by using a flip-flop in the input divider to divide by 2 and then on command shifting the output of the flip-flop by 180.degree. to obtain the divide by 3 function.

Abstract: A programmable high resolution timing system includes a selectable modulus prescaler counter. In one embodiment a high frequency clock is coupled to a prescaler counter which provides an output signal every predetermined number of clock pulses. The prescaler is coupled to a period counter which provides a period signal after a predetermined number of prescaler output signal pulses. The prescaler and period counter are coupled to a memory which stores data corresponding to the selected modulus of the prescaler and the number of counts by which the period counter output signal is to be delayed. The period resolution is thus made substantially equal to the resolution of the high frequency clock by varying the prescaler modulus at programmable intervals.

Abstract: A digital device generating a frequency-modulated signal. The device comprises a programmable divider which divides the frequency f.sub.H of the clock by a variable integer N supplied by a control circuit. The output pulse signal of the frequency divider initiates the supplying of the next value of N by the control circuit. A shaping circuit brings the pulse signal into the form of a signal whose half-cycles successively have a duration equal to an integer multiple N of the clock period 1/f.sub.H. A supplementary circuit makes it possible to improve the precision of the modulation obtained compared with the desired phase by optionally delaying each half-cycle of the modulated signal by a fraction of the block period. The present invention is applicable to radar and telemetry.

Abstract: Apparatus is disclosed wherein the average period of a synthesized signal is a non-integral multiple of the period of a given signal. The apparatus is arranged so that a counter alternates its count between N and N+1, wherein N is a predetermined integer, in a predetermined pattern so that the average count approximates a rational non-integral value between N and N+1.

Abstract: A synchronous carry frequency divider having a series of counters wherein each pair of counters is separated by a flip-flop and wherein the last counter in the series is followed by a terminal flip-flop. The counters and the flip-flops are synchronously clocked so that the divisor ratio is increased by the number of flip-flops employed. When the terminal flip-flop is toggled by the last counter a terminal count signal and a preset enable signal are simultaneously achieved without the delays associated with terminal count decode networks.

Abstract: A programmable counter system of the swallow operation type using binary counters is disclosed. The counter comprises a prescaler for frequency dividing an input signal by a frequency division factor "2.sup.n -1" or "2.sup.n ", upper and lower order bit counters for counting down an output signal from the prescaler, a flip-flop for selecting either the frequency division factor "2.sup.n -1" or "2.sup.n " according to the logical level of the output signal of the counter A or B, and inverters for level inverting programming data and applying them to the lower order bit counter A, thereby setting a division number of the counter A to a complement of the binary code of the programming data.

Abstract: A device for determining with high accuracy the period and frequency of an input signal by taking into account the fractions of a clock signal that are normally ignored. A gate signal with an integral number of clock pulses is generated. Each fractional time is accurately measured by first and second integrators, and an up-down counter provides the difference between the fractional times for the final determination.

Abstract: The clock signal to a fine delay shift register is divided by the number of fine delay bits for application to a coarse delay shift register such that two serially connected shift registers can provide a range of delays equivalent to a shift register having a number of bits equal to the product of the bits of the two shift registers.

Abstract: A variable resolution counter is provided in which the resolution of the count decreases as the counted value increases. A set of scale control bits from the most significant bits of the counter are used to control selection of one of several prescaled signals from a prescaler. Resetting of the count value may be made conditional on the value of the count, and a flag may be provided to effectively redistribute the capacity of the counter between high and low resolution modes. A gray code of particular interest is also disclosed.

Abstract: In a transceiver, a synthesizer includes a multiposition switch which accesses various addressable memory locations in a programmable read-only memory (PROM), where the appropriate divisors are stored to cause tuning of the synthesizer to the appropriate communication channel. A zone selector switch enables grouping and easy retrievability of channels. The divisors are supplied to a single synchronous binary swallow counter which works in conjunction with a dual modulus prescaler to monitor the frequency output of the voltage controlled oscillator. In the swallow counting device, two latches receive divisor related information supplied by the PROM. When the sampled state of a single up counter reaches a first latched number, the prescaler changes the modulus. Synchronous counting then continues, without reprogramming new values. When the up counter reaches a second latched number, a predetermined frequency ratio has been achieved, and the counter is reset.

Abstract: A data separator for providing data and clock information derived from a floppy disk to a controller includes a synthetic oscillator phase-locked loop which adjusts the phase of the derived clock, thereby to tend to position data inputs within the central portion of their associated half-bit slots. The center frequency of the synthetic oscillator may be modified in accordance with prior phase adjustments to compensate for variations in the speed of the floppy disk drive.

Abstract: The swallow counter includes a two modulus prescaler which selectively divides a frequency of an input pulse according to a signal level of a control signal for producing a frequency divided signal, a first programmable counter which starts counting in response to the frequency divided signal to produce a first code signal, a second programmable counter which starts counting in response to the first code signal for producing a second code signal, a first code detector for detecting a specific code signal of the first and second code signals to produce a first pulse signal, a third programmable counter which, in response to the frequency divided signal, starts to count for producing a third code signal, a second code detector for detecting a specific bit of the third code signal for producing a second pulse signal utilized as a reset signal of the first to third programmable counters, a flip-flop circuit for selectively outputting a reset or set signal in response to the first or second pulse signal, and a per

Abstract: A unique frequency synthesizer unit for use in a data processing system I/O interface unit for providing at least one clock signal having a substantially constant frequency which can be generated in response to any one of a plurality of input clock signals each having a different frequency. The system I/O interface unit may be used, for example, to control communication between a system bus and a plurality of I/O buses having different timing and operating characteristics. The system I/O interface unit may be used, for example, to control communication between a system bus and a plurality of I/O buses having different timing and operating characteristics.

Abstract: A digital depth indicator for rotary earth drills, and particularly auger type drills, operates from the means used to lower and raise the drill. The indicator operates from either the wire or cable of a wire line hoist auger or the hydraulic fluid flow in a hydraulic Kelly hoist type machine. A rotary measuring device is provided with an incremental shaft encoder which rotates to produce a dual signal which is supplied to (1) an up/down digital counter and (2) a programmable .div.N counter, which counter supplies a .div.N pulse to the up/down digital counter. The programmable .div.N counter is provided with switches for (1) setting the apparatus to read in feet or in meters and (2) setting the program for the drilling machine type or model. The output from the up/down digital counter is fed through a display driver to a digital display showing the indicated depth in feet or meters.

Abstract: A frequency counter (20) measures and displays a plurality of frequencies appearing on input channels (22, 24, 26 and 28) of an analog circuit (30). A program switch (32) is coupled to a decoder logic circuit (34) which facilitates the operation of counter (20) in one of a plurality of selectable program modes. A steering logic circuit (36) is coupled to circuit (34) and facilitates the selection and order of the input channels (22, 24, 26 and 28) during a measurement cycle. Toggle switches (38, 40 and 42) are coupled to circuit (36) to facilitate the establishment of a sign bit, a channel order and a channel select, respectively. A channel display circuit (46) provides visual indication of the sign, channel select and channel order.

Abstract: A write-only sequence controller in which data regarding the period of time in one cycle is divided into data "1" and data "0" which are designated by the number of the clock pulse. To this end, the system is provided with ten key switches for converting the data "1" and data "0" into the number of the clock pulse and an encoder for converting the number of the clock pulse into BCD codes. The BCD codes are set in presettable counter which counts the clock pulse from a clock pulse generating circuit through gate circuits. The system is further provided with a binary counter for counting the clock pulse applied to the presettable counter, memory RAMs connected to address lines of the binary counter for memorizing data from the counter, and an EPROM for memorizing data stored in the memory RAMs. When the number of the clock pulse applied to the presettable counter and to the binary counter reaches the preset number, the gate circuits are closed.

Abstract: A frequency divider which divides clock pulses to obtain the clock frequency of a desired dividing ratio comprises a binary counter, cycle data forming circuit and inhibit circuit to which the dividing ratio is fed in the form of the dividing ratio data.The counter counts the clock pulses, and the cycle data forming circuit converts the count value of the binary counter to a cycle data in which a certain single bit only becomes a logical state "1" and the rest of the bits are a state "0". The bit which becomes "1" in the cycle data is uniquely determined by the count value. Further, each bit of the cycle data becomes "1" in proportion to the weight of the each bit. With the cycle data being thus formed, the dividing ratio data is simplified.The inhibit circuit receives the cycle data and the dividing ratio data to suspend the counting operation of the binary count if the bit of the dividing ratio data corresponding to the bit of the cycle data whose state is "1" is also "1".

Abstract: Apparatus for imparting a delay to an input signal utilizing counter means comprised of a plurality of binary coded decimal counter stages connected in cascade. The high frequency input signal applied to the counter undergoes a divide-by 10.sup.N operation wherein N equals the number of binary coded decimal stages. Preferably, the least significant stage is adapted to be selectively and periodically preset to a binary coded decimal value different from its normal reset state to either increase or reduce the number of pulses required to cause the counter stage to read a terminal count to selectively either advance or retard the phase of the reduced frequency output signal developed at the output of the counter relative to the phase of the input signal applied to the counter in accordance with a preprogrammed value set into said counter stage.

Abstract: In order to improve the operable frequency of a programmable counter circuit which serves as an N-step counter by loading an initial value N, load terminals of flip-flops of respective stages forming the counter circuit are sequentially cascade-connected via buffers and a load signal is applied to each of the load terminals from a load signal generator circuit. The load signal generator circuit includes a detector circuit which detects a specified value which is provided a short time before the initial value loading of the counter circuit and generates a detected output signal. The detected output signal is shifted by a shift register included in the load signal generator circuit which operates on the same clock signal as that which drives the counter circuit, thereby generating the load signal at the moment of the initial value loading of the counter circuit.

Abstract: A digital to analog converter utilizes a digital missing pulse detector as a time interval measuring means in which the detector includes a programmable counter, the count of which is set to correspond with the digital number or word to be converted. Clock pulses at a high frequency are applied to advance the programmable counter from a reset condition to a terminal or output condition, and the time interval produced depends upon the binary word or number set into the programmable counter. Pulses at a second lower frequency, equal to the repetition rate of the system, are applied to the input of the time interval measuring circuit; so that the output is a series of pulse width modulated pulses having a duty cycle corresponding to the binary word originally set into the programmable counter.

Abstract: An electronic trip meter for an automotive vehicle comprises a memory circuit to store sector distances between a start point and intermediate and final destinations, a distance presetting circuit to determine alarm points near to and before intermediate and final destinations, a counter to count the actual distance travelled from the last destination, a comparator to output a signal from the time when the value in the counter becomes equal to that in the distance presetting circuit until the time when the value in the counter becomes equal to that in the memory circuit, an alarm device driven by the comparator output signal, and a display device. Such an electronic trip meter displays the remaining distance to the next destination while the comparator is sending out an output signal; that is, at any intermediate points in between an alarm-point and the next destination. At other times the display shows a value representative of the total distance travelled.

Abstract: A device for determining with high accuracy the period and frequency of an input signal by taking into account the fractions of a clock signal that are normally ignored. A gate signal with an integral number of clock pulses is generated. Each fractional time is accurately measured by first and second integrators, and an up-down counter provides the difference between the fractional times for the final determination.